| David Cohen | 68e342b | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 1 | /* |
| 2 | * isph3a.h |
| 3 | * |
| 4 | * TI OMAP3 ISP - H3A AF module |
| 5 | * |
| 6 | * Copyright (C) 2010 Nokia Corporation |
| 7 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 8 | * |
| 9 | * Contacts: David Cohen <dacohen@gmail.com> |
| 10 | * Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 11 | * Sakari Ailus <sakari.ailus@iki.fi> |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| David Cohen | 68e342b | 2011-02-12 18:05:06 -0300 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #ifndef OMAP3_ISP_H3A_H |
| 19 | #define OMAP3_ISP_H3A_H |
| 20 | |
| 21 | #include <linux/omap3isp.h> |
| 22 | |
| 23 | /* |
| 24 | * ---------- |
| 25 | * -H3A AEWB- |
| 26 | * ---------- |
| 27 | */ |
| 28 | |
| 29 | #define AEWB_PACKET_SIZE 16 |
| 30 | #define AEWB_SATURATION_LIMIT 0x3ff |
| 31 | |
| 32 | /* Flags for changed registers */ |
| 33 | #define PCR_CHNG (1 << 0) |
| 34 | #define AEWWIN1_CHNG (1 << 1) |
| 35 | #define AEWINSTART_CHNG (1 << 2) |
| 36 | #define AEWINBLK_CHNG (1 << 3) |
| 37 | #define AEWSUBWIN_CHNG (1 << 4) |
| 38 | #define PRV_WBDGAIN_CHNG (1 << 5) |
| 39 | #define PRV_WBGAIN_CHNG (1 << 6) |
| 40 | |
| 41 | /* ISPH3A REGISTERS bits */ |
| 42 | #define ISPH3A_PCR_AF_EN (1 << 0) |
| 43 | #define ISPH3A_PCR_AF_ALAW_EN (1 << 1) |
| 44 | #define ISPH3A_PCR_AF_MED_EN (1 << 2) |
| 45 | #define ISPH3A_PCR_AF_BUSY (1 << 15) |
| 46 | #define ISPH3A_PCR_AEW_EN (1 << 16) |
| 47 | #define ISPH3A_PCR_AEW_ALAW_EN (1 << 17) |
| 48 | #define ISPH3A_PCR_AEW_BUSY (1 << 18) |
| 49 | #define ISPH3A_PCR_AEW_MASK (ISPH3A_PCR_AEW_ALAW_EN | \ |
| 50 | ISPH3A_PCR_AEW_AVE2LMT_MASK) |
| 51 | |
| 52 | /* |
| 53 | * -------- |
| 54 | * -H3A AF- |
| 55 | * -------- |
| 56 | */ |
| 57 | |
| 58 | /* Peripheral Revision */ |
| 59 | #define AFPID 0x0 |
| 60 | |
| 61 | #define AFCOEF_OFFSET 0x00000004 /* COEF base address */ |
| 62 | |
| 63 | /* PCR fields */ |
| 64 | #define AF_BUSYAF (1 << 15) |
| 65 | #define AF_FVMODE (1 << 14) |
| 66 | #define AF_RGBPOS (0x7 << 11) |
| 67 | #define AF_MED_TH (0xFF << 3) |
| 68 | #define AF_MED_EN (1 << 2) |
| 69 | #define AF_ALAW_EN (1 << 1) |
| 70 | #define AF_EN (1 << 0) |
| 71 | #define AF_PCR_MASK (AF_FVMODE | AF_RGBPOS | AF_MED_TH | \ |
| 72 | AF_MED_EN | AF_ALAW_EN) |
| 73 | |
| 74 | /* AFPAX1 fields */ |
| 75 | #define AF_PAXW (0x7F << 16) |
| 76 | #define AF_PAXH 0x7F |
| 77 | |
| 78 | /* AFPAX2 fields */ |
| 79 | #define AF_AFINCV (0xF << 13) |
| 80 | #define AF_PAXVC (0x7F << 6) |
| 81 | #define AF_PAXHC 0x3F |
| 82 | |
| 83 | /* AFPAXSTART fields */ |
| 84 | #define AF_PAXSH (0xFFF<<16) |
| 85 | #define AF_PAXSV 0xFFF |
| 86 | |
| 87 | /* COEFFICIENT MASK */ |
| 88 | #define AF_COEF_MASK0 0xFFF |
| 89 | #define AF_COEF_MASK1 (0xFFF<<16) |
| 90 | |
| 91 | /* BIT SHIFTS */ |
| 92 | #define AF_RGBPOS_SHIFT 11 |
| 93 | #define AF_MED_TH_SHIFT 3 |
| 94 | #define AF_PAXW_SHIFT 16 |
| 95 | #define AF_LINE_INCR_SHIFT 13 |
| 96 | #define AF_VT_COUNT_SHIFT 6 |
| 97 | #define AF_HZ_START_SHIFT 16 |
| 98 | #define AF_COEF_SHIFT 16 |
| 99 | |
| 100 | /* Init and cleanup functions */ |
| 101 | int omap3isp_h3a_aewb_init(struct isp_device *isp); |
| 102 | int omap3isp_h3a_af_init(struct isp_device *isp); |
| 103 | |
| 104 | void omap3isp_h3a_aewb_cleanup(struct isp_device *isp); |
| 105 | void omap3isp_h3a_af_cleanup(struct isp_device *isp); |
| 106 | |
| 107 | #endif /* OMAP3_ISP_H3A_H */ |