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Archit Taneja9262e5a2013-10-16 02:36:45 -03001/*
2 * Copyright (c) 2013 Texas Instruments Inc.
3 *
4 * David Griego, <dagriego@biglakesoftware.com>
5 * Dale Farnsworth, <dale@farnsworth.org>
6 * Archit Taneja, <archit@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 */
12
13#ifndef __TI_VPDMA_H_
14#define __TI_VPDMA_H_
15
Nikhil Devshatwarc1cd15e2016-11-18 21:20:29 -020016#define VPDMA_MAX_NUM_LIST 8
Archit Taneja9262e5a2013-10-16 02:36:45 -030017/*
18 * A vpdma_buf tracks the size, DMA address and mapping status of each
19 * driver DMA area.
20 */
21struct vpdma_buf {
22 void *addr;
23 dma_addr_t dma_addr;
24 size_t size;
25 bool mapped;
26};
27
28struct vpdma_desc_list {
29 struct vpdma_buf buf;
30 void *next;
31 int type;
32};
33
34struct vpdma_data {
35 void __iomem *base;
36
37 struct platform_device *pdev;
38
Nikhil Devshatwar4e4676d2016-11-18 21:20:23 -020039 spinlock_t lock;
Nikhil Devshatwarc1cd15e2016-11-18 21:20:29 -020040 bool hwlist_used[VPDMA_MAX_NUM_LIST];
41 void *hwlist_priv[VPDMA_MAX_NUM_LIST];
Archit Tanejab2c94722014-03-13 08:44:04 -030042 /* callback to VPE driver when the firmware is loaded */
43 void (*cb)(struct platform_device *pdev);
Archit Taneja9262e5a2013-10-16 02:36:45 -030044};
45
Archit Tanejab4fcdaf2013-12-12 05:36:04 -030046enum vpdma_data_format_type {
47 VPDMA_DATA_FMT_TYPE_YUV,
48 VPDMA_DATA_FMT_TYPE_RGB,
49 VPDMA_DATA_FMT_TYPE_MISC,
50};
51
Archit Taneja9262e5a2013-10-16 02:36:45 -030052struct vpdma_data_format {
Archit Tanejab4fcdaf2013-12-12 05:36:04 -030053 enum vpdma_data_format_type type;
Archit Taneja9262e5a2013-10-16 02:36:45 -030054 int data_type;
55 u8 depth;
56};
57
58#define VPDMA_DESC_ALIGN 16 /* 16-byte descriptor alignment */
Archit Tanejaa51cd8f2013-12-03 08:51:13 -030059#define VPDMA_STRIDE_ALIGN 16 /*
60 * line stride of source and dest
61 * buffers should be 16 byte aligned
62 */
Archit Taneja9262e5a2013-10-16 02:36:45 -030063#define VPDMA_DTD_DESC_SIZE 32 /* 8 words */
64#define VPDMA_CFD_CTD_DESC_SIZE 16 /* 4 words */
65
66#define VPDMA_LIST_TYPE_NORMAL 0
67#define VPDMA_LIST_TYPE_SELF_MODIFYING 1
68#define VPDMA_LIST_TYPE_DOORBELL 2
69
70enum vpdma_yuv_formats {
71 VPDMA_DATA_FMT_Y444 = 0,
72 VPDMA_DATA_FMT_Y422,
73 VPDMA_DATA_FMT_Y420,
74 VPDMA_DATA_FMT_C444,
75 VPDMA_DATA_FMT_C422,
76 VPDMA_DATA_FMT_C420,
Benoit Parroteaa68082016-11-18 21:20:31 -020077 VPDMA_DATA_FMT_YCR422,
Archit Taneja9262e5a2013-10-16 02:36:45 -030078 VPDMA_DATA_FMT_YC444,
Benoit Parroteaa68082016-11-18 21:20:31 -020079 VPDMA_DATA_FMT_CRY422,
80 VPDMA_DATA_FMT_CBY422,
81 VPDMA_DATA_FMT_YCB422,
Archit Taneja9262e5a2013-10-16 02:36:45 -030082};
83
84enum vpdma_rgb_formats {
85 VPDMA_DATA_FMT_RGB565 = 0,
86 VPDMA_DATA_FMT_ARGB16_1555,
87 VPDMA_DATA_FMT_ARGB16,
88 VPDMA_DATA_FMT_RGBA16_5551,
89 VPDMA_DATA_FMT_RGBA16,
90 VPDMA_DATA_FMT_ARGB24,
91 VPDMA_DATA_FMT_RGB24,
92 VPDMA_DATA_FMT_ARGB32,
93 VPDMA_DATA_FMT_RGBA24,
94 VPDMA_DATA_FMT_RGBA32,
95 VPDMA_DATA_FMT_BGR565,
96 VPDMA_DATA_FMT_ABGR16_1555,
97 VPDMA_DATA_FMT_ABGR16,
98 VPDMA_DATA_FMT_BGRA16_5551,
99 VPDMA_DATA_FMT_BGRA16,
100 VPDMA_DATA_FMT_ABGR24,
101 VPDMA_DATA_FMT_BGR24,
102 VPDMA_DATA_FMT_ABGR32,
103 VPDMA_DATA_FMT_BGRA24,
104 VPDMA_DATA_FMT_BGRA32,
105};
106
Benoit Parrotee1c0292016-11-18 21:20:42 -0200107enum vpdma_raw_formats {
108 VPDMA_DATA_FMT_RAW8 = 0,
109 VPDMA_DATA_FMT_RAW16,
110};
111
Archit Taneja9262e5a2013-10-16 02:36:45 -0300112enum vpdma_misc_formats {
113 VPDMA_DATA_FMT_MV = 0,
114};
115
116extern const struct vpdma_data_format vpdma_yuv_fmts[];
117extern const struct vpdma_data_format vpdma_rgb_fmts[];
Benoit Parrotee1c0292016-11-18 21:20:42 -0200118extern const struct vpdma_data_format vpdma_raw_fmts[];
Archit Taneja9262e5a2013-10-16 02:36:45 -0300119extern const struct vpdma_data_format vpdma_misc_fmts[];
120
121enum vpdma_frame_start_event {
122 VPDMA_FSEVENT_HDMI_FID = 0,
123 VPDMA_FSEVENT_DVO2_FID,
124 VPDMA_FSEVENT_HDCOMP_FID,
125 VPDMA_FSEVENT_SD_FID,
126 VPDMA_FSEVENT_LM_FID0,
127 VPDMA_FSEVENT_LM_FID1,
128 VPDMA_FSEVENT_LM_FID2,
129 VPDMA_FSEVENT_CHANNEL_ACTIVE,
130};
131
Nikhil Devshatwar634271f82016-11-18 21:20:21 -0200132/* max width configurations */
133enum vpdma_max_width {
134 MAX_OUT_WIDTH_UNLIMITED = 0,
135 MAX_OUT_WIDTH_REG1,
136 MAX_OUT_WIDTH_REG2,
137 MAX_OUT_WIDTH_REG3,
138 MAX_OUT_WIDTH_352,
139 MAX_OUT_WIDTH_768,
140 MAX_OUT_WIDTH_1280,
141 MAX_OUT_WIDTH_1920,
142};
143
144/* max height configurations */
145enum vpdma_max_height {
146 MAX_OUT_HEIGHT_UNLIMITED = 0,
147 MAX_OUT_HEIGHT_REG1,
148 MAX_OUT_HEIGHT_REG2,
149 MAX_OUT_HEIGHT_REG3,
150 MAX_OUT_HEIGHT_288,
151 MAX_OUT_HEIGHT_576,
152 MAX_OUT_HEIGHT_720,
153 MAX_OUT_HEIGHT_1080,
154};
155
Archit Taneja9262e5a2013-10-16 02:36:45 -0300156/*
157 * VPDMA channel numbers
158 */
159enum vpdma_channel {
160 VPE_CHAN_LUMA1_IN,
161 VPE_CHAN_CHROMA1_IN,
162 VPE_CHAN_LUMA2_IN,
163 VPE_CHAN_CHROMA2_IN,
164 VPE_CHAN_LUMA3_IN,
165 VPE_CHAN_CHROMA3_IN,
166 VPE_CHAN_MV_IN,
167 VPE_CHAN_MV_OUT,
168 VPE_CHAN_LUMA_OUT,
169 VPE_CHAN_CHROMA_OUT,
170 VPE_CHAN_RGB_OUT,
171};
172
Benoit Parrot2f887032016-11-18 21:20:12 -0200173#define VIP_CHAN_VIP2_OFFSET 70
174#define VIP_CHAN_MULT_PORTB_OFFSET 16
175#define VIP_CHAN_YUV_PORTB_OFFSET 2
176#define VIP_CHAN_RGB_PORTB_OFFSET 1
177
Nikhil Devshatwardc12b122016-11-18 21:20:22 -0200178#define VPDMA_MAX_CHANNELS 256
179
Archit Taneja213b8ee2013-10-16 02:36:46 -0300180/* flags for VPDMA data descriptors */
181#define VPDMA_DATA_ODD_LINE_SKIP (1 << 0)
182#define VPDMA_DATA_EVEN_LINE_SKIP (1 << 1)
183#define VPDMA_DATA_FRAME_1D (1 << 2)
184#define VPDMA_DATA_MODE_TILED (1 << 3)
185
186/*
187 * client identifiers used for configuration descriptors
188 */
189#define CFD_MMR_CLIENT 0
190#define CFD_SC_CLIENT 4
191
192/* Address data block header format */
193struct vpdma_adb_hdr {
194 u32 offset;
195 u32 nwords;
196 u32 reserved0;
197 u32 reserved1;
198};
199
200/* helpers for creating ADB headers for config descriptors MMRs as client */
201#define ADB_ADDR(dma_buf, str, fld) ((dma_buf)->addr + offsetof(str, fld))
202#define MMR_ADB_ADDR(buf, str, fld) ADB_ADDR(&(buf), struct str, fld)
203
204#define VPDMA_SET_MMR_ADB_HDR(buf, str, hdr, regs, offset_a) \
205 do { \
206 struct vpdma_adb_hdr *h; \
207 struct str *adb = NULL; \
208 h = MMR_ADB_ADDR(buf, str, hdr); \
209 h->offset = (offset_a); \
210 h->nwords = sizeof(adb->regs) >> 2; \
211 } while (0)
212
Archit Taneja9262e5a2013-10-16 02:36:45 -0300213/* vpdma descriptor buffer allocation and management */
214int vpdma_alloc_desc_buf(struct vpdma_buf *buf, size_t size);
215void vpdma_free_desc_buf(struct vpdma_buf *buf);
216int vpdma_map_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf);
217void vpdma_unmap_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf);
218
219/* vpdma descriptor list funcs */
220int vpdma_create_desc_list(struct vpdma_desc_list *list, size_t size, int type);
221void vpdma_reset_desc_list(struct vpdma_desc_list *list);
222void vpdma_free_desc_list(struct vpdma_desc_list *list);
Benoit Parrot2f887032016-11-18 21:20:12 -0200223int vpdma_submit_descs(struct vpdma_data *vpdma, struct vpdma_desc_list *list,
224 int list_num);
225bool vpdma_list_busy(struct vpdma_data *vpdma, int list_num);
226void vpdma_update_dma_addr(struct vpdma_data *vpdma,
227 struct vpdma_desc_list *list, dma_addr_t dma_addr,
228 void *write_dtd, int drop, int idx);
Nikhil Devshatwarc1cd15e2016-11-18 21:20:29 -0200229
230/* VPDMA hardware list funcs */
231int vpdma_hwlist_alloc(struct vpdma_data *vpdma, void *priv);
232void *vpdma_hwlist_get_priv(struct vpdma_data *vpdma, int list_num);
233void *vpdma_hwlist_release(struct vpdma_data *vpdma, int list_num);
234
Archit Taneja213b8ee2013-10-16 02:36:46 -0300235/* helpers for creating vpdma descriptors */
236void vpdma_add_cfd_block(struct vpdma_desc_list *list, int client,
237 struct vpdma_buf *blk, u32 dest_offset);
238void vpdma_add_cfd_adb(struct vpdma_desc_list *list, int client,
239 struct vpdma_buf *adb);
240void vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list *list,
241 enum vpdma_channel chan);
Nikhil Devshatwardc12b122016-11-18 21:20:22 -0200242void vpdma_add_abort_channel_ctd(struct vpdma_desc_list *list,
243 int chan_num);
Archit Taneja928bf2b2014-03-13 08:44:08 -0300244void vpdma_add_out_dtd(struct vpdma_desc_list *list, int width,
Benoit Parrotda4414e2017-02-13 11:06:57 -0200245 int stride, const struct v4l2_rect *c_rect,
Archit Taneja213b8ee2013-10-16 02:36:46 -0300246 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
Nikhil Devshatwar634271f82016-11-18 21:20:21 -0200247 int max_w, int max_h, enum vpdma_channel chan, u32 flags);
Benoit Parrot2f887032016-11-18 21:20:12 -0200248void vpdma_rawchan_add_out_dtd(struct vpdma_desc_list *list, int width,
Benoit Parrotda4414e2017-02-13 11:06:57 -0200249 int stride, const struct v4l2_rect *c_rect,
Benoit Parrot2f887032016-11-18 21:20:12 -0200250 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
Nikhil Devshatwar634271f82016-11-18 21:20:21 -0200251 int max_w, int max_h, int raw_vpdma_chan, u32 flags);
252
Archit Taneja928bf2b2014-03-13 08:44:08 -0300253void vpdma_add_in_dtd(struct vpdma_desc_list *list, int width,
Benoit Parrotda4414e2017-02-13 11:06:57 -0200254 int stride, const struct v4l2_rect *c_rect,
Archit Taneja213b8ee2013-10-16 02:36:46 -0300255 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
Archit Taneja928bf2b2014-03-13 08:44:08 -0300256 enum vpdma_channel chan, int field, u32 flags, int frame_width,
257 int frame_height, int start_h, int start_v);
Nikhil Devshatwardc12b122016-11-18 21:20:22 -0200258int vpdma_list_cleanup(struct vpdma_data *vpdma, int list_num,
259 int *channels, int size);
Archit Taneja213b8ee2013-10-16 02:36:46 -0300260
Archit Taneja9262e5a2013-10-16 02:36:45 -0300261/* vpdma list interrupt management */
Benoit Parrot2f887032016-11-18 21:20:12 -0200262void vpdma_enable_list_complete_irq(struct vpdma_data *vpdma, int irq_num,
263 int list_num, bool enable);
Nikhil Devshatwarafbc0ae2016-11-18 21:20:24 -0200264void vpdma_clear_list_stat(struct vpdma_data *vpdma, int irq_num,
265 int list_num);
Benoit Parrot2f887032016-11-18 21:20:12 -0200266unsigned int vpdma_get_list_stat(struct vpdma_data *vpdma, int irq_num);
267unsigned int vpdma_get_list_mask(struct vpdma_data *vpdma, int irq_num);
Archit Taneja9262e5a2013-10-16 02:36:45 -0300268
269/* vpdma client configuration */
270void vpdma_set_line_mode(struct vpdma_data *vpdma, int line_mode,
271 enum vpdma_channel chan);
272void vpdma_set_frame_start_event(struct vpdma_data *vpdma,
273 enum vpdma_frame_start_event fs_event, enum vpdma_channel chan);
Nikhil Devshatwar634271f82016-11-18 21:20:21 -0200274void vpdma_set_max_size(struct vpdma_data *vpdma, int reg_addr,
275 u32 width, u32 height);
276
Benoit Parrot3f435542016-11-18 21:20:13 -0200277void vpdma_set_bg_color(struct vpdma_data *vpdma,
278 struct vpdma_data_format *fmt, u32 color);
Archit Taneja9262e5a2013-10-16 02:36:45 -0300279void vpdma_dump_regs(struct vpdma_data *vpdma);
280
281/* initialize vpdma, passed with VPE's platform device pointer */
Nikhil Devshatwarc7865952016-11-18 21:20:35 -0200282int vpdma_create(struct platform_device *pdev, struct vpdma_data *vpdma,
Archit Tanejab2c94722014-03-13 08:44:04 -0300283 void (*cb)(struct platform_device *pdev));
Archit Taneja9262e5a2013-10-16 02:36:45 -0300284
285#endif