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gerrit-public.fairphone.software / kernel / msm-5.4 / 8982735f8dd02096b75255e3c0a0df28aeaa9955 / . / drivers / media / dvb-frontends / stv0367.c
blob: f266c18c574c79467bcfa1a637d236f21df32dfe [file] [log] [blame]
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1/*
2 * stv0367.c
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/string.h>
25#include <linux/slab.h>
26#include <linux/i2c.h>
27
28#include "stv0367.h"
Daniel Scheller8881ceb2017-03-29 13:43:04 -0300[diff] [blame]29#include "stv0367_defs.h"
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]30#include "stv0367_regs.h"
31#include "stv0367_priv.h"
32
Mauro Carvalho Chehab9aca4fb2013-11-02 05:17:01 -0300[diff] [blame]33/* Max transfer size done by I2C transfer functions */
34#define MAX_XFER_SIZE 64
35
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]36static int stvdebug;
37module_param_named(debug, stvdebug, int, 0644);
38
39static int i2cdebug;
40module_param_named(i2c_debug, i2cdebug, int, 0644);
41
42#define dprintk(args...) \
43 do { \
44 if (stvdebug) \
45 printk(KERN_DEBUG args); \
46 } while (0)
47 /* DVB-C */
48
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]49enum active_demod_state { demod_none, demod_ter, demod_cab };
50
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]51struct stv0367cab_state {
52 enum stv0367_cab_signal_type state;
53 u32 mclk;
54 u32 adc_clk;
55 s32 search_range;
56 s32 derot_offset;
57 /* results */
58 int locked; /* channel found */
59 u32 freq_khz; /* found frequency (in kHz) */
60 u32 symbol_rate; /* found symbol rate (in Bds) */
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -0300[diff] [blame]61 enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
Daniel Schellercae7a902017-03-29 13:43:08 -0300[diff] [blame]62 u32 qamfec_status_reg; /* status reg to poll for FEC Lock */
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]63};
64
65struct stv0367ter_state {
66 /* DVB-T */
67 enum stv0367_ter_signal_type state;
68 enum stv0367_ter_if_iq_mode if_iq_mode;
69 enum stv0367_ter_mode mode;/* mode 2K or 8K */
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -0300[diff] [blame]70 enum fe_guard_interval guard;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]71 enum stv0367_ter_hierarchy hierarchy;
72 u32 frequency;
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -0300[diff] [blame]73 enum fe_spectral_inversion sense; /* current search spectrum */
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]74 u8 force; /* force mode/guard */
75 u8 bw; /* channel width 6, 7 or 8 in MHz */
76 u8 pBW; /* channel width used during previous lock */
77 u32 pBER;
78 u32 pPER;
79 u32 ucblocks;
80 s8 echo_pos; /* echo position */
81 u8 first_lock;
82 u8 unlock_counter;
83 u32 agc_val;
84};
85
86struct stv0367_state {
87 struct dvb_frontend fe;
88 struct i2c_adapter *i2c;
89 /* config settings */
90 const struct stv0367_config *config;
91 u8 chip_id;
92 /* DVB-C */
93 struct stv0367cab_state *cab_state;
94 /* DVB-T */
95 struct stv0367ter_state *ter_state;
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]96 /* flags for operation control */
97 u8 use_i2c_gatectrl;
Daniel Scheller8881ceb2017-03-29 13:43:04 -0300[diff] [blame]98 u8 deftabs;
Daniel Scheller7718dcf2017-03-29 13:43:06 -0300[diff] [blame]99 u8 reinit_on_setfrontend;
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]100 u8 auto_if_khz;
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]101 enum active_demod_state activedemod;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]102};
103
104#define RF_LOOKUP_TABLE_SIZE 31
105#define RF_LOOKUP_TABLE2_SIZE 16
106/* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
Hans Verkuil817d2fd2014-08-20 19:30:33 -0300[diff] [blame]107static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]108 {/*AGC1*/
109 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
110 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
111 76, 77, 78, 80, 83, 85, 88,
112 }, {/*RF(dbm)*/
113 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
114 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
115 49, 50, 52, 53, 54, 55, 56,
116 }
117};
118/* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
Hans Verkuil817d2fd2014-08-20 19:30:33 -0300[diff] [blame]119static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]120 {/*AGC2*/
121 28, 29, 31, 32, 34, 35, 36, 37,
122 38, 39, 40, 41, 42, 43, 44, 45,
123 }, {/*RF(dbm)*/
124 57, 58, 59, 60, 61, 62, 63, 64,
125 65, 66, 67, 68, 69, 70, 71, 72,
126 }
127};
128
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]129static
130int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
131{
Mauro Carvalho Chehab9aca4fb2013-11-02 05:17:01 -0300[diff] [blame]132 u8 buf[MAX_XFER_SIZE];
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]133 struct i2c_msg msg = {
134 .addr = state->config->demod_address,
135 .flags = 0,
136 .buf = buf,
137 .len = len + 2
138 };
139 int ret;
140
Mauro Carvalho Chehab9aca4fb2013-11-02 05:17:01 -0300[diff] [blame]141 if (2 + len > sizeof(buf)) {
142 printk(KERN_WARNING
143 "%s: i2c wr reg=%04x: len=%d is too big!\n",
144 KBUILD_MODNAME, reg, len);
145 return -EINVAL;
146 }
147
148
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]149 buf[0] = MSB(reg);
150 buf[1] = LSB(reg);
151 memcpy(buf + 2, data, len);
152
153 if (i2cdebug)
Peter Griffin86a10282015-07-30 14:08:51 -0300[diff] [blame]154 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
155 state->config->demod_address, reg, buf[2]);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]156
157 ret = i2c_transfer(state->i2c, &msg, 1);
158 if (ret != 1)
Peter Griffin86a10282015-07-30 14:08:51 -0300[diff] [blame]159 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
160 __func__, state->config->demod_address, reg, buf[2]);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]161
162 return (ret != 1) ? -EREMOTEIO : 0;
163}
164
165static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
166{
167 return stv0367_writeregs(state, reg, &data, 1);
168}
169
170static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
171{
172 u8 b0[] = { 0, 0 };
173 u8 b1[] = { 0 };
174 struct i2c_msg msg[] = {
175 {
176 .addr = state->config->demod_address,
177 .flags = 0,
178 .buf = b0,
179 .len = 2
180 }, {
181 .addr = state->config->demod_address,
182 .flags = I2C_M_RD,
183 .buf = b1,
184 .len = 1
185 }
186 };
187 int ret;
188
189 b0[0] = MSB(reg);
190 b0[1] = LSB(reg);
191
192 ret = i2c_transfer(state->i2c, msg, 2);
193 if (ret != 2)
Peter Griffin86a10282015-07-30 14:08:51 -0300[diff] [blame]194 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
195 __func__, state->config->demod_address, reg, b1[0]);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]196
197 if (i2cdebug)
Peter Griffin86a10282015-07-30 14:08:51 -0300[diff] [blame]198 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
199 state->config->demod_address, reg, b1[0]);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]200
201 return b1[0];
202}
203
204static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
205{
206 u8 position = 0, i = 0;
207
208 (*mask) = label & 0xff;
209
210 while ((position == 0) && (i < 8)) {
211 position = ((*mask) >> i) & 0x01;
212 i++;
213 }
214
215 (*pos) = (i - 1);
216}
217
218static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
219{
220 u8 reg, mask, pos;
221
222 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
223 extract_mask_pos(label, &mask, &pos);
224
225 val = mask & (val << pos);
226
227 reg = (reg & (~mask)) | val;
228 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
229
230}
231
232static void stv0367_setbits(u8 *reg, u32 label, u8 val)
233{
234 u8 mask, pos;
235
236 extract_mask_pos(label, &mask, &pos);
237
238 val = mask & (val << pos);
239
240 (*reg) = ((*reg) & (~mask)) | val;
241}
242
243static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
244{
245 u8 val = 0xff;
246 u8 mask, pos;
247
248 extract_mask_pos(label, &mask, &pos);
249
250 val = stv0367_readreg(state, label >> 16);
251 val = (val & mask) >> pos;
252
253 return val;
254}
255
Mauro Carvalho Chehab8c8ca1c2012-10-27 11:26:42 -0300[diff] [blame]256#if 0 /* Currently, unused */
257static u8 stv0367_getbits(u8 reg, u32 label)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]258{
259 u8 mask, pos;
260
261 extract_mask_pos(label, &mask, &pos);
262
263 return (reg & mask) >> pos;
264}
Mauro Carvalho Chehab8c8ca1c2012-10-27 11:26:42 -0300[diff] [blame]265#endif
Daniel Scheller41727cb2017-03-29 13:43:03 -0300[diff] [blame]266
267static void stv0367_write_table(struct stv0367_state *state,
268 const struct st_register *deftab)
269{
270 int i = 0;
271
272 while (1) {
273 if (!deftab[i].addr)
274 break;
275 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
276 i++;
277 }
278}
279
Daniel Scheller8a9c0732017-03-29 13:43:05 -0300[diff] [blame]280static void stv0367_pll_setup(struct stv0367_state *state,
281 u32 icspeed, u32 xtal)
282{
283 /* note on regs: R367TER_* and R367CAB_* defines each point to
284 * 0xf0d8, so just use R367TER_ for both cases
285 */
286
287 switch (icspeed) {
288 case STV0367_ICSPEED_58000:
289 switch (xtal) {
290 default:
291 case 27000000:
292 dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
293 /* PLLMDIV: 27, PLLNDIV: 232 */
294 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
295 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
296 break;
297 }
298 break;
299 default:
300 case STV0367_ICSPEED_53125:
301 switch (xtal) {
302 /* set internal freq to 53.125MHz */
303 case 16000000:
304 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
305 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
306 break;
307 case 25000000:
308 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
309 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
310 break;
311 default:
312 case 27000000:
313 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
314 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
315 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
316 break;
317 case 30000000:
318 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
319 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
320 break;
321 }
322 }
323
324 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
325}
326
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]327static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
328{
329 if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
330 state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
331 *ifkhz = *ifkhz / 1000; /* hz -> khz */
332 } else
333 *ifkhz = state->config->if_khz;
334
335 return 0;
336}
337
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]338static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
339{
340 struct stv0367_state *state = fe->demodulator_priv;
341 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
342
343 dprintk("%s:\n", __func__);
344
345 if (enable) {
346 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
347 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
348 } else {
349 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
350 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
351 }
352
353 stv0367_writereg(state, R367TER_I2CRPT, tmp);
354
355 return 0;
356}
357
358static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
359{
Emil Goode20721182014-06-24 18:42:27 -0300[diff] [blame]360 struct dvb_frontend_ops *frontend_ops = &fe->ops;
361 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]362 u32 freq = 0;
Dan Carpenterbf512b22011-03-06 10:40:11 -0300[diff] [blame]363 int err = 0;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]364
365 dprintk("%s:\n", __func__);
366
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]367 if (tuner_ops->get_frequency) {
368 err = tuner_ops->get_frequency(fe, &freq);
369 if (err < 0) {
370 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
371 return err;
372 }
373
374 dprintk("%s: frequency=%d\n", __func__, freq);
375
376 } else
377 return -1;
378
379 return freq;
380}
381
382static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
383 {
384 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
385 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
386 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
387 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
388 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
389 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
390 }, {
391 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
392 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
393 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
394 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
395 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
396 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
397 }, {
398 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
399 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
400 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
401 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
402 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
403 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
404 }
405};
406
407static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
408 {
409 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
410 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
411 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
412 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
413 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
414 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
415 }, {
416 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
417 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
418 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
419 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
420 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
421 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
422 }, {
423 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
424 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
425 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
426 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
427 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
428 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
429 }
430};
431
432static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
433 {
434 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
435 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
436 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
437 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
438 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
439 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
440 }, {
441 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
442 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
443 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
444 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
445 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
446 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
447
448 }, {
449 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
450 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
451 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
452 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
453 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
454 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
455 }
456};
457
458static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
459{
460 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
461 u32 m, n, p;
462
463 dprintk("%s:\n", __func__);
464
465 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
466 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
467 if (n == 0)
468 n = n + 1;
469
470 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
471 if (m == 0)
472 m = m + 1;
473
474 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
475 if (p > 5)
476 p = 5;
477
478 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
479
480 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
481 n, m, p, mclk_Hz, ExtClk_Hz);
482 } else
483 mclk_Hz = ExtClk_Hz;
484
485 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
486
487 return mclk_Hz;
488}
489
490static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
Dan Carpenterbc4b18c2011-03-06 10:41:23 -0300[diff] [blame]491 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]492{
493 int i, j, k, freq;
494
495 dprintk("%s:\n", __func__);
496
497 freq = stv0367ter_get_mclk(state, DemodXtal);
498
499 if (freq == 53125000)
500 k = 1; /* equivalent to Xtal 25M on 362*/
501 else if (freq == 54000000)
502 k = 0; /* equivalent to Xtal 27M on 362*/
503 else if (freq == 52500000)
504 k = 2; /* equivalent to Xtal 30M on 362*/
505 else
506 return 0;
507
508 for (i = 1; i <= 6; i++) {
509 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
510
511 for (j = 1; j <= 5; j++) {
512 stv0367_writereg(state,
513 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
514 MSB(CellsCoeffs[k][i-1][j-1]));
515 stv0367_writereg(state,
516 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
517 LSB(CellsCoeffs[k][i-1][j-1]));
518 }
519 }
520
521 return 1;
522
523}
524
525static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
526{
527 dprintk("%s:\n", __func__);
528
529 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
530
531 /* Lock detect 1 */
532 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
533 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
534 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
535
536 /* Lock detect 2 */
537 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
538 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
539 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
540
541 /* Lock detect 3 */
542 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
543 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
544 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
545
546 /* Lock detect 4 */
547 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
548 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
549 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
550
551}
552
553static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
554 u32 DemodXtalValue)
555{
556 dprintk("%s:\n", __func__);
557
558 stv0367_writebits(state, F367TER_NRST_IIR, 0);
559
560 switch (Bandwidth) {
561 case 6:
562 if (!stv0367ter_filt_coeff_init(state,
563 CellsCoeffs_6MHz_367cofdm,
564 DemodXtalValue))
565 return 0;
566 break;
567 case 7:
568 if (!stv0367ter_filt_coeff_init(state,
569 CellsCoeffs_7MHz_367cofdm,
570 DemodXtalValue))
571 return 0;
572 break;
573 case 8:
574 if (!stv0367ter_filt_coeff_init(state,
575 CellsCoeffs_8MHz_367cofdm,
576 DemodXtalValue))
577 return 0;
578 break;
579 default:
580 return 0;
581 }
582
583 stv0367_writebits(state, F367TER_NRST_IIR, 1);
584
585 return 1;
586}
587
588static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
589{
590
591 u8 com_n;
592
593 dprintk("%s:\n", __func__);
594
595 com_n = stv0367_readbits(state, F367TER_COM_N);
596
597 stv0367_writebits(state, F367TER_COM_N, 0x07);
598
599 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
600 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
601
602 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
603 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
604
605 stv0367_writebits(state, F367TER_COM_N, com_n);
606
607}
608
609static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
610{
611 int local_tempo = 0;
612 switch (mode) {
613 case 0:
614 local_tempo = tempo1;
615 break;
616 case 1:
617 local_tempo = tempo2;
618 break ;
619
620 case 2:
621 local_tempo = tempo3;
622 break;
623
624 default:
625 break;
626 }
627 /* msleep(local_tempo); */
628 return local_tempo;
629}
630
631static enum
632stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
633{
634 int wd = 100;
635 unsigned short int SYR_var;
636 s32 SYRStatus;
637
638 dprintk("%s:\n", __func__);
639
640 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
641
642 while ((!SYR_var) && (wd > 0)) {
643 usleep_range(2000, 3000);
644 wd -= 2;
645 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
646 }
647
648 if (!SYR_var)
649 SYRStatus = FE_TER_NOSYMBOL;
650 else
651 SYRStatus = FE_TER_SYMBOLOK;
652
653 dprintk("stv0367ter_check_syr SYRStatus %s\n",
654 SYR_var == 0 ? "No Symbol" : "OK");
655
656 return SYRStatus;
657}
658
659static enum
660stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
661 s32 FFTmode)
662{
663
664 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
665 int wd = 0;
666
667 dprintk("%s:\n", __func__);
668
669 switch (FFTmode) {
670 case 0: /*2k mode*/
671 CPAMPMin = 20;
672 wd = 10;
673 break;
674 case 1: /*8k mode*/
675 CPAMPMin = 80;
676 wd = 55;
677 break;
678 case 2: /*4k mode*/
679 CPAMPMin = 40;
680 wd = 30;
681 break;
682 default:
683 CPAMPMin = 0xffff; /*drives to NOCPAMP */
684 break;
685 }
686
687 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
688
689 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
690 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
691 usleep_range(1000, 2000);
692 wd -= 1;
693 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
694 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
695 }
696 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
697 if (CPAMPvalue < CPAMPMin) {
698 CPAMPStatus = FE_TER_NOCPAMP;
Daniel Schellerdf5a38e2017-03-29 13:43:02 -0300[diff] [blame]699 dprintk("%s: CPAMP failed\n", __func__);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]700 } else {
Daniel Schellerdf5a38e2017-03-29 13:43:02 -0300[diff] [blame]701 dprintk("%s: CPAMP OK !\n", __func__);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]702 CPAMPStatus = FE_TER_CPAMPOK;
703 }
704
705 return CPAMPStatus;
706}
707
Mauro Carvalho Chehab8c8ca1c2012-10-27 11:26:42 -0300[diff] [blame]708static enum stv0367_ter_signal_type
709stv0367ter_lock_algo(struct stv0367_state *state)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]710{
711 enum stv0367_ter_signal_type ret_flag;
712 short int wd, tempo;
713 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
714 u8 tmp, tmp2;
715
716 dprintk("%s:\n", __func__);
717
718 if (state == NULL)
719 return FE_TER_SWNOK;
720
721 try = 0;
722 do {
723 ret_flag = FE_TER_LOCKOK;
724
725 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
726
727 if (state->config->if_iq_mode != 0)
728 stv0367_writebits(state, F367TER_COM_N, 0x07);
729
730 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
731 stv0367_writebits(state, F367TER_MODE, 0);
732 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
733 usleep_range(5000, 10000);
734
735 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
736
737
738 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
739 return FE_TER_NOSYMBOL;
740 else { /*
741 if chip locked on wrong mode first try,
742 it must lock correctly second try */
743 mode = stv0367_readbits(state, F367TER_SYR_MODE);
744 if (stv0367ter_check_cpamp(state, mode) ==
745 FE_TER_NOCPAMP) {
746 if (try == 0)
747 ret_flag = FE_TER_NOCPAMP;
748
749 }
750 }
751
752 try++;
753 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
754
755 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
756 tmp2 = stv0367_readreg(state, R367TER_STATUS);
Hans Verkuilfb661a72011-03-06 09:26:24 -0300[diff] [blame]757 dprintk("state=%p\n", state);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]758 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
759 mode, tmp, tmp2);
760
761 tmp = stv0367_readreg(state, R367TER_PRVIT);
762 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
763 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
764
765 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
766 dprintk("GAIN_SRC1=0x%x\n", tmp);
767
768 if ((mode != 0) && (mode != 1) && (mode != 2))
769 return FE_TER_SWNOK;
770
771 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
772
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]773 /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]774 and set channel predictor in automatic */
775#if 0
776 switch (guard) {
777
778 case 0:
779 case 1:
780 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
781 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
782 break;
783 case 2:
784 case 3:
785 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
786 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
787 break;
788
789 default:
790 return FE_TER_SWNOK;
791 }
792#endif
793
794 /*reset fec an reedsolo FOR 367 only*/
795 stv0367_writebits(state, F367TER_RST_SFEC, 1);
796 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
797 usleep_range(1000, 2000);
798 stv0367_writebits(state, F367TER_RST_SFEC, 0);
799 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
800
801 u_var1 = stv0367_readbits(state, F367TER_LK);
802 u_var2 = stv0367_readbits(state, F367TER_PRF);
803 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
804 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
805
806 wd = stv0367ter_duration(mode, 125, 500, 250);
807 tempo = stv0367ter_duration(mode, 4, 16, 8);
808
809 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
810 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
811 usleep_range(1000 * tempo, 1000 * (tempo + 1));
812 wd -= tempo;
813 u_var1 = stv0367_readbits(state, F367TER_LK);
814 u_var2 = stv0367_readbits(state, F367TER_PRF);
815 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
816 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
817 }
818
819 if (!u_var1)
820 return FE_TER_NOLOCK;
821
822
823 if (!u_var2)
824 return FE_TER_NOPRFOUND;
825
826 if (!u_var3)
827 return FE_TER_NOTPS;
828
829 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
830 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
831 switch (guard) {
832 case 0:
833 case 1:
834 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
835 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
836 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
837 break;
838 case 2:
839 case 3:
840 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
841 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
842 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
843 break;
844
845 default:
846 return FE_TER_SWNOK;
847 }
848
849 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
850 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
851 (mode == 1) &&
852 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
853 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
854 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
855 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
856 } else
857 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
858
859 wd = stv0367ter_duration(mode, 125, 500, 250);
860 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
861
862 while ((!u_var4) && (wd >= 0)) {
863 usleep_range(1000 * tempo, 1000 * (tempo + 1));
864 wd -= tempo;
865 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
866 }
867
868 if (!u_var4)
869 return FE_TER_NOLOCK;
870
871 /* for 367 leave COM_N at 0x7 for IQ_mode*/
872 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
873 tempo=0;
874 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
875 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
876 ChipWaitOrAbort(state,1);
877 tempo+=1;
878 }
879
880 stv0367_writebits(state,F367TER_COM_N,0x17);
881 } */
882
883 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
884
885 dprintk("FE_TER_LOCKOK !!!\n");
886
887 return FE_TER_LOCKOK;
888
889}
890
891static void stv0367ter_set_ts_mode(struct stv0367_state *state,
892 enum stv0367_ts_mode PathTS)
893{
894
895 dprintk("%s:\n", __func__);
896
897 if (state == NULL)
898 return;
899
900 stv0367_writebits(state, F367TER_TS_DIS, 0);
901 switch (PathTS) {
902 default:
903 /*for removing warning :default we can assume in parallel mode*/
904 case STV0367_PARALLEL_PUNCT_CLOCK:
905 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
906 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
907 break;
908 case STV0367_SERIAL_PUNCT_CLOCK:
909 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
910 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
911 break;
912 }
913}
914
915static void stv0367ter_set_clk_pol(struct stv0367_state *state,
916 enum stv0367_clk_pol clock)
917{
918
919 dprintk("%s:\n", __func__);
920
921 if (state == NULL)
922 return;
923
924 switch (clock) {
925 case STV0367_RISINGEDGE_CLOCK:
926 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
927 break;
928 case STV0367_FALLINGEDGE_CLOCK:
929 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
930 break;
931 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
932 default:
933 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
934 break;
935 }
936}
937
938#if 0
939static void stv0367ter_core_sw(struct stv0367_state *state)
940{
941
942 dprintk("%s:\n", __func__);
943
944 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
945 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
946 msleep(350);
947}
948#endif
949static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
950{
951 struct stv0367_state *state = fe->demodulator_priv;
952
953 dprintk("%s:\n", __func__);
954
955 if (standby_on) {
956 stv0367_writebits(state, F367TER_STDBY, 1);
957 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
958 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
959 } else {
960 stv0367_writebits(state, F367TER_STDBY, 0);
961 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
962 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
963 }
964
965 return 0;
966}
967
968static int stv0367ter_sleep(struct dvb_frontend *fe)
969{
970 return stv0367ter_standby(fe, 1);
971}
972
Mauro Carvalho Chehab8c8ca1c2012-10-27 11:26:42 -0300[diff] [blame]973static int stv0367ter_init(struct dvb_frontend *fe)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]974{
975 struct stv0367_state *state = fe->demodulator_priv;
976 struct stv0367ter_state *ter_state = state->ter_state;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]977
978 dprintk("%s:\n", __func__);
979
980 ter_state->pBER = 0;
981
Daniel Scheller8881ceb2017-03-29 13:43:04 -0300[diff] [blame]982 stv0367_write_table(state,
983 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]984
Daniel Scheller8a9c0732017-03-29 13:43:05 -0300[diff] [blame]985 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]986
987 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
988 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
989
990 /*Set TS1 and TS2 to serial or parallel mode */
991 stv0367ter_set_ts_mode(state, state->config->ts_mode);
992 stv0367ter_set_clk_pol(state, state->config->clk_pol);
993
994 state->chip_id = stv0367_readreg(state, R367TER_ID);
995 ter_state->first_lock = 0;
996 ter_state->unlock_counter = 2;
997
998 return 0;
999}
1000
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1001static int stv0367ter_algo(struct dvb_frontend *fe)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1002{
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1003 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1004 struct stv0367_state *state = fe->demodulator_priv;
1005 struct stv0367ter_state *ter_state = state->ter_state;
1006 int offset = 0, tempo = 0;
1007 u8 u_var;
Peter Senna Tschudindf1ec022012-06-14 13:58:14 -0300[diff] [blame]1008 u8 /*constell,*/ counter;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1009 s8 step;
1010 s32 timing_offset = 0;
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]1011 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1012
1013 dprintk("%s:\n", __func__);
1014
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]1015 stv0367_get_if_khz(state, &ifkhz);
1016
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1017 ter_state->frequency = p->frequency;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1018 ter_state->force = FE_TER_FORCENONE
1019 + stv0367_readbits(state, F367TER_FORCE) * 2;
1020 ter_state->if_iq_mode = state->config->if_iq_mode;
1021 switch (state->config->if_iq_mode) {
1022 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1023 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1024 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1025 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1026 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1027 break;
1028 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1029 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1030 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1031 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1032 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1033 break;
1034 case FE_TER_IQ_TUNER: /* IQ mode */
1035 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1036 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1037 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1038 break;
1039 default:
1040 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1041 return -EINVAL;
1042 }
1043
1044 usleep_range(5000, 7000);
1045
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1046 switch (p->inversion) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1047 case INVERSION_AUTO:
1048 default:
1049 dprintk("%s: inversion AUTO\n", __func__);
1050 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1051 stv0367_writebits(state, F367TER_IQ_INVERT,
1052 ter_state->sense);
1053 else
1054 stv0367_writebits(state, F367TER_INV_SPECTR,
1055 ter_state->sense);
1056
1057 break;
1058 case INVERSION_ON:
1059 case INVERSION_OFF:
1060 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1061 stv0367_writebits(state, F367TER_IQ_INVERT,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1062 p->inversion);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1063 else
1064 stv0367_writebits(state, F367TER_INV_SPECTR,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1065 p->inversion);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1066
1067 break;
1068 }
1069
1070 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1071 (ter_state->pBW != ter_state->bw)) {
1072 stv0367ter_agc_iir_lock_detect_set(state);
1073
1074 /*set fine agc target to 180 for LPIF or IQ mode*/
1075 /* set Q_AGCTarget */
1076 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1077 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1078 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1079
1080 /* set Q_AGCTarget */
1081 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1082 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1083 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1084
1085 if (!stv0367_iir_filt_init(state, ter_state->bw,
1086 state->config->xtal))
1087 return -EINVAL;
1088 /*set IIR filter once for 6,7 or 8MHz BW*/
1089 ter_state->pBW = ter_state->bw;
1090
1091 stv0367ter_agc_iir_rst(state);
1092 }
1093
1094 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1095 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1096 else
1097 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1098
1099 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1100 temp = (int)
1101 ((((ter_state->bw * 64 * (1 << 15) * 100)
1102 / (InternalFreq)) * 10) / 7);
1103
1104 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1105 temp = temp / 2;
1106 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1107 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1108
1109 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1110 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1111 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1112 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1113 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1114 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1115 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1116 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1117
1118 temp = (int)
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]1119 ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1120
1121 dprintk("DEROT temp=0x%x\n", temp);
1122 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1123 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1124
1125 ter_state->echo_pos = 0;
1126 ter_state->ucblocks = 0; /* liplianin */
1127 ter_state->pBER = 0; /* liplianin */
1128 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1129
1130 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1131 return 0;
1132
1133 ter_state->state = FE_TER_LOCKOK;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1134
1135 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1136 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1137
1138 ter_state->first_lock = 1; /* we know sense now :) */
1139
1140 ter_state->agc_val =
1141 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1142 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1143 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1144 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1145
1146 /* Carrier offset calculation */
1147 stv0367_writebits(state, F367TER_FREEZE, 1);
1148 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1149 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1150 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1151 stv0367_writebits(state, F367TER_FREEZE, 0);
1152 if (offset > 8388607)
1153 offset -= 16777216;
1154
1155 offset = offset * 2 / 16384;
1156
1157 if (ter_state->mode == FE_TER_MODE_2K)
1158 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1159 else if (ter_state->mode == FE_TER_MODE_4K)
1160 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1161 else if (ter_state->mode == FE_TER_MODE_8K)
1162 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1163
1164 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1165 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1166 (stv0367_readbits(state,
1167 F367TER_STATUS_INV_SPECRUM) == 1)))
1168 offset = offset * -1;
1169 }
1170
1171 if (ter_state->bw == 6)
1172 offset = (offset * 6) / 8;
1173 else if (ter_state->bw == 7)
1174 offset = (offset * 7) / 8;
1175
1176 ter_state->frequency += offset;
1177
1178 tempo = 10; /* exit even if timing_offset stays null */
1179 while ((timing_offset == 0) && (tempo > 0)) {
1180 usleep_range(10000, 20000); /*was 20ms */
1181 /* fine tuning of timing offset if required */
1182 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1183 + 256 * stv0367_readbits(state,
1184 F367TER_TRL_TOFFSET_HI);
1185 if (timing_offset >= 32768)
1186 timing_offset -= 65536;
1187 trl_nomrate = (512 * stv0367_readbits(state,
1188 F367TER_TRL_NOMRATE_HI)
1189 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1190 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1191
1192 timing_offset = ((signed)(1000000 / trl_nomrate) *
1193 timing_offset) / 2048;
1194 tempo--;
1195 }
1196
1197 if (timing_offset <= 0) {
1198 timing_offset = (timing_offset - 11) / 22;
1199 step = -1;
1200 } else {
1201 timing_offset = (timing_offset + 11) / 22;
1202 step = 1;
1203 }
1204
1205 for (counter = 0; counter < abs(timing_offset); counter++) {
1206 trl_nomrate += step;
1207 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1208 trl_nomrate % 2);
1209 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1210 trl_nomrate / 2);
1211 usleep_range(1000, 2000);
1212 }
1213
1214 usleep_range(5000, 6000);
1215 /* unlocks could happen in case of trl centring big step,
1216 then a core off/on restarts demod */
1217 u_var = stv0367_readbits(state, F367TER_LK);
1218
1219 if (!u_var) {
1220 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1221 msleep(20);
1222 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1223 }
1224
1225 return 0;
1226}
1227
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1228static int stv0367ter_set_frontend(struct dvb_frontend *fe)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1229{
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1230 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1231 struct stv0367_state *state = fe->demodulator_priv;
1232 struct stv0367ter_state *ter_state = state->ter_state;
1233
1234 /*u8 trials[2]; */
1235 s8 num_trials, index;
1236 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1237
Daniel Scheller7718dcf2017-03-29 13:43:06 -0300[diff] [blame]1238 if (state->reinit_on_setfrontend)
1239 stv0367ter_init(fe);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1240
1241 if (fe->ops.tuner_ops.set_params) {
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]1242 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1243 fe->ops.i2c_gate_ctrl(fe, 1);
Mauro Carvalho Chehab14d24d12011-12-24 12:24:33 -0300[diff] [blame]1244 fe->ops.tuner_ops.set_params(fe);
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]1245 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1246 fe->ops.i2c_gate_ctrl(fe, 0);
1247 }
1248
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1249 switch (p->transmission_mode) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1250 default:
1251 case TRANSMISSION_MODE_AUTO:
1252 case TRANSMISSION_MODE_2K:
1253 ter_state->mode = FE_TER_MODE_2K;
1254 break;
1255/* case TRANSMISSION_MODE_4K:
1256 pLook.mode = FE_TER_MODE_4K;
1257 break;*/
1258 case TRANSMISSION_MODE_8K:
1259 ter_state->mode = FE_TER_MODE_8K;
1260 break;
1261 }
1262
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1263 switch (p->guard_interval) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1264 default:
1265 case GUARD_INTERVAL_1_32:
1266 case GUARD_INTERVAL_1_16:
1267 case GUARD_INTERVAL_1_8:
1268 case GUARD_INTERVAL_1_4:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1269 ter_state->guard = p->guard_interval;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1270 break;
1271 case GUARD_INTERVAL_AUTO:
1272 ter_state->guard = GUARD_INTERVAL_1_32;
1273 break;
1274 }
1275
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1276 switch (p->bandwidth_hz) {
1277 case 6000000:
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1278 ter_state->bw = FE_TER_CHAN_BW_6M;
1279 break;
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1280 case 7000000:
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1281 ter_state->bw = FE_TER_CHAN_BW_7M;
1282 break;
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1283 case 8000000:
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1284 default:
1285 ter_state->bw = FE_TER_CHAN_BW_8M;
1286 }
1287
1288 ter_state->hierarchy = FE_TER_HIER_NONE;
1289
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1290 switch (p->inversion) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1291 case INVERSION_OFF:
1292 case INVERSION_ON:
1293 num_trials = 1;
1294 break;
1295 default:
1296 num_trials = 2;
1297 if (ter_state->first_lock)
1298 num_trials = 1;
1299 break;
1300 }
1301
1302 ter_state->state = FE_TER_NOLOCK;
1303 index = 0;
1304
1305 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1306 if (!ter_state->first_lock) {
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1307 if (p->inversion == INVERSION_AUTO)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1308 ter_state->sense = SenseTrials[index];
1309
1310 }
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1311 stv0367ter_algo(fe);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1312
1313 if ((ter_state->state == FE_TER_LOCKOK) &&
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1314 (p->inversion == INVERSION_AUTO) &&
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1315 (index == 1)) {
1316 /* invert spectrum sense */
1317 SenseTrials[index] = SenseTrials[0];
1318 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1319 }
1320
1321 index++;
1322 }
1323
1324 return 0;
1325}
1326
1327static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1328{
1329 struct stv0367_state *state = fe->demodulator_priv;
1330 struct stv0367ter_state *ter_state = state->ter_state;
1331 u32 errs = 0;
1332
1333 /*wait for counting completion*/
1334 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1335 errs =
1336 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1337 * (1 << 16))
1338 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1339 * (1 << 8))
1340 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1341 ter_state->ucblocks = errs;
1342 }
1343
1344 (*ucblocks) = ter_state->ucblocks;
1345
1346 return 0;
1347}
1348
Mauro Carvalho Chehab7e3e68b2016-02-04 12:58:30 -0200[diff] [blame]1349static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1350 struct dtv_frontend_properties *p)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1351{
1352 struct stv0367_state *state = fe->demodulator_priv;
1353 struct stv0367ter_state *ter_state = state->ter_state;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1354 enum stv0367_ter_mode mode;
1355 int constell = 0,/* snr = 0,*/ Data = 0;
1356
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1357 p->frequency = stv0367_get_tuner_freq(fe);
1358 if ((int)p->frequency < 0)
1359 p->frequency = -p->frequency;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1360
1361 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1362 if (constell == 0)
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1363 p->modulation = QPSK;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1364 else if (constell == 1)
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1365 p->modulation = QAM_16;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1366 else
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1367 p->modulation = QAM_64;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1368
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1369 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1370
1371 /* Get the Hierarchical mode */
1372 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1373
1374 switch (Data) {
1375 case 0:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1376 p->hierarchy = HIERARCHY_NONE;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1377 break;
1378 case 1:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1379 p->hierarchy = HIERARCHY_1;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1380 break;
1381 case 2:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1382 p->hierarchy = HIERARCHY_2;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1383 break;
1384 case 3:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1385 p->hierarchy = HIERARCHY_4;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1386 break;
1387 default:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1388 p->hierarchy = HIERARCHY_AUTO;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1389 break; /* error */
1390 }
1391
1392 /* Get the FEC Rate */
1393 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1394 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1395 else
1396 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1397
1398 switch (Data) {
1399 case 0:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1400 p->code_rate_HP = FEC_1_2;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1401 break;
1402 case 1:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1403 p->code_rate_HP = FEC_2_3;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1404 break;
1405 case 2:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1406 p->code_rate_HP = FEC_3_4;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1407 break;
1408 case 3:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1409 p->code_rate_HP = FEC_5_6;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1410 break;
1411 case 4:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1412 p->code_rate_HP = FEC_7_8;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1413 break;
1414 default:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1415 p->code_rate_HP = FEC_AUTO;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1416 break; /* error */
1417 }
1418
1419 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1420
1421 switch (mode) {
1422 case FE_TER_MODE_2K:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1423 p->transmission_mode = TRANSMISSION_MODE_2K;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1424 break;
1425/* case FE_TER_MODE_4K:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1426 p->transmission_mode = TRANSMISSION_MODE_4K;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1427 break;*/
1428 case FE_TER_MODE_8K:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1429 p->transmission_mode = TRANSMISSION_MODE_8K;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1430 break;
1431 default:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1432 p->transmission_mode = TRANSMISSION_MODE_AUTO;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1433 }
1434
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1435 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1436
Mauro Carvalho Chehab7c995072014-09-03 15:10:25 -0300[diff] [blame]1437 return 0;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1438}
1439
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]1440static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1441{
1442 struct stv0367_state *state = fe->demodulator_priv;
1443 u32 snru32 = 0;
1444 int cpt = 0;
1445 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1446
1447 while (cpt < 10) {
1448 usleep_range(2000, 3000);
1449 if (cut == 0x50) /*cut 1.0 cut 1.1*/
1450 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1451 else /*cu2.0*/
1452 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1453
1454 cpt++;
1455 }
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1456 snru32 /= 10;/*average on 10 values*/
1457
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]1458 return snru32;
1459}
1460
1461static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
1462{
1463 u32 snrval = stv0367ter_snr_readreg(fe);
1464
1465 *snr = snrval / 1000;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1466
1467 return 0;
1468}
1469
1470#if 0
1471static int stv0367ter_status(struct dvb_frontend *fe)
1472{
1473
1474 struct stv0367_state *state = fe->demodulator_priv;
1475 struct stv0367ter_state *ter_state = state->ter_state;
1476 int locked = FALSE;
1477
1478 locked = (stv0367_readbits(state, F367TER_LK));
1479 if (!locked)
1480 ter_state->unlock_counter += 1;
1481 else
1482 ter_state->unlock_counter = 0;
1483
1484 if (ter_state->unlock_counter > 2) {
1485 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1486 (!stv0367_readbits(state, F367TER_LK))) {
1487 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1488 usleep_range(2000, 3000);
1489 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1490 msleep(350);
1491 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1492 (stv0367_readbits(state, F367TER_LK));
1493 }
1494
1495 }
1496
1497 return locked;
1498}
1499#endif
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -0300[diff] [blame]1500static int stv0367ter_read_status(struct dvb_frontend *fe,
1501 enum fe_status *status)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1502{
1503 struct stv0367_state *state = fe->demodulator_priv;
1504
1505 dprintk("%s:\n", __func__);
1506
1507 *status = 0;
1508
1509 if (stv0367_readbits(state, F367TER_LK)) {
1510 *status |= FE_HAS_LOCK;
1511 dprintk("%s: stv0367 has locked\n", __func__);
1512 }
1513
1514 return 0;
1515}
1516
1517static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
1518{
1519 struct stv0367_state *state = fe->demodulator_priv;
1520 struct stv0367ter_state *ter_state = state->ter_state;
1521 u32 Errors = 0, tber = 0, temporary = 0;
1522 int abc = 0, def = 0;
1523
1524
1525 /*wait for counting completion*/
1526 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1527 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1528 * (1 << 16))
1529 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1530 * (1 << 8))
1531 + ((u32)stv0367_readbits(state,
1532 F367TER_SFEC_ERR_CNT_LO));
1533 /*measurement not completed, load previous value*/
1534 else {
1535 tber = ter_state->pBER;
1536 return 0;
1537 }
1538
1539 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1540 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1541
1542 if (Errors == 0) {
1543 tber = 0;
1544 } else if (abc == 0x7) {
1545 if (Errors <= 4) {
1546 temporary = (Errors * 1000000000) / (8 * (1 << 14));
1547 temporary = temporary;
1548 } else if (Errors <= 42) {
1549 temporary = (Errors * 100000000) / (8 * (1 << 14));
1550 temporary = temporary * 10;
1551 } else if (Errors <= 429) {
1552 temporary = (Errors * 10000000) / (8 * (1 << 14));
1553 temporary = temporary * 100;
1554 } else if (Errors <= 4294) {
1555 temporary = (Errors * 1000000) / (8 * (1 << 14));
1556 temporary = temporary * 1000;
1557 } else if (Errors <= 42949) {
1558 temporary = (Errors * 100000) / (8 * (1 << 14));
1559 temporary = temporary * 10000;
1560 } else if (Errors <= 429496) {
1561 temporary = (Errors * 10000) / (8 * (1 << 14));
1562 temporary = temporary * 100000;
1563 } else { /*if (Errors<4294967) 2^22 max error*/
1564 temporary = (Errors * 1000) / (8 * (1 << 14));
1565 temporary = temporary * 100000; /* still to *10 */
1566 }
1567
1568 /* Byte error*/
1569 if (def == 2)
1570 /*tber=Errors/(8*(1 <<14));*/
1571 tber = temporary;
1572 else if (def == 3)
1573 /*tber=Errors/(8*(1 <<16));*/
1574 tber = temporary / 4;
1575 else if (def == 4)
1576 /*tber=Errors/(8*(1 <<18));*/
1577 tber = temporary / 16;
1578 else if (def == 5)
1579 /*tber=Errors/(8*(1 <<20));*/
1580 tber = temporary / 64;
1581 else if (def == 6)
1582 /*tber=Errors/(8*(1 <<22));*/
1583 tber = temporary / 256;
1584 else
1585 /* should not pass here*/
1586 tber = 0;
1587
1588 if ((Errors < 4294967) && (Errors > 429496))
1589 tber *= 10;
1590
1591 }
1592
1593 /* save actual value */
1594 ter_state->pBER = tber;
1595
1596 (*ber) = tber;
1597
1598 return 0;
1599}
1600#if 0
1601static u32 stv0367ter_get_per(struct stv0367_state *state)
1602{
1603 struct stv0367ter_state *ter_state = state->ter_state;
1604 u32 Errors = 0, Per = 0, temporary = 0;
1605 int abc = 0, def = 0, cpt = 0;
1606
1607 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1608 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1609 usleep_range(1000, 2000);
1610 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1611 * (1 << 16))
1612 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1613 * (1 << 8))
1614 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1615 cpt++;
1616 }
1617 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1618 def = stv0367_readbits(state, F367TER_NUM_EVT1);
1619
1620 if (Errors == 0)
1621 Per = 0;
1622 else if (abc == 0x9) {
1623 if (Errors <= 4) {
1624 temporary = (Errors * 1000000000) / (8 * (1 << 8));
1625 temporary = temporary;
1626 } else if (Errors <= 42) {
1627 temporary = (Errors * 100000000) / (8 * (1 << 8));
1628 temporary = temporary * 10;
1629 } else if (Errors <= 429) {
1630 temporary = (Errors * 10000000) / (8 * (1 << 8));
1631 temporary = temporary * 100;
1632 } else if (Errors <= 4294) {
1633 temporary = (Errors * 1000000) / (8 * (1 << 8));
1634 temporary = temporary * 1000;
1635 } else if (Errors <= 42949) {
1636 temporary = (Errors * 100000) / (8 * (1 << 8));
1637 temporary = temporary * 10000;
1638 } else { /*if(Errors<=429496) 2^16 errors max*/
1639 temporary = (Errors * 10000) / (8 * (1 << 8));
1640 temporary = temporary * 100000;
1641 }
1642
1643 /* pkt error*/
1644 if (def == 2)
1645 /*Per=Errors/(1 << 8);*/
1646 Per = temporary;
1647 else if (def == 3)
1648 /*Per=Errors/(1 << 10);*/
1649 Per = temporary / 4;
1650 else if (def == 4)
1651 /*Per=Errors/(1 << 12);*/
1652 Per = temporary / 16;
1653 else if (def == 5)
1654 /*Per=Errors/(1 << 14);*/
1655 Per = temporary / 64;
1656 else if (def == 6)
1657 /*Per=Errors/(1 << 16);*/
1658 Per = temporary / 256;
1659 else
1660 Per = 0;
1661
1662 }
1663 /* save actual value */
1664 ter_state->pPER = Per;
1665
1666 return Per;
1667}
1668#endif
1669static int stv0367_get_tune_settings(struct dvb_frontend *fe,
1670 struct dvb_frontend_tune_settings
1671 *fe_tune_settings)
1672{
1673 fe_tune_settings->min_delay_ms = 1000;
1674 fe_tune_settings->step_size = 0;
1675 fe_tune_settings->max_drift = 0;
1676
1677 return 0;
1678}
1679
1680static void stv0367_release(struct dvb_frontend *fe)
1681{
1682 struct stv0367_state *state = fe->demodulator_priv;
1683
1684 kfree(state->ter_state);
1685 kfree(state->cab_state);
1686 kfree(state);
1687}
1688
Max Kellermannbd336e62016-08-09 18:32:21 -0300[diff] [blame]1689static const struct dvb_frontend_ops stv0367ter_ops = {
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1690 .delsys = { SYS_DVBT },
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1691 .info = {
1692 .name = "ST STV0367 DVB-T",
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1693 .frequency_min = 47000000,
1694 .frequency_max = 862000000,
1695 .frequency_stepsize = 15625,
1696 .frequency_tolerance = 0,
1697 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1698 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
1699 FE_CAN_FEC_AUTO |
1700 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1701 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
1702 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
1703 FE_CAN_INVERSION_AUTO |
1704 FE_CAN_MUTE_TS
1705 },
1706 .release = stv0367_release,
1707 .init = stv0367ter_init,
1708 .sleep = stv0367ter_sleep,
1709 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]1710 .set_frontend = stv0367ter_set_frontend,
1711 .get_frontend = stv0367ter_get_frontend,
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1712 .get_tune_settings = stv0367_get_tune_settings,
1713 .read_status = stv0367ter_read_status,
1714 .read_ber = stv0367ter_read_ber,/* too slow */
1715/* .read_signal_strength = stv0367_read_signal_strength,*/
1716 .read_snr = stv0367ter_read_snr,
1717 .read_ucblocks = stv0367ter_read_ucblocks,
1718};
1719
1720struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
1721 struct i2c_adapter *i2c)
1722{
1723 struct stv0367_state *state = NULL;
1724 struct stv0367ter_state *ter_state = NULL;
1725
1726 /* allocate memory for the internal state */
1727 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1728 if (state == NULL)
1729 goto error;
1730 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
1731 if (ter_state == NULL)
1732 goto error;
1733
1734 /* setup the state */
1735 state->i2c = i2c;
1736 state->config = config;
1737 state->ter_state = ter_state;
1738 state->fe.ops = stv0367ter_ops;
1739 state->fe.demodulator_priv = state;
1740 state->chip_id = stv0367_readreg(state, 0xf000);
1741
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]1742 /* demod operation options */
1743 state->use_i2c_gatectrl = 1;
Daniel Scheller8881ceb2017-03-29 13:43:04 -0300[diff] [blame]1744 state->deftabs = STV0367_DEFTAB_GENERIC;
Daniel Scheller7718dcf2017-03-29 13:43:06 -0300[diff] [blame]1745 state->reinit_on_setfrontend = 1;
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]1746 state->auto_if_khz = 0;
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]1747
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1748 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1749
1750 /* check if the demod is there */
1751 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1752 goto error;
1753
1754 return &state->fe;
1755
1756error:
1757 kfree(ter_state);
1758 kfree(state);
1759 return NULL;
1760}
1761EXPORT_SYMBOL(stv0367ter_attach);
1762
1763static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
1764{
1765 struct stv0367_state *state = fe->demodulator_priv;
1766
1767 dprintk("%s:\n", __func__);
1768
1769 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1770
1771 return 0;
1772}
1773
1774static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
1775{
1776 struct stv0367_state *state = fe->demodulator_priv;
1777 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
1778 u32 M, N, P;
1779
1780
1781 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1782 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1783 if (N == 0)
1784 N = N + 1;
1785
1786 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1787 if (M == 0)
1788 M = M + 1;
1789
1790 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1791
1792 if (P > 5)
1793 P = 5;
1794
1795 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
1796 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
1797 mclk_Hz);
1798 } else
1799 mclk_Hz = ExtClk_Hz;
1800
1801 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
1802
1803 return mclk_Hz;
1804}
1805
1806static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
1807{
1808 u32 ADCClk_Hz = ExtClk_Hz;
1809
1810 ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
1811
1812 return ADCClk_Hz;
1813}
1814
Mauro Carvalho Chehab8c8ca1c2012-10-27 11:26:42 -0300[diff] [blame]1815static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1816 u32 SymbolRate,
1817 enum stv0367cab_mod QAMSize)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1818{
1819 /* Set QAM size */
1820 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1821
1822 /* Set Registers settings specific to the QAM size */
1823 switch (QAMSize) {
1824 case FE_CAB_MOD_QAM4:
1825 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1826 break;
1827 case FE_CAB_MOD_QAM16:
1828 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1829 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1830 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1831 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1832 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1833 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1834 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1835 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1836 break;
1837 case FE_CAB_MOD_QAM32:
1838 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1839 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1840 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1841 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1842 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1843 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1844 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1845 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1846 break;
1847 case FE_CAB_MOD_QAM64:
1848 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1849 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
Daniel Scheller8b39f072017-03-29 13:43:09 -0300[diff] [blame]1850 if (SymbolRate > 4500000) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1851 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1852 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1853 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
Daniel Scheller8b39f072017-03-29 13:43:09 -0300[diff] [blame]1854 } else if (SymbolRate > 2500000) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1855 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1856 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1857 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1858 } else {
1859 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1860 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1861 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1862 }
1863 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1864 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1865 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1866 break;
1867 case FE_CAB_MOD_QAM128:
1868 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1869 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1870 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1871 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
Daniel Scheller8b39f072017-03-29 13:43:09 -0300[diff] [blame]1872 if (SymbolRate > 4500000)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1873 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
Daniel Scheller8b39f072017-03-29 13:43:09 -0300[diff] [blame]1874 else if (SymbolRate > 2500000)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1875 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1876 else
1877 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1878
1879 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1880 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1881 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1882 break;
1883 case FE_CAB_MOD_QAM256:
1884 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1885 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1886 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
Daniel Scheller8b39f072017-03-29 13:43:09 -0300[diff] [blame]1887 if (SymbolRate > 4500000)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1888 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
Daniel Scheller8b39f072017-03-29 13:43:09 -0300[diff] [blame]1889 else if (SymbolRate > 2500000)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]1890 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1891 else
1892 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1893
1894 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1895 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1896 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1897 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1898 break;
1899 case FE_CAB_MOD_QAM512:
1900 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1901 break;
1902 case FE_CAB_MOD_QAM1024:
1903 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1904 break;
1905 default:
1906 break;
1907 }
1908
1909 return QAMSize;
1910}
1911
1912static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1913 u32 adc_hz, s32 derot_hz)
1914{
1915 u32 sampled_if = 0;
1916 u32 adc_khz;
1917
1918 adc_khz = adc_hz / 1000;
1919
1920 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
1921
1922 if (adc_khz != 0) {
1923 if (derot_hz < 1000000)
1924 derot_hz = adc_hz / 4; /* ZIF operation */
1925 if (derot_hz > adc_hz)
1926 derot_hz = derot_hz - adc_hz;
1927 sampled_if = (u32)derot_hz / 1000;
1928 sampled_if *= 32768;
1929 sampled_if /= adc_khz;
1930 sampled_if *= 256;
1931 }
1932
1933 if (sampled_if > 8388607)
1934 sampled_if = 8388607;
1935
1936 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
1937
1938 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1939 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1940 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1941
1942 return derot_hz;
1943}
1944
1945static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1946{
1947 u32 sampled_if;
1948
1949 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1950 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1951 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1952
1953 sampled_if /= 256;
1954 sampled_if *= (adc_hz / 1000);
1955 sampled_if += 1;
1956 sampled_if /= 32768;
1957
1958 return sampled_if;
1959}
1960
1961static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1962 u32 mclk_hz, u32 SymbolRate,
1963 enum stv0367cab_mod QAMSize)
1964{
1965 u32 QamSizeCorr = 0;
1966 u32 u32_tmp = 0, u32_tmp1 = 0;
1967 u32 adp_khz;
1968
1969 dprintk("%s:\n", __func__);
1970
1971 /* Set Correction factor of SRC gain */
1972 switch (QAMSize) {
1973 case FE_CAB_MOD_QAM4:
1974 QamSizeCorr = 1110;
1975 break;
1976 case FE_CAB_MOD_QAM16:
1977 QamSizeCorr = 1032;
1978 break;
1979 case FE_CAB_MOD_QAM32:
1980 QamSizeCorr = 954;
1981 break;
1982 case FE_CAB_MOD_QAM64:
1983 QamSizeCorr = 983;
1984 break;
1985 case FE_CAB_MOD_QAM128:
1986 QamSizeCorr = 957;
1987 break;
1988 case FE_CAB_MOD_QAM256:
1989 QamSizeCorr = 948;
1990 break;
1991 case FE_CAB_MOD_QAM512:
1992 QamSizeCorr = 0;
1993 break;
1994 case FE_CAB_MOD_QAM1024:
1995 QamSizeCorr = 944;
1996 break;
1997 default:
1998 break;
1999 }
2000
2001 /* Transfer ratio calculation */
2002 if (adc_hz != 0) {
2003 u32_tmp = 256 * SymbolRate;
2004 u32_tmp = u32_tmp / adc_hz;
2005 }
2006 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2007
2008 /* Symbol rate and SRC gain calculation */
2009 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2010 if (adp_khz != 0) {
2011 u32_tmp = SymbolRate;
2012 u32_tmp1 = SymbolRate;
2013
2014 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2015 /* Symbol rate calculation */
2016 u32_tmp *= 2048; /* 2048 = 2^11 */
2017 u32_tmp = u32_tmp / adp_khz;
2018 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2019 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2020 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2021
2022 /* SRC Gain Calculation */
2023 u32_tmp1 *= 2048; /* *2*2^10 */
2024 u32_tmp1 /= 439; /* *2/878 */
2025 u32_tmp1 *= 256; /* *2^8 */
2026 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2027 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2028 u32_tmp1 = u32_tmp1 / 10000000;
2029
2030 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2031 /* Symbol rate calculation */
2032 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2033 u32_tmp = u32_tmp / adp_khz;
2034 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2035 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2036 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2037
2038 /* SRC Gain Calculation */
2039 u32_tmp1 *= 1024; /* *2*2^9 */
2040 u32_tmp1 /= 439; /* *2/878 */
2041 u32_tmp1 *= 256; /* *2^8 */
2042 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2043 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2044 u32_tmp1 = u32_tmp1 / 5000000;
2045 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2046 /* Symbol rate calculation */
2047 u32_tmp *= 512 ; /* 512 = 2**9 */
2048 u32_tmp = u32_tmp / adp_khz;
2049 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2050 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2051 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2052
2053 /* SRC Gain Calculation */
2054 u32_tmp1 *= 512; /* *2*2^8 */
2055 u32_tmp1 /= 439; /* *2/878 */
2056 u32_tmp1 *= 256; /* *2^8 */
2057 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2058 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2059 u32_tmp1 = u32_tmp1 / 2500000;
2060 } else {
2061 /* Symbol rate calculation */
2062 u32_tmp *= 256 ; /* 256 = 2**8 */
2063 u32_tmp = u32_tmp / adp_khz;
2064 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2065 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2066 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2067
2068 /* SRC Gain Calculation */
2069 u32_tmp1 *= 256; /* 2*2^7 */
2070 u32_tmp1 /= 439; /* *2/878 */
2071 u32_tmp1 *= 256; /* *2^8 */
2072 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2073 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2074 u32_tmp1 = u32_tmp1 / 1250000;
2075 }
2076 }
2077#if 0
2078 /* Filters' coefficients are calculated and written
2079 into registers only if the filters are enabled */
2080 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2081 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2082 SymbolRate);
2083 /* AllPass filter must be enabled
2084 when the adjacents filter is used */
2085 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2086 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2087 } else
2088 /* AllPass filter must be disabled
2089 when the adjacents filter is not used */
2090#endif
2091 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2092
2093 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2094 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2095 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2096 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2097
2098 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2099 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2100
2101 return SymbolRate ;
2102}
2103
2104static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2105{
2106 u32 regsym;
2107 u32 adp_khz;
2108
2109 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2110 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2111 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2112 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2113
2114 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2115
2116 if (regsym < 134217728) { /* 134217728L = 2**27*/
2117 regsym = regsym * 32; /* 32 = 2**5 */
2118 regsym = regsym / 32768; /* 32768L = 2**15 */
2119 regsym = adp_khz * regsym; /* AdpClk in kHz */
2120 regsym = regsym / 128; /* 128 = 2**7 */
2121 regsym *= 125 ; /* 125 = 1000/2**3 */
2122 regsym /= 2048 ; /* 2048 = 2**11 */
2123 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2124 regsym = regsym * 16; /* 16 = 2**4 */
2125 regsym = regsym / 32768; /* 32768L = 2**15 */
2126 regsym = adp_khz * regsym; /* AdpClk in kHz */
2127 regsym = regsym / 128; /* 128 = 2**7 */
2128 regsym *= 125 ; /* 125 = 1000/2**3*/
2129 regsym /= 1024 ; /* 256 = 2**10*/
2130 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2131 regsym = regsym * 8; /* 8 = 2**3 */
2132 regsym = regsym / 32768; /* 32768L = 2**15 */
2133 regsym = adp_khz * regsym; /* AdpClk in kHz */
2134 regsym = regsym / 128; /* 128 = 2**7 */
2135 regsym *= 125 ; /* 125 = 1000/2**3 */
2136 regsym /= 512 ; /* 128 = 2**9 */
2137 } else {
2138 regsym = regsym * 4; /* 4 = 2**2 */
2139 regsym = regsym / 32768; /* 32768L = 2**15 */
2140 regsym = adp_khz * regsym; /* AdpClk in kHz */
2141 regsym = regsym / 128; /* 128 = 2**7 */
2142 regsym *= 125 ; /* 125 = 1000/2**3 */
2143 regsym /= 256 ; /* 64 = 2**8 */
2144 }
2145
2146 return regsym;
2147}
2148
Mauro Carvalho Chehab0df289a2015-06-07 14:53:52 -0300[diff] [blame]2149static int stv0367cab_read_status(struct dvb_frontend *fe,
2150 enum fe_status *status)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2151{
2152 struct stv0367_state *state = fe->demodulator_priv;
2153
2154 dprintk("%s:\n", __func__);
2155
2156 *status = 0;
2157
Daniel Schellercae7a902017-03-29 13:43:08 -0300[diff] [blame]2158 if (stv0367_readbits(state, (state->cab_state->qamfec_status_reg ?
2159 state->cab_state->qamfec_status_reg : F367CAB_QAMFEC_LOCK))) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2160 *status |= FE_HAS_LOCK;
2161 dprintk("%s: stv0367 has locked\n", __func__);
2162 }
2163
2164 return 0;
2165}
2166
2167static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2168{
2169 struct stv0367_state *state = fe->demodulator_priv;
2170
2171 dprintk("%s:\n", __func__);
2172
2173 if (standby_on) {
2174 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2175 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2176 stv0367_writebits(state, F367CAB_STDBY, 1);
2177 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2178 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2179 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2180 stv0367_writebits(state, F367CAB_POFFQ, 1);
2181 stv0367_writebits(state, F367CAB_POFFI, 1);
2182 } else {
2183 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2184 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2185 stv0367_writebits(state, F367CAB_STDBY, 0);
2186 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2187 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2188 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2189 stv0367_writebits(state, F367CAB_POFFQ, 0);
2190 stv0367_writebits(state, F367CAB_POFFI, 0);
2191 }
2192
2193 return 0;
2194}
2195
2196static int stv0367cab_sleep(struct dvb_frontend *fe)
2197{
2198 return stv0367cab_standby(fe, 1);
2199}
2200
Mauro Carvalho Chehab8c8ca1c2012-10-27 11:26:42 -0300[diff] [blame]2201static int stv0367cab_init(struct dvb_frontend *fe)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2202{
2203 struct stv0367_state *state = fe->demodulator_priv;
2204 struct stv0367cab_state *cab_state = state->cab_state;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2205
2206 dprintk("%s:\n", __func__);
2207
Daniel Scheller8881ceb2017-03-29 13:43:04 -0300[diff] [blame]2208 stv0367_write_table(state,
2209 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2210
2211 switch (state->config->ts_mode) {
2212 case STV0367_DVBCI_CLOCK:
2213 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2214 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2215 break;
2216 case STV0367_SERIAL_PUNCT_CLOCK:
2217 case STV0367_SERIAL_CONT_CLOCK:
2218 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2219 break;
2220 case STV0367_PARALLEL_PUNCT_CLOCK:
2221 case STV0367_OUTPUTMODE_DEFAULT:
2222 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2223 break;
2224 }
2225
2226 switch (state->config->clk_pol) {
2227 case STV0367_RISINGEDGE_CLOCK:
2228 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2229 break;
2230 case STV0367_FALLINGEDGE_CLOCK:
2231 case STV0367_CLOCKPOLARITY_DEFAULT:
2232 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2233 break;
2234 }
2235
2236 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2237
2238 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2239
2240 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2241
2242 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2243
2244 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2245
2246 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2247 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2248
2249 return 0;
2250}
2251static
2252enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2253 struct dtv_frontend_properties *p)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2254{
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2255 struct stv0367cab_state *cab_state = state->cab_state;
2256 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2257 u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2258 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2259 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2260 u8 TrackAGCAccum;
2261 s32 tmp;
2262
2263 dprintk("%s:\n", __func__);
2264
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2265 stv0367_get_if_khz(state, &ifkhz);
2266
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2267 /* Timeouts calculation */
2268 /* A max lock time of 25 ms is allowed for delayed AGC */
2269 AGCTimeOut = 25;
2270 /* 100000 symbols needed by the TRL as a maximum value */
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2271 TRLTimeOut = 100000000 / p->symbol_rate;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2272 /* CRLSymbols is the needed number of symbols to achieve a lock
2273 within [-4%, +4%] of the symbol rate.
2274 CRL timeout is calculated
2275 for a lock within [-search_range, +search_range].
2276 EQL timeout can be changed depending on
2277 the micro-reflections we want to handle.
2278 A characterization must be performed
2279 with these echoes to get new timeout values.
2280 */
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2281 switch (p->modulation) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2282 case QAM_16:
2283 CRLSymbols = 150000;
2284 EQLTimeOut = 100;
2285 break;
2286 case QAM_32:
2287 CRLSymbols = 250000;
2288 EQLTimeOut = 100;
2289 break;
2290 case QAM_64:
2291 CRLSymbols = 200000;
2292 EQLTimeOut = 100;
2293 break;
2294 case QAM_128:
2295 CRLSymbols = 250000;
2296 EQLTimeOut = 100;
2297 break;
2298 case QAM_256:
2299 CRLSymbols = 250000;
2300 EQLTimeOut = 100;
2301 break;
2302 default:
2303 CRLSymbols = 200000;
2304 EQLTimeOut = 100;
2305 break;
2306 }
2307#if 0
2308 if (pIntParams->search_range < 0) {
2309 CRLTimeOut = (25 * CRLSymbols *
2310 (-pIntParams->search_range / 1000)) /
2311 (pIntParams->symbol_rate / 1000);
2312 } else
2313#endif
2314 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2315 (p->symbol_rate / 1000);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2316
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2317 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2318 /* Timeouts below 50ms are coerced */
2319 if (CRLTimeOut < 50)
2320 CRLTimeOut = 50;
2321 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2322 the spectrum inversion needs to be changed.
2323 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2324 */
2325 FECTimeOut = 20;
2326 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2327
2328 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2329
2330 /* Reset the TRL to ensure nothing starts until the
2331 AGC is stable which ensures a better lock time
2332 */
2333 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2334 /* Set AGC accumulation time to minimum and lock threshold to maximum
2335 in order to speed up the AGC lock */
2336 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2337 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2338 /* Modulus Mapper is disabled */
2339 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2340 /* Disable the sweep function */
2341 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2342 /* The sweep function is never used, Sweep rate must be set to 0 */
2343 /* Set the derotator frequency in Hz */
2344 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2345 (1000 * (s32)ifkhz + cab_state->derot_offset));
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2346 /* Disable the Allpass Filter when the symbol rate is out of range */
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2347 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2348 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2349 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2350 }
2351#if 0
2352 /* Check if the tuner is locked */
2353 tuner_lock = stv0367cab_tuner_get_status(fe);
2354 if (tuner_lock == 0)
2355 return FE_367CAB_NOTUNER;
2356#endif
Geert Uytterhoeven83a35e32013-06-28 11:27:31 +0200[diff] [blame]2357 /* Release the TRL to start demodulator acquisition */
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2358 /* Wait for QAM lock */
2359 LockTime = 0;
2360 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2361 do {
2362 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2363 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2364 (QAM_Lock == 0x04))
2365 /*
2366 * We don't wait longer, the frequency/phase offset
2367 * must be too big
2368 */
2369 LockTime = DemodTimeOut;
2370 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2371 (QAM_Lock == 0x02))
2372 /*
2373 * We don't wait longer, either there is no signal or
2374 * it is not the right symbol rate or it is an analog
2375 * carrier
2376 */
2377 {
2378 LockTime = DemodTimeOut;
2379 u32_tmp = stv0367_readbits(state,
2380 F367CAB_AGC_PWR_WORD_LO) +
2381 (stv0367_readbits(state,
2382 F367CAB_AGC_PWR_WORD_ME) << 8) +
2383 (stv0367_readbits(state,
2384 F367CAB_AGC_PWR_WORD_HI) << 16);
2385 if (u32_tmp >= 131072)
2386 u32_tmp = 262144 - u32_tmp;
2387 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2388 F367CAB_AGC_IF_BWSEL)));
2389
2390 if (u32_tmp < stv0367_readbits(state,
2391 F367CAB_AGC_PWRREF_LO) +
2392 256 * stv0367_readbits(state,
2393 F367CAB_AGC_PWRREF_HI) - 10)
2394 QAM_Lock = 0x0f;
2395 } else {
2396 usleep_range(10000, 20000);
2397 LockTime += 10;
2398 }
2399 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2400 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2401
2402 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2403
2404 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2405 (LockTime < DemodTimeOut));
2406
2407 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2408
2409 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2410 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2411 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2412 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2413
2414 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2415 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2416
2417 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2418 /* Wait for FEC lock */
2419 LockTime = 0;
2420 do {
2421 usleep_range(5000, 7000);
2422 LockTime += 5;
2423 QAMFEC_Lock = stv0367_readbits(state,
Daniel Schellercae7a902017-03-29 13:43:08 -0300[diff] [blame]2424 (state->cab_state->qamfec_status_reg ?
2425 state->cab_state->qamfec_status_reg :
2426 F367CAB_QAMFEC_LOCK));
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2427 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2428 } else
2429 QAMFEC_Lock = 0;
2430
2431 if (QAMFEC_Lock) {
2432 signalType = FE_CAB_DATAOK;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2433 cab_state->spect_inv = stv0367_readbits(state,
2434 F367CAB_QUAD_INV);
2435#if 0
2436/* not clear for me */
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2437 if (ifkhz != 0) {
2438 if (ifkhz > cab_state->adc_clk / 1000) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2439 cab_state->freq_khz =
2440 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2441 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2442 - cab_state->adc_clk / 1000 + ifkhz;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2443 } else {
2444 cab_state->freq_khz =
2445 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2446 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2447 + ifkhz;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2448 }
2449 } else {
2450 cab_state->freq_khz =
2451 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
2452 stv0367cab_get_derot_freq(state,
2453 cab_state->adc_clk) -
2454 cab_state->adc_clk / 4000;
2455 }
2456#endif
2457 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2458 cab_state->mclk);
2459 cab_state->locked = 1;
2460
2461 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2462 } else {
2463 switch (QAM_Lock) {
2464 case 1:
2465 signalType = FE_CAB_NOAGC;
2466 break;
2467 case 2:
2468 signalType = FE_CAB_NOTIMING;
2469 break;
2470 case 3:
2471 signalType = FE_CAB_TIMINGOK;
2472 break;
2473 case 4:
2474 signalType = FE_CAB_NOCARRIER;
2475 break;
2476 case 5:
2477 signalType = FE_CAB_CARRIEROK;
2478 break;
2479 case 7:
2480 signalType = FE_CAB_NOBLIND;
2481 break;
2482 case 8:
2483 signalType = FE_CAB_BLINDOK;
2484 break;
2485 case 10:
2486 signalType = FE_CAB_NODEMOD;
2487 break;
2488 case 11:
2489 signalType = FE_CAB_DEMODOK;
2490 break;
2491 case 12:
2492 signalType = FE_CAB_DEMODOK;
2493 break;
2494 case 13:
2495 signalType = FE_CAB_NODEMOD;
2496 break;
2497 case 14:
2498 signalType = FE_CAB_NOBLIND;
2499 break;
2500 case 15:
2501 signalType = FE_CAB_NOSIGNAL;
2502 break;
2503 default:
2504 break;
2505 }
2506
2507 }
2508
2509 /* Set the AGC control values to tracking values */
2510 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2511 return signalType;
2512}
2513
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2514static int stv0367cab_set_frontend(struct dvb_frontend *fe)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2515{
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2516 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2517 struct stv0367_state *state = fe->demodulator_priv;
2518 struct stv0367cab_state *cab_state = state->cab_state;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2519 enum stv0367cab_mod QAMSize = 0;
2520
2521 dprintk("%s: freq = %d, srate = %d\n", __func__,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2522 p->frequency, p->symbol_rate);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2523
2524 cab_state->derot_offset = 0;
2525
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2526 switch (p->modulation) {
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2527 case QAM_16:
2528 QAMSize = FE_CAB_MOD_QAM16;
2529 break;
2530 case QAM_32:
2531 QAMSize = FE_CAB_MOD_QAM32;
2532 break;
2533 case QAM_64:
2534 QAMSize = FE_CAB_MOD_QAM64;
2535 break;
2536 case QAM_128:
2537 QAMSize = FE_CAB_MOD_QAM128;
2538 break;
2539 case QAM_256:
2540 QAMSize = FE_CAB_MOD_QAM256;
2541 break;
2542 default:
2543 break;
2544 }
2545
Daniel Scheller7718dcf2017-03-29 13:43:06 -0300[diff] [blame]2546 if (state->reinit_on_setfrontend)
2547 stv0367cab_init(fe);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2548
2549 /* Tuner Frequency Setting */
2550 if (fe->ops.tuner_ops.set_params) {
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]2551 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2552 fe->ops.i2c_gate_ctrl(fe, 1);
Mauro Carvalho Chehab14d24d12011-12-24 12:24:33 -0300[diff] [blame]2553 fe->ops.tuner_ops.set_params(fe);
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]2554 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2555 fe->ops.i2c_gate_ctrl(fe, 0);
2556 }
2557
2558 stv0367cab_SetQamSize(
2559 state,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2560 p->symbol_rate,
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2561 QAMSize);
2562
2563 stv0367cab_set_srate(state,
2564 cab_state->adc_clk,
2565 cab_state->mclk,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2566 p->symbol_rate,
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2567 QAMSize);
2568 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2569 cab_state->state = stv0367cab_algo(state, p);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2570 return 0;
2571}
2572
Mauro Carvalho Chehab7e3e68b2016-02-04 12:58:30 -0200[diff] [blame]2573static int stv0367cab_get_frontend(struct dvb_frontend *fe,
2574 struct dtv_frontend_properties *p)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2575{
2576 struct stv0367_state *state = fe->demodulator_priv;
2577 struct stv0367cab_state *cab_state = state->cab_state;
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2578 u32 ifkhz = 0;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2579
2580 enum stv0367cab_mod QAMSize;
2581
2582 dprintk("%s:\n", __func__);
2583
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2584 stv0367_get_if_khz(state, &ifkhz);
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2585 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2586
2587 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2588 switch (QAMSize) {
2589 case FE_CAB_MOD_QAM16:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2590 p->modulation = QAM_16;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2591 break;
2592 case FE_CAB_MOD_QAM32:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2593 p->modulation = QAM_32;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2594 break;
2595 case FE_CAB_MOD_QAM64:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2596 p->modulation = QAM_64;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2597 break;
2598 case FE_CAB_MOD_QAM128:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2599 p->modulation = QAM_128;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2600 break;
Maks Naumoveafeda92014-08-15 16:23:20 -0300[diff] [blame]2601 case FE_CAB_MOD_QAM256:
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2602 p->modulation = QAM_256;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2603 break;
2604 default:
2605 break;
2606 }
2607
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2608 p->frequency = stv0367_get_tuner_freq(fe);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2609
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2610 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2611
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2612 if (ifkhz == 0) {
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2613 p->frequency +=
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2614 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2615 cab_state->adc_clk / 4000);
2616 return 0;
2617 }
2618
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2619 if (ifkhz > cab_state->adc_clk / 1000)
2620 p->frequency += (ifkhz
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2621 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2622 - cab_state->adc_clk / 1000);
2623 else
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2624 p->frequency += (ifkhz
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2625 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2626
2627 return 0;
2628}
2629
2630#if 0
2631void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2632 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
2633{
2634 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2635 stv0367cab_GetPacketsCount(state, Monitor_results);
2636
2637 return;
2638}
2639
2640static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
2641{
2642 struct stv0367_state *state = fe->demodulator_priv;
2643
2644 return 0;
2645}
2646#endif
2647static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2648{
2649 s32 rfLevel = 0;
2650 s32 RfAgcPwm = 0, IfAgcPwm = 0;
2651 u8 i;
2652
2653 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2654
2655 RfAgcPwm =
2656 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2657 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2658 RfAgcPwm = 100 * RfAgcPwm / 1023;
2659
2660 IfAgcPwm =
2661 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2662 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2663 if (IfAgcPwm >= 2048)
2664 IfAgcPwm -= 2048;
2665 else
2666 IfAgcPwm += 2048;
2667
2668 IfAgcPwm = 100 * IfAgcPwm / 4095;
2669
2670 /* For DTT75467 on NIM */
2671 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
2672 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
2673 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
2674 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
2675 break;
2676 }
2677 }
2678 if (i == RF_LOOKUP_TABLE_SIZE)
2679 rfLevel = -56;
2680 } else { /*if IF AGC>10*/
2681 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
2682 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
2683 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
2684 break;
2685 }
2686 }
2687 if (i == RF_LOOKUP_TABLE2_SIZE)
2688 rfLevel = -72;
2689 }
2690 return rfLevel;
2691}
2692
2693static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
2694{
2695 struct stv0367_state *state = fe->demodulator_priv;
2696
2697 s32 signal = stv0367cab_get_rf_lvl(state);
2698
2699 dprintk("%s: signal=%d dBm\n", __func__, signal);
2700
2701 if (signal <= -72)
2702 *strength = 65535;
2703 else
2704 *strength = (22 + signal) * (-1311);
2705
2706 dprintk("%s: strength=%d\n", __func__, (*strength));
2707
2708 return 0;
2709}
2710
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2711static int stv0367cab_snr_power(struct dvb_frontend *fe)
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2712{
2713 struct stv0367_state *state = fe->demodulator_priv;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2714 enum stv0367cab_mod QAMSize;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2715
2716 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2717 switch (QAMSize) {
2718 case FE_CAB_MOD_QAM4:
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2719 return 21904;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2720 case FE_CAB_MOD_QAM16:
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2721 return 20480;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2722 case FE_CAB_MOD_QAM32:
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2723 return 23040;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2724 case FE_CAB_MOD_QAM64:
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2725 return 21504;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2726 case FE_CAB_MOD_QAM128:
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2727 return 23616;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2728 case FE_CAB_MOD_QAM256:
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2729 return 21760;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2730 case FE_CAB_MOD_QAM1024:
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2731 return 21280;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2732 default:
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2733 break;
2734 }
2735
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2736 return 1;
2737}
2738
2739static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
2740{
2741 struct stv0367_state *state = fe->demodulator_priv;
2742 u32 regval = 0;
2743 int i;
2744
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2745 for (i = 0; i < 10; i++) {
2746 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2747 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2748 }
2749
Daniel Schellerb138afd2017-06-21 16:45:42 -0300[diff] [blame]2750 if (avgdiv)
2751 regval /= 10;
2752
2753 return regval;
2754}
2755
2756static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
2757{
2758 struct stv0367_state *state = fe->demodulator_priv;
2759 u32 noisepercentage;
2760 u32 regval = 0, temp = 0;
2761 int power;
2762
2763 power = stv0367cab_snr_power(fe);
2764 regval = stv0367cab_snr_readreg(fe, 1);
2765
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2766 if (regval != 0) {
2767 temp = power
2768 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2769 temp /= regval;
2770 }
2771
2772 /* table values, not needed to calculate logarithms */
2773 if (temp >= 5012)
2774 noisepercentage = 100;
2775 else if (temp >= 3981)
2776 noisepercentage = 93;
2777 else if (temp >= 3162)
2778 noisepercentage = 86;
2779 else if (temp >= 2512)
2780 noisepercentage = 79;
2781 else if (temp >= 1995)
2782 noisepercentage = 72;
2783 else if (temp >= 1585)
2784 noisepercentage = 65;
2785 else if (temp >= 1259)
2786 noisepercentage = 58;
2787 else if (temp >= 1000)
2788 noisepercentage = 50;
2789 else if (temp >= 794)
2790 noisepercentage = 43;
2791 else if (temp >= 501)
2792 noisepercentage = 36;
2793 else if (temp >= 316)
2794 noisepercentage = 29;
2795 else if (temp >= 200)
2796 noisepercentage = 22;
2797 else if (temp >= 158)
2798 noisepercentage = 14;
2799 else if (temp >= 126)
2800 noisepercentage = 7;
2801 else
2802 noisepercentage = 0;
2803
2804 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
2805
2806 *snr = (noisepercentage * 65535) / 100;
2807
2808 return 0;
2809}
2810
Abylay Ospan78db66e2011-01-02 09:12:00 -0300[diff] [blame]2811static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
2812{
2813 struct stv0367_state *state = fe->demodulator_priv;
2814 int corrected, tscount;
2815
2816 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2817 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2818 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2819 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2820 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2821 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2822
2823 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
2824 __func__, *ucblocks, corrected, tscount);
2825
2826 return 0;
2827};
2828
Max Kellermannbd336e62016-08-09 18:32:21 -0300[diff] [blame]2829static const struct dvb_frontend_ops stv0367cab_ops = {
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2830 .delsys = { SYS_DVBC_ANNEX_A },
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2831 .info = {
2832 .name = "ST STV0367 DVB-C",
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2833 .frequency_min = 47000000,
2834 .frequency_max = 862000000,
2835 .frequency_stepsize = 62500,
2836 .symbol_rate_min = 870000,
2837 .symbol_rate_max = 11700000,
2838 .caps = 0x400 |/* FE_CAN_QAM_4 */
2839 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
2840 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
2841 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
2842 },
2843 .release = stv0367_release,
2844 .init = stv0367cab_init,
2845 .sleep = stv0367cab_sleep,
2846 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
Mauro Carvalho Chehab285d55a2011-12-26 13:03:00 -0300[diff] [blame]2847 .set_frontend = stv0367cab_set_frontend,
2848 .get_frontend = stv0367cab_get_frontend,
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2849 .read_status = stv0367cab_read_status,
2850/* .read_ber = stv0367cab_read_ber, */
2851 .read_signal_strength = stv0367cab_read_strength,
2852 .read_snr = stv0367cab_read_snr,
Abylay Ospan78db66e2011-01-02 09:12:00 -0300[diff] [blame]2853 .read_ucblocks = stv0367cab_read_ucblcks,
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2854 .get_tune_settings = stv0367_get_tune_settings,
2855};
2856
2857struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
2858 struct i2c_adapter *i2c)
2859{
2860 struct stv0367_state *state = NULL;
2861 struct stv0367cab_state *cab_state = NULL;
2862
2863 /* allocate memory for the internal state */
2864 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2865 if (state == NULL)
2866 goto error;
2867 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
2868 if (cab_state == NULL)
2869 goto error;
2870
2871 /* setup the state */
2872 state->i2c = i2c;
2873 state->config = config;
2874 cab_state->search_range = 280000;
Daniel Schellercae7a902017-03-29 13:43:08 -0300[diff] [blame]2875 cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2876 state->cab_state = cab_state;
2877 state->fe.ops = stv0367cab_ops;
2878 state->fe.demodulator_priv = state;
2879 state->chip_id = stv0367_readreg(state, 0xf000);
2880
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]2881 /* demod operation options */
2882 state->use_i2c_gatectrl = 1;
Daniel Scheller8881ceb2017-03-29 13:43:04 -0300[diff] [blame]2883 state->deftabs = STV0367_DEFTAB_GENERIC;
Daniel Scheller7718dcf2017-03-29 13:43:06 -0300[diff] [blame]2884 state->reinit_on_setfrontend = 1;
Daniel Schellerb16338e2017-03-29 13:43:07 -0300[diff] [blame]2885 state->auto_if_khz = 0;
Daniel Schellerf61c2992017-03-29 13:43:01 -0300[diff] [blame]2886
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]2887 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2888
2889 /* check if the demod is there */
2890 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2891 goto error;
2892
2893 return &state->fe;
2894
2895error:
2896 kfree(cab_state);
2897 kfree(state);
2898 return NULL;
2899}
2900EXPORT_SYMBOL(stv0367cab_attach);
2901
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]2902/*
2903 * Functions for operation on Digital Devices hardware
2904 */
2905
2906static void stv0367ddb_setup_ter(struct stv0367_state *state)
2907{
2908 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2909 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2910 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2911 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2912 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2913 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2914
2915 /* Tuner Setup */
2916 /* Buffer Q disabled, I Enabled, unsigned ADC */
2917 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2918 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2919
2920 /* Clock setup */
2921 /* PLL bypassed and disabled */
2922 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2923 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2924
2925 /* IC runs at 54 MHz with a 27 MHz crystal */
2926 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2927
2928 msleep(50);
2929 /* PLL enabled and used */
2930 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2931
2932 state->activedemod = demod_ter;
2933}
2934
2935static void stv0367ddb_setup_cab(struct stv0367_state *state)
2936{
2937 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2938 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2939 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2940 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2941 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2942 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2943
2944 /* Tuner Setup */
2945 /* Buffer Q disabled, I Enabled, signed ADC */
2946 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2947 /* ADCQ disabled */
2948 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2949
2950 /* Clock setup */
2951 /* PLL bypassed and disabled */
2952 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2953 /* Set QAM */
2954 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2955
2956 /* IC runs at 58 MHz with a 27 MHz crystal */
2957 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2958
2959 msleep(50);
2960 /* PLL enabled and used */
2961 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2962
2963 state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
2964 state->config->xtal);
2965 state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
2966 state->config->xtal);
2967
2968 state->activedemod = demod_cab;
2969}
2970
2971static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
2972{
2973 struct stv0367_state *state = fe->demodulator_priv;
2974
2975 switch (fe->dtv_property_cache.delivery_system) {
2976 case SYS_DVBT:
2977 if (state->activedemod != demod_ter)
2978 stv0367ddb_setup_ter(state);
2979
2980 return stv0367ter_set_frontend(fe);
2981 case SYS_DVBC_ANNEX_A:
2982 if (state->activedemod != demod_cab)
2983 stv0367ddb_setup_cab(state);
2984
2985 /* protect against division error oopses */
2986 if (fe->dtv_property_cache.symbol_rate == 0) {
2987 printk(KERN_ERR "Invalid symbol rate\n");
2988 return -EINVAL;
2989 }
2990
2991 return stv0367cab_set_frontend(fe);
2992 default:
2993 break;
2994 }
2995
2996 return -EINVAL;
2997}
2998
Daniel Scheller4043eb22017-06-21 16:45:41 -0300[diff] [blame]2999static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
3000{
3001 struct stv0367_state *state = fe->demodulator_priv;
3002 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3003 u32 ucblocks = 0;
3004
3005 switch (state->activedemod) {
3006 case demod_ter:
3007 stv0367ter_read_ucblocks(fe, &ucblocks);
3008 break;
3009 case demod_cab:
3010 stv0367cab_read_ucblcks(fe, &ucblocks);
3011 break;
3012 default:
3013 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3014 return;
3015 }
3016
3017 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
3018 p->block_error.stat[0].uvalue = ucblocks;
3019}
3020
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3021static int stv0367ddb_read_status(struct dvb_frontend *fe,
3022 enum fe_status *status)
3023{
3024 struct stv0367_state *state = fe->demodulator_priv;
Daniel Scheller4043eb22017-06-21 16:45:41 -0300[diff] [blame]3025 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3026 int ret;
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3027
3028 switch (state->activedemod) {
3029 case demod_ter:
Daniel Scheller4043eb22017-06-21 16:45:41 -0300[diff] [blame]3030 ret = stv0367ter_read_status(fe, status);
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3031 break;
Daniel Scheller4043eb22017-06-21 16:45:41 -0300[diff] [blame]3032 case demod_cab:
3033 ret = stv0367cab_read_status(fe, status);
3034 break;
3035 default:
3036 return 0;
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3037 }
3038
Daniel Scheller4043eb22017-06-21 16:45:41 -0300[diff] [blame]3039 /* stop and report on *_read_status failure */
3040 if (ret)
3041 return ret;
3042
3043 /* stop if demod isn't locked */
3044 if (!(*status & FE_HAS_LOCK)) {
3045 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3046 return ret;
3047 }
3048
3049 stv0367ddb_read_ucblocks(fe);
3050
3051 return 0;
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3052}
3053
3054static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
3055 struct dtv_frontend_properties *p)
3056{
3057 struct stv0367_state *state = fe->demodulator_priv;
3058
3059 switch (state->activedemod) {
3060 case demod_ter:
3061 return stv0367ter_get_frontend(fe, p);
3062 case demod_cab:
3063 return stv0367cab_get_frontend(fe, p);
3064 default:
3065 break;
3066 }
3067
3068 return -EINVAL;
3069}
3070
3071static int stv0367ddb_sleep(struct dvb_frontend *fe)
3072{
3073 struct stv0367_state *state = fe->demodulator_priv;
3074
3075 switch (state->activedemod) {
3076 case demod_ter:
3077 state->activedemod = demod_none;
3078 return stv0367ter_sleep(fe);
3079 case demod_cab:
3080 state->activedemod = demod_none;
3081 return stv0367cab_sleep(fe);
3082 default:
3083 break;
3084 }
3085
3086 return -EINVAL;
3087}
3088
3089static int stv0367ddb_init(struct stv0367_state *state)
3090{
3091 struct stv0367ter_state *ter_state = state->ter_state;
Daniel Scheller4043eb22017-06-21 16:45:41 -0300[diff] [blame]3092 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3093
3094 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3095
3096 if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3097 stv0367_write_table(state,
3098 stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3099
3100 stv0367_write_table(state,
3101 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3102
3103 stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3104 stv0367_write_table(state,
3105 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3106
3107 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3108 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3109 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3110 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3111 stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3112 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3113 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3114 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3115
3116 /* OFDM TS Setup */
3117
3118 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3119 stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3120 stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3121 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3122
3123 stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3124 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3125
3126 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3127
3128 /* Also needed for QAM */
3129 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3130
3131 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3132
3133 /* QAM TS setup, note exact format also depends on descrambler */
3134 /* settings */
3135 /* Inverted Clock, Swap, serial */
3136 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3137
3138 /* Clock setup (PLL bypassed and disabled) */
3139 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3140
3141 /* IC runs at 58 MHz with a 27 MHz crystal */
3142 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3143
3144 /* Tuner setup */
3145 /* Buffer Q disabled, I Enabled, signed ADC */
3146 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3147 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3148
3149 /* Improves the C/N lock limit */
3150 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3151 /* ZIF/IF Automatic mode */
3152 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3153 /* Improving burst noise performances */
3154 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3155 /* Improving ACI performances */
3156 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3157
3158 /* PLL enabled and used */
3159 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3160
3161 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3162
3163 ter_state->pBER = 0;
3164 ter_state->first_lock = 0;
3165 ter_state->unlock_counter = 2;
3166
Daniel Scheller4043eb22017-06-21 16:45:41 -0300[diff] [blame]3167 p->strength.len = 1;
3168 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3169 p->cnr.len = 1;
3170 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3171 p->block_error.len = 1;
3172 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3173
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3174 return 0;
3175}
3176
3177static const struct dvb_frontend_ops stv0367ddb_ops = {
3178 .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
3179 .info = {
3180 .name = "ST STV0367 DDB DVB-C/T",
3181 .frequency_min = 47000000,
3182 .frequency_max = 865000000,
3183 .frequency_stepsize = 166667,
3184 .frequency_tolerance = 0,
3185 .symbol_rate_min = 870000,
3186 .symbol_rate_max = 11700000,
3187 .caps = /* DVB-C */
3188 0x400 |/* FE_CAN_QAM_4 */
3189 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3190 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
Daniel Schellerf9c1e252017-06-21 17:10:54 -0300[diff] [blame]3191 FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3192 /* DVB-T */
Daniel Schellerf9c1e252017-06-21 17:10:54 -0300[diff] [blame]3193 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
3194 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
3195 FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
3196 FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
Daniel Schellerdbbac112017-03-29 13:43:11 -0300[diff] [blame]3197 FE_CAN_MUTE_TS
3198 },
3199 .release = stv0367_release,
3200 .sleep = stv0367ddb_sleep,
3201 .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
3202 .set_frontend = stv0367ddb_set_frontend,
3203 .get_frontend = stv0367ddb_get_frontend,
3204 .get_tune_settings = stv0367_get_tune_settings,
3205 .read_status = stv0367ddb_read_status,
3206};
3207
3208struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
3209 struct i2c_adapter *i2c)
3210{
3211 struct stv0367_state *state = NULL;
3212 struct stv0367ter_state *ter_state = NULL;
3213 struct stv0367cab_state *cab_state = NULL;
3214
3215 /* allocate memory for the internal state */
3216 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3217 if (state == NULL)
3218 goto error;
3219 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
3220 if (ter_state == NULL)
3221 goto error;
3222 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3223 if (cab_state == NULL)
3224 goto error;
3225
3226 /* setup the state */
3227 state->i2c = i2c;
3228 state->config = config;
3229 state->ter_state = ter_state;
3230 cab_state->search_range = 280000;
3231 cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
3232 state->cab_state = cab_state;
3233 state->fe.ops = stv0367ddb_ops;
3234 state->fe.demodulator_priv = state;
3235 state->chip_id = stv0367_readreg(state, R367TER_ID);
3236
3237 /* demod operation options */
3238 state->use_i2c_gatectrl = 0;
3239 state->deftabs = STV0367_DEFTAB_DDB;
3240 state->reinit_on_setfrontend = 0;
3241 state->auto_if_khz = 1;
3242 state->activedemod = demod_none;
3243
3244 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3245
3246 /* check if the demod is there */
3247 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3248 goto error;
3249
3250 dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
3251 state->fe.ops.info.name, state->chip_id,
3252 config->demod_address);
3253
3254 stv0367ddb_init(state);
3255
3256 return &state->fe;
3257
3258error:
3259 kfree(cab_state);
3260 kfree(ter_state);
3261 kfree(state);
3262 return NULL;
3263}
3264EXPORT_SYMBOL(stv0367ddb_attach);
3265
Igor M. Liplianin17cce932011-01-25 17:02:00 -0300[diff] [blame]3266MODULE_PARM_DESC(debug, "Set debug");
3267MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3268
3269MODULE_AUTHOR("Igor M. Liplianin");
3270MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3271MODULE_LICENSE("GPL");