blob: 4f7379fe01e24c5f00c06e2ed92002db531250f4 [file] [log] [blame]
Barry Song156a0992012-08-23 13:41:58 +08001if ARCH_SIRF
2
3menu "CSR SiRF primaII/Marco/Polo Specific Features"
4
5config ARCH_PRIMA2
6 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
7 default y
8 select CPU_V7
Barry Songc1e3c112012-08-23 13:41:59 +08009 select SIRF_IRQ
Russell Kingb1b3f492012-10-06 17:12:25 +010010 select ZONE_DMA
Barry Song156a0992012-08-23 13:41:58 +080011 help
12 Support for CSR SiRFSoC ARM Cortex A9 Platform
13
Barry Song4898de32012-12-20 19:37:32 +080014config ARCH_MARCO
15 bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
16 default y
17 select ARM_GIC
18 select CPU_V7
19 select HAVE_SMP
20 select SMP_ON_UP
21 help
22 Support for CSR SiRFSoC ARM Cortex A9 Platform
23
Barry Song156a0992012-08-23 13:41:58 +080024endmenu
25
Barry Songc1e3c112012-08-23 13:41:59 +080026config SIRF_IRQ
27 bool
28
Barry Song156a0992012-08-23 13:41:58 +080029endif