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gerrit-public.fairphone.software / kernel / msm-5.4 / d6a016616ba834b7da7653effb98d413acde7aa2 / . / arch / arm / boot / dts / at91sam9g45.dtsi
blob: d79021b831c4c7296a1ec3dccdc2ae8e9ca42ff1 [file] [log] [blame]
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]1/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9G45 family SoC";
16 compatible = "atmel,at91sam9g45";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
Nicolas Ferre21f81872012-02-11 15:41:40 +0100[diff] [blame]25 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 gpio3 = &pioD;
29 gpio4 = &pioE;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +0100[diff] [blame]30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]32 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,arm926ejs";
36 };
37 };
38
39 memory@70000000 {
40 reg = <0x70000000 0x10000000>;
41 };
42
43 ahb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 aic: interrupt-controller@fffff000 {
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]56 #interrupt-cells = <2>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]57 compatible = "atmel,at91rm9200-aic";
58 interrupt-controller;
59 interrupt-parent;
60 reg = <0xfffff000 0x200>;
61 };
62
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +0100[diff] [blame]63 pit: timer@fffffd30 {
64 compatible = "atmel,at91sam9260-pit";
65 reg = <0xfffffd30 0xf>;
66 interrupts = <1 4>;
67 };
68
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +0100[diff] [blame]69
70 tcb0: timer@fff7c000 {
71 compatible = "atmel,at91rm9200-tcb";
72 reg = <0xfff7c000 0x100>;
73 interrupts = <18 4>;
74 };
75
76 tcb1: timer@fffd4000 {
77 compatible = "atmel,at91rm9200-tcb";
78 reg = <0xfffd4000 0x100>;
79 interrupts = <18 4>;
80 };
81
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]82 dma: dma-controller@ffffec00 {
83 compatible = "atmel,at91sam9g45-dma";
84 reg = <0xffffec00 0x200>;
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]85 interrupts = <21 4>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]86 };
87
Nicolas Ferre21f81872012-02-11 15:41:40 +0100[diff] [blame]88 pioA: gpio@fffff200 {
89 compatible = "atmel,at91rm9200-gpio";
90 reg = <0xfffff200 0x100>;
91 interrupts = <2 4>;
92 #gpio-cells = <2>;
93 gpio-controller;
94 interrupt-controller;
95 };
96
97 pioB: gpio@fffff400 {
98 compatible = "atmel,at91rm9200-gpio";
99 reg = <0xfffff400 0x100>;
100 interrupts = <3 4>;
101 #gpio-cells = <2>;
102 gpio-controller;
103 interrupt-controller;
104 };
105
106 pioC: gpio@fffff600 {
107 compatible = "atmel,at91rm9200-gpio";
108 reg = <0xfffff600 0x100>;
109 interrupts = <4 4>;
110 #gpio-cells = <2>;
111 gpio-controller;
112 interrupt-controller;
113 };
114
115 pioD: gpio@fffff800 {
116 compatible = "atmel,at91rm9200-gpio";
117 reg = <0xfffff800 0x100>;
118 interrupts = <5 4>;
119 #gpio-cells = <2>;
120 gpio-controller;
121 interrupt-controller;
122 };
123
124 pioE: gpio@fffffa00 {
125 compatible = "atmel,at91rm9200-gpio";
126 reg = <0xfffffa00 0x100>;
127 interrupts = <5 4>;
128 #gpio-cells = <2>;
129 gpio-controller;
130 interrupt-controller;
131 };
132
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]133 dbgu: serial@ffffee00 {
134 compatible = "atmel,at91sam9260-usart";
135 reg = <0xffffee00 0x200>;
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]136 interrupts = <1 4>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]137 status = "disabled";
138 };
139
140 usart0: serial@fff8c000 {
141 compatible = "atmel,at91sam9260-usart";
142 reg = <0xfff8c000 0x200>;
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]143 interrupts = <7 4>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]144 atmel,use-dma-rx;
145 atmel,use-dma-tx;
146 status = "disabled";
147 };
148
149 usart1: serial@fff90000 {
150 compatible = "atmel,at91sam9260-usart";
151 reg = <0xfff90000 0x200>;
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]152 interrupts = <8 4>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]153 atmel,use-dma-rx;
154 atmel,use-dma-tx;
155 status = "disabled";
156 };
157
158 usart2: serial@fff94000 {
159 compatible = "atmel,at91sam9260-usart";
160 reg = <0xfff94000 0x200>;
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]161 interrupts = <9 4>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]162 atmel,use-dma-rx;
163 atmel,use-dma-tx;
164 status = "disabled";
165 };
166
167 usart3: serial@fff98000 {
168 compatible = "atmel,at91sam9260-usart";
169 reg = <0xfff98000 0x200>;
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]170 interrupts = <10 4>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]171 atmel,use-dma-rx;
172 atmel,use-dma-tx;
173 status = "disabled";
174 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100[diff] [blame]175
176 macb0: ethernet@fffbc000 {
177 compatible = "cdns,at32ap7000-macb", "cdns,macb";
178 reg = <0xfffbc000 0x100>;
Nicolas Ferree2615012011-11-22 22:26:09 +0100[diff] [blame]179 interrupts = <25 4>;
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100[diff] [blame]180 status = "disabled";
181 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]182 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800[diff] [blame^]183
184 nand0: nand@40000000 {
185 compatible = "atmel,at91rm9200-nand";
186 #address-cells = <1>;
187 #size-cells = <1>;
188 reg = <0x40000000 0x10000000
189 0xffffe200 0x200
190 >;
191 atmel,nand-addr-offset = <21>;
192 atmel,nand-cmd-offset = <22>;
193 gpios = <&pioC 8 0
194 &pioC 14 0
195 0
196 >;
197 status = "disabled";
198 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200[diff] [blame]199 };
200};