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Divy Le Ray4d22de32007-01-18 22:04:14 -05001/*
Divy Le Raya02d44a2008-10-13 18:47:30 -07002 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
Divy Le Ray4d22de32007-01-18 22:04:14 -05003 *
Divy Le Ray1d68e932007-01-30 19:44:35 -08004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
Divy Le Ray4d22de32007-01-18 22:04:14 -05009 *
Divy Le Ray1d68e932007-01-30 19:44:35 -080010 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Divy Le Ray4d22de32007-01-18 22:04:14 -050031 */
Divy Le Ray4d22de32007-01-18 22:04:14 -050032#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090039#include <linux/slab.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040040#include <linux/prefetch.h>
Karen Xiea109a5b2008-12-18 22:56:20 -080041#include <net/arp.h>
Divy Le Ray4d22de32007-01-18 22:04:14 -050042#include "common.h"
43#include "regs.h"
44#include "sge_defs.h"
45#include "t3_cpl.h"
46#include "firmware_exports.h"
Steve Wisee998f242010-01-27 17:03:34 +000047#include "cxgb3_offload.h"
Divy Le Ray4d22de32007-01-18 22:04:14 -050048
49#define USE_GTS 0
50
51#define SGE_RX_SM_BUF_SIZE 1536
Divy Le Raye0994eb2007-02-24 16:44:17 -080052
Divy Le Ray4d22de32007-01-18 22:04:14 -050053#define SGE_RX_COPY_THRES 256
Divy Le Raycf992af2007-05-30 21:10:47 -070054#define SGE_RX_PULL_LEN 128
Divy Le Ray4d22de32007-01-18 22:04:14 -050055
Divy Le Ray5e68b772009-03-26 16:39:29 +000056#define SGE_PG_RSVD SMP_CACHE_BYTES
Divy Le Raye0994eb2007-02-24 16:44:17 -080057/*
Divy Le Raycf992af2007-05-30 21:10:47 -070058 * Page chunk size for FL0 buffers if FL0 is to be populated with page chunks.
59 * It must be a divisor of PAGE_SIZE. If set to 0 FL0 will use sk_buffs
60 * directly.
Divy Le Raye0994eb2007-02-24 16:44:17 -080061 */
Divy Le Raycf992af2007-05-30 21:10:47 -070062#define FL0_PG_CHUNK_SIZE 2048
Divy Le Ray7385ecf2008-05-21 18:56:21 -070063#define FL0_PG_ORDER 0
Divy Le Ray5e68b772009-03-26 16:39:29 +000064#define FL0_PG_ALLOC_SIZE (PAGE_SIZE << FL0_PG_ORDER)
Divy Le Ray7385ecf2008-05-21 18:56:21 -070065#define FL1_PG_CHUNK_SIZE (PAGE_SIZE > 8192 ? 16384 : 8192)
66#define FL1_PG_ORDER (PAGE_SIZE > 8192 ? 0 : 1)
Divy Le Ray5e68b772009-03-26 16:39:29 +000067#define FL1_PG_ALLOC_SIZE (PAGE_SIZE << FL1_PG_ORDER)
Divy Le Raycf992af2007-05-30 21:10:47 -070068
Divy Le Raye0994eb2007-02-24 16:44:17 -080069#define SGE_RX_DROP_THRES 16
Divy Le Ray42c8ea12009-03-12 21:14:04 +000070#define RX_RECLAIM_PERIOD (HZ/4)
Divy Le Ray4d22de32007-01-18 22:04:14 -050071
72/*
Divy Le Ray26b38712009-03-12 21:13:43 +000073 * Max number of Rx buffers we replenish at a time.
74 */
75#define MAX_RX_REFILL 16U
76/*
Divy Le Ray4d22de32007-01-18 22:04:14 -050077 * Period of the Tx buffer reclaim timer. This timer does not need to run
78 * frequently as Tx buffers are usually reclaimed by new Tx packets.
79 */
80#define TX_RECLAIM_PERIOD (HZ / 4)
Divy Le Ray42c8ea12009-03-12 21:14:04 +000081#define TX_RECLAIM_TIMER_CHUNK 64U
82#define TX_RECLAIM_CHUNK 16U
Divy Le Ray4d22de32007-01-18 22:04:14 -050083
84/* WR size in bytes */
85#define WR_LEN (WR_FLITS * 8)
86
87/*
88 * Types of Tx queues in each queue set. Order here matters, do not change.
89 */
90enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
91
92/* Values for sge_txq.flags */
93enum {
94 TXQ_RUNNING = 1 << 0, /* fetch engine is running */
95 TXQ_LAST_PKT_DB = 1 << 1, /* last packet rang the doorbell */
96};
97
98struct tx_desc {
Al Virofb8e4442007-08-23 03:04:12 -040099 __be64 flit[TX_DESC_FLITS];
Divy Le Ray4d22de32007-01-18 22:04:14 -0500100};
101
102struct rx_desc {
103 __be32 addr_lo;
104 __be32 len_gen;
105 __be32 gen2;
106 __be32 addr_hi;
107};
108
109struct tx_sw_desc { /* SW state per Tx descriptor */
110 struct sk_buff *skb;
Divy Le Ray23561c92007-11-16 11:22:05 -0800111 u8 eop; /* set if last descriptor for packet */
112 u8 addr_idx; /* buffer index of first SGL entry in descriptor */
113 u8 fragidx; /* first page fragment associated with descriptor */
114 s8 sflit; /* start flit of first SGL entry in descriptor */
Divy Le Ray4d22de32007-01-18 22:04:14 -0500115};
116
Divy Le Raycf992af2007-05-30 21:10:47 -0700117struct rx_sw_desc { /* SW state per Rx descriptor */
Divy Le Raye0994eb2007-02-24 16:44:17 -0800118 union {
119 struct sk_buff *skb;
Divy Le Raycf992af2007-05-30 21:10:47 -0700120 struct fl_pg_chunk pg_chunk;
121 };
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000122 DEFINE_DMA_UNMAP_ADDR(dma_addr);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500123};
124
125struct rsp_desc { /* response queue descriptor */
126 struct rss_header rss_hdr;
127 __be32 flags;
128 __be32 len_cq;
129 u8 imm_data[47];
130 u8 intr_gen;
131};
132
Divy Le Ray4d22de32007-01-18 22:04:14 -0500133/*
Divy Le Ray99d7cf32007-02-24 16:44:06 -0800134 * Holds unmapping information for Tx packets that need deferred unmapping.
135 * This structure lives at skb->head and must be allocated by callers.
136 */
137struct deferred_unmap_info {
138 struct pci_dev *pdev;
139 dma_addr_t addr[MAX_SKB_FRAGS + 1];
140};
141
142/*
Divy Le Ray4d22de32007-01-18 22:04:14 -0500143 * Maps a number of flits to the number of Tx descriptors that can hold them.
144 * The formula is
145 *
146 * desc = 1 + (flits - 2) / (WR_FLITS - 1).
147 *
148 * HW allows up to 4 descriptors to be combined into a WR.
149 */
150static u8 flit_desc_map[] = {
151 0,
152#if SGE_NUM_GENBITS == 1
153 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
154 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
155 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
156 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
157#elif SGE_NUM_GENBITS == 2
158 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
159 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
160 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
161 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
162#else
163# error "SGE_NUM_GENBITS must be 1 or 2"
164#endif
165};
166
167static inline struct sge_qset *fl_to_qset(const struct sge_fl *q, int qidx)
168{
169 return container_of(q, struct sge_qset, fl[qidx]);
170}
171
172static inline struct sge_qset *rspq_to_qset(const struct sge_rspq *q)
173{
174 return container_of(q, struct sge_qset, rspq);
175}
176
177static inline struct sge_qset *txq_to_qset(const struct sge_txq *q, int qidx)
178{
179 return container_of(q, struct sge_qset, txq[qidx]);
180}
181
182/**
183 * refill_rspq - replenish an SGE response queue
184 * @adapter: the adapter
185 * @q: the response queue to replenish
186 * @credits: how many new responses to make available
187 *
188 * Replenishes a response queue by making the supplied number of responses
189 * available to HW.
190 */
191static inline void refill_rspq(struct adapter *adapter,
192 const struct sge_rspq *q, unsigned int credits)
193{
Divy Le Rayafefce62007-11-16 11:22:21 -0800194 rmb();
Divy Le Ray4d22de32007-01-18 22:04:14 -0500195 t3_write_reg(adapter, A_SG_RSPQ_CREDIT_RETURN,
196 V_RSPQ(q->cntxt_id) | V_CREDITS(credits));
197}
198
199/**
200 * need_skb_unmap - does the platform need unmapping of sk_buffs?
201 *
Stefan Weil947af292010-01-07 00:03:52 +0100202 * Returns true if the platform needs sk_buff unmapping. The compiler
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300203 * optimizes away unnecessary code if this returns true.
Divy Le Ray4d22de32007-01-18 22:04:14 -0500204 */
205static inline int need_skb_unmap(void)
206{
FUJITA Tomonori122e28e2010-07-07 23:52:38 +0000207#ifdef CONFIG_NEED_DMA_MAP_STATE
208 return 1;
209#else
210 return 0;
211#endif
Divy Le Ray4d22de32007-01-18 22:04:14 -0500212}
213
214/**
215 * unmap_skb - unmap a packet main body and its page fragments
216 * @skb: the packet
217 * @q: the Tx queue containing Tx descriptors for the packet
218 * @cidx: index of Tx descriptor
219 * @pdev: the PCI device
220 *
221 * Unmap the main body of an sk_buff and its page fragments, if any.
222 * Because of the fairly complicated structure of our SGLs and the desire
Divy Le Ray23561c92007-11-16 11:22:05 -0800223 * to conserve space for metadata, the information necessary to unmap an
224 * sk_buff is spread across the sk_buff itself (buffer lengths), the HW Tx
225 * descriptors (the physical addresses of the various data buffers), and
226 * the SW descriptor state (assorted indices). The send functions
227 * initialize the indices for the first packet descriptor so we can unmap
228 * the buffers held in the first Tx descriptor here, and we have enough
229 * information at this point to set the state for the next Tx descriptor.
230 *
231 * Note that it is possible to clean up the first descriptor of a packet
232 * before the send routines have written the next descriptors, but this
233 * race does not cause any problem. We just end up writing the unmapping
234 * info for the descriptor first.
Divy Le Ray4d22de32007-01-18 22:04:14 -0500235 */
236static inline void unmap_skb(struct sk_buff *skb, struct sge_txq *q,
237 unsigned int cidx, struct pci_dev *pdev)
238{
239 const struct sg_ent *sgp;
Divy Le Ray23561c92007-11-16 11:22:05 -0800240 struct tx_sw_desc *d = &q->sdesc[cidx];
241 int nfrags, frag_idx, curflit, j = d->addr_idx;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500242
Divy Le Ray23561c92007-11-16 11:22:05 -0800243 sgp = (struct sg_ent *)&q->desc[cidx].flit[d->sflit];
244 frag_idx = d->fragidx;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500245
Divy Le Ray23561c92007-11-16 11:22:05 -0800246 if (frag_idx == 0 && skb_headlen(skb)) {
247 pci_unmap_single(pdev, be64_to_cpu(sgp->addr[0]),
248 skb_headlen(skb), PCI_DMA_TODEVICE);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500249 j = 1;
250 }
251
Divy Le Ray23561c92007-11-16 11:22:05 -0800252 curflit = d->sflit + 1 + j;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500253 nfrags = skb_shinfo(skb)->nr_frags;
254
255 while (frag_idx < nfrags && curflit < WR_FLITS) {
256 pci_unmap_page(pdev, be64_to_cpu(sgp->addr[j]),
257 skb_shinfo(skb)->frags[frag_idx].size,
258 PCI_DMA_TODEVICE);
259 j ^= 1;
260 if (j == 0) {
261 sgp++;
262 curflit++;
263 }
264 curflit++;
265 frag_idx++;
266 }
267
Divy Le Ray23561c92007-11-16 11:22:05 -0800268 if (frag_idx < nfrags) { /* SGL continues into next Tx descriptor */
269 d = cidx + 1 == q->size ? q->sdesc : d + 1;
270 d->fragidx = frag_idx;
271 d->addr_idx = j;
272 d->sflit = curflit - WR_FLITS - j; /* sflit can be -1 */
Divy Le Ray4d22de32007-01-18 22:04:14 -0500273 }
274}
275
276/**
277 * free_tx_desc - reclaims Tx descriptors and their buffers
278 * @adapter: the adapter
279 * @q: the Tx queue to reclaim descriptors from
280 * @n: the number of descriptors to reclaim
281 *
282 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
283 * Tx buffers. Called with the Tx queue lock held.
284 */
285static void free_tx_desc(struct adapter *adapter, struct sge_txq *q,
286 unsigned int n)
287{
288 struct tx_sw_desc *d;
289 struct pci_dev *pdev = adapter->pdev;
290 unsigned int cidx = q->cidx;
291
Divy Le Ray99d7cf32007-02-24 16:44:06 -0800292 const int need_unmap = need_skb_unmap() &&
293 q->cntxt_id >= FW_TUNNEL_SGEEC_START;
294
Divy Le Ray4d22de32007-01-18 22:04:14 -0500295 d = &q->sdesc[cidx];
296 while (n--) {
297 if (d->skb) { /* an SGL is present */
Divy Le Ray99d7cf32007-02-24 16:44:06 -0800298 if (need_unmap)
Divy Le Ray4d22de32007-01-18 22:04:14 -0500299 unmap_skb(d->skb, q, cidx, pdev);
Krishna Kumarb1424ed2010-10-27 19:10:31 +0000300 if (d->eop) {
Divy Le Ray4d22de32007-01-18 22:04:14 -0500301 kfree_skb(d->skb);
Krishna Kumarb1424ed2010-10-27 19:10:31 +0000302 d->skb = NULL;
303 }
Divy Le Ray4d22de32007-01-18 22:04:14 -0500304 }
305 ++d;
306 if (++cidx == q->size) {
307 cidx = 0;
308 d = q->sdesc;
309 }
310 }
311 q->cidx = cidx;
312}
313
314/**
315 * reclaim_completed_tx - reclaims completed Tx descriptors
316 * @adapter: the adapter
317 * @q: the Tx queue to reclaim completed descriptors from
Divy Le Ray42c8ea12009-03-12 21:14:04 +0000318 * @chunk: maximum number of descriptors to reclaim
Divy Le Ray4d22de32007-01-18 22:04:14 -0500319 *
320 * Reclaims Tx descriptors that the SGE has indicated it has processed,
321 * and frees the associated buffers if possible. Called with the Tx
322 * queue's lock held.
323 */
Divy Le Ray42c8ea12009-03-12 21:14:04 +0000324static inline unsigned int reclaim_completed_tx(struct adapter *adapter,
325 struct sge_txq *q,
326 unsigned int chunk)
Divy Le Ray4d22de32007-01-18 22:04:14 -0500327{
328 unsigned int reclaim = q->processed - q->cleaned;
329
Divy Le Ray42c8ea12009-03-12 21:14:04 +0000330 reclaim = min(chunk, reclaim);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500331 if (reclaim) {
332 free_tx_desc(adapter, q, reclaim);
333 q->cleaned += reclaim;
334 q->in_use -= reclaim;
335 }
Divy Le Ray42c8ea12009-03-12 21:14:04 +0000336 return q->processed - q->cleaned;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500337}
338
339/**
340 * should_restart_tx - are there enough resources to restart a Tx queue?
341 * @q: the Tx queue
342 *
343 * Checks if there are enough descriptors to restart a suspended Tx queue.
344 */
345static inline int should_restart_tx(const struct sge_txq *q)
346{
347 unsigned int r = q->processed - q->cleaned;
348
349 return q->in_use - r < (q->size >> 1);
350}
351
Divy Le Ray5e68b772009-03-26 16:39:29 +0000352static void clear_rx_desc(struct pci_dev *pdev, const struct sge_fl *q,
353 struct rx_sw_desc *d)
Divy Le Ray9bb2b312009-03-12 21:13:49 +0000354{
Divy Le Ray5e68b772009-03-26 16:39:29 +0000355 if (q->use_pages && d->pg_chunk.page) {
356 (*d->pg_chunk.p_cnt)--;
357 if (!*d->pg_chunk.p_cnt)
358 pci_unmap_page(pdev,
Divy Le Ray10b6d952009-05-28 11:23:02 +0000359 d->pg_chunk.mapping,
Divy Le Ray5e68b772009-03-26 16:39:29 +0000360 q->alloc_size, PCI_DMA_FROMDEVICE);
361
362 put_page(d->pg_chunk.page);
Divy Le Ray9bb2b312009-03-12 21:13:49 +0000363 d->pg_chunk.page = NULL;
364 } else {
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000365 pci_unmap_single(pdev, dma_unmap_addr(d, dma_addr),
Divy Le Ray5e68b772009-03-26 16:39:29 +0000366 q->buf_size, PCI_DMA_FROMDEVICE);
Divy Le Ray9bb2b312009-03-12 21:13:49 +0000367 kfree_skb(d->skb);
368 d->skb = NULL;
369 }
370}
371
Divy Le Ray4d22de32007-01-18 22:04:14 -0500372/**
373 * free_rx_bufs - free the Rx buffers on an SGE free list
374 * @pdev: the PCI device associated with the adapter
375 * @rxq: the SGE free list to clean up
376 *
377 * Release the buffers on an SGE free-buffer Rx queue. HW fetching from
378 * this queue should be stopped before calling this function.
379 */
380static void free_rx_bufs(struct pci_dev *pdev, struct sge_fl *q)
381{
382 unsigned int cidx = q->cidx;
383
384 while (q->credits--) {
385 struct rx_sw_desc *d = &q->sdesc[cidx];
386
Divy Le Ray5e68b772009-03-26 16:39:29 +0000387
388 clear_rx_desc(pdev, q, d);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500389 if (++cidx == q->size)
390 cidx = 0;
391 }
Divy Le Raye0994eb2007-02-24 16:44:17 -0800392
Divy Le Raycf992af2007-05-30 21:10:47 -0700393 if (q->pg_chunk.page) {
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700394 __free_pages(q->pg_chunk.page, q->order);
Divy Le Raycf992af2007-05-30 21:10:47 -0700395 q->pg_chunk.page = NULL;
396 }
Divy Le Ray4d22de32007-01-18 22:04:14 -0500397}
398
399/**
400 * add_one_rx_buf - add a packet buffer to a free-buffer list
Divy Le Raycf992af2007-05-30 21:10:47 -0700401 * @va: buffer start VA
Divy Le Ray4d22de32007-01-18 22:04:14 -0500402 * @len: the buffer length
403 * @d: the HW Rx descriptor to write
404 * @sd: the SW Rx descriptor to write
405 * @gen: the generation bit value
406 * @pdev: the PCI device associated with the adapter
407 *
408 * Add a buffer of the given length to the supplied HW and SW Rx
409 * descriptors.
410 */
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700411static inline int add_one_rx_buf(void *va, unsigned int len,
412 struct rx_desc *d, struct rx_sw_desc *sd,
413 unsigned int gen, struct pci_dev *pdev)
Divy Le Ray4d22de32007-01-18 22:04:14 -0500414{
415 dma_addr_t mapping;
416
Divy Le Raye0994eb2007-02-24 16:44:17 -0800417 mapping = pci_map_single(pdev, va, len, PCI_DMA_FROMDEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700418 if (unlikely(pci_dma_mapping_error(pdev, mapping)))
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700419 return -ENOMEM;
420
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000421 dma_unmap_addr_set(sd, dma_addr, mapping);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500422
423 d->addr_lo = cpu_to_be32(mapping);
424 d->addr_hi = cpu_to_be32((u64) mapping >> 32);
425 wmb();
426 d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
427 d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700428 return 0;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500429}
430
Divy Le Ray5e68b772009-03-26 16:39:29 +0000431static inline int add_one_rx_chunk(dma_addr_t mapping, struct rx_desc *d,
432 unsigned int gen)
433{
434 d->addr_lo = cpu_to_be32(mapping);
435 d->addr_hi = cpu_to_be32((u64) mapping >> 32);
436 wmb();
437 d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
438 d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
439 return 0;
440}
441
442static int alloc_pg_chunk(struct adapter *adapter, struct sge_fl *q,
443 struct rx_sw_desc *sd, gfp_t gfp,
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700444 unsigned int order)
Divy Le Raycf992af2007-05-30 21:10:47 -0700445{
446 if (!q->pg_chunk.page) {
Divy Le Ray5e68b772009-03-26 16:39:29 +0000447 dma_addr_t mapping;
448
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700449 q->pg_chunk.page = alloc_pages(gfp, order);
Divy Le Raycf992af2007-05-30 21:10:47 -0700450 if (unlikely(!q->pg_chunk.page))
451 return -ENOMEM;
452 q->pg_chunk.va = page_address(q->pg_chunk.page);
Divy Le Ray5e68b772009-03-26 16:39:29 +0000453 q->pg_chunk.p_cnt = q->pg_chunk.va + (PAGE_SIZE << order) -
454 SGE_PG_RSVD;
Divy Le Raycf992af2007-05-30 21:10:47 -0700455 q->pg_chunk.offset = 0;
Divy Le Ray5e68b772009-03-26 16:39:29 +0000456 mapping = pci_map_page(adapter->pdev, q->pg_chunk.page,
457 0, q->alloc_size, PCI_DMA_FROMDEVICE);
Divy Le Ray10b6d952009-05-28 11:23:02 +0000458 q->pg_chunk.mapping = mapping;
Divy Le Raycf992af2007-05-30 21:10:47 -0700459 }
460 sd->pg_chunk = q->pg_chunk;
461
Divy Le Ray5e68b772009-03-26 16:39:29 +0000462 prefetch(sd->pg_chunk.p_cnt);
463
Divy Le Raycf992af2007-05-30 21:10:47 -0700464 q->pg_chunk.offset += q->buf_size;
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700465 if (q->pg_chunk.offset == (PAGE_SIZE << order))
Divy Le Raycf992af2007-05-30 21:10:47 -0700466 q->pg_chunk.page = NULL;
467 else {
468 q->pg_chunk.va += q->buf_size;
469 get_page(q->pg_chunk.page);
470 }
Divy Le Ray5e68b772009-03-26 16:39:29 +0000471
472 if (sd->pg_chunk.offset == 0)
473 *sd->pg_chunk.p_cnt = 1;
474 else
475 *sd->pg_chunk.p_cnt += 1;
476
Divy Le Raycf992af2007-05-30 21:10:47 -0700477 return 0;
478}
479
Divy Le Ray26b38712009-03-12 21:13:43 +0000480static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
481{
482 if (q->pend_cred >= q->credits / 4) {
483 q->pend_cred = 0;
Divy Le Ray2e026442010-02-01 10:29:29 +0000484 wmb();
Divy Le Ray26b38712009-03-12 21:13:43 +0000485 t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id));
486 }
487}
488
Divy Le Ray4d22de32007-01-18 22:04:14 -0500489/**
490 * refill_fl - refill an SGE free-buffer list
491 * @adapter: the adapter
492 * @q: the free-list to refill
493 * @n: the number of new buffers to allocate
494 * @gfp: the gfp flags for allocating new buffers
495 *
496 * (Re)populate an SGE free-buffer list with up to @n new packet buffers,
497 * allocated with the supplied gfp flags. The caller must assure that
498 * @n does not exceed the queue's capacity.
499 */
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700500static int refill_fl(struct adapter *adap, struct sge_fl *q, int n, gfp_t gfp)
Divy Le Ray4d22de32007-01-18 22:04:14 -0500501{
502 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
503 struct rx_desc *d = &q->desc[q->pidx];
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700504 unsigned int count = 0;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500505
506 while (n--) {
Divy Le Ray5e68b772009-03-26 16:39:29 +0000507 dma_addr_t mapping;
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700508 int err;
509
Divy Le Raycf992af2007-05-30 21:10:47 -0700510 if (q->use_pages) {
Divy Le Ray5e68b772009-03-26 16:39:29 +0000511 if (unlikely(alloc_pg_chunk(adap, q, sd, gfp,
512 q->order))) {
Divy Le Raycf992af2007-05-30 21:10:47 -0700513nomem: q->alloc_failed++;
Divy Le Raye0994eb2007-02-24 16:44:17 -0800514 break;
515 }
Divy Le Ray10b6d952009-05-28 11:23:02 +0000516 mapping = sd->pg_chunk.mapping + sd->pg_chunk.offset;
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000517 dma_unmap_addr_set(sd, dma_addr, mapping);
Divy Le Raye0994eb2007-02-24 16:44:17 -0800518
Divy Le Ray5e68b772009-03-26 16:39:29 +0000519 add_one_rx_chunk(mapping, d, q->gen);
520 pci_dma_sync_single_for_device(adap->pdev, mapping,
521 q->buf_size - SGE_PG_RSVD,
522 PCI_DMA_FROMDEVICE);
523 } else {
524 void *buf_start;
525
526 struct sk_buff *skb = alloc_skb(q->buf_size, gfp);
Divy Le Raycf992af2007-05-30 21:10:47 -0700527 if (!skb)
528 goto nomem;
Divy Le Raye0994eb2007-02-24 16:44:17 -0800529
Divy Le Raycf992af2007-05-30 21:10:47 -0700530 sd->skb = skb;
531 buf_start = skb->data;
Divy Le Ray5e68b772009-03-26 16:39:29 +0000532 err = add_one_rx_buf(buf_start, q->buf_size, d, sd,
533 q->gen, adap->pdev);
534 if (unlikely(err)) {
535 clear_rx_desc(adap->pdev, q, sd);
536 break;
537 }
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700538 }
539
Divy Le Ray4d22de32007-01-18 22:04:14 -0500540 d++;
541 sd++;
542 if (++q->pidx == q->size) {
543 q->pidx = 0;
544 q->gen ^= 1;
545 sd = q->sdesc;
546 d = q->desc;
547 }
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700548 count++;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500549 }
Divy Le Ray26b38712009-03-12 21:13:43 +0000550
551 q->credits += count;
552 q->pend_cred += count;
553 ring_fl_db(adap, q);
Divy Le Rayb1fb1f22008-05-21 18:56:16 -0700554
555 return count;
Divy Le Ray4d22de32007-01-18 22:04:14 -0500556}
557
558static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
559{
Divy Le Ray26b38712009-03-12 21:13:43 +0000560 refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits),
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700561 GFP_ATOMIC | __GFP_COMP);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500562}
563
564/**
565 * recycle_rx_buf - recycle a receive buffer
566 * @adapter: the adapter
567 * @q: the SGE free list
568 * @idx: index of buffer to recycle
569 *
570 * Recycles the specified buffer on the given free list by adding it at
571 * the next available slot on the list.
572 */
573static void recycle_rx_buf(struct adapter *adap, struct sge_fl *q,
574 unsigned int idx)
575{
576 struct rx_desc *from = &q->desc[idx];
577 struct rx_desc *to = &q->desc[q->pidx];
578
Divy Le Raycf992af2007-05-30 21:10:47 -0700579 q->sdesc[q->pidx] = q->sdesc[idx];
Divy Le Ray4d22de32007-01-18 22:04:14 -0500580 to->addr_lo = from->addr_lo; /* already big endian */
581 to->addr_hi = from->addr_hi; /* likewise */
582 wmb();
583 to->len_gen = cpu_to_be32(V_FLD_GEN1(q->gen));
584 to->gen2 = cpu_to_be32(V_FLD_GEN2(q->gen));
Divy Le Ray4d22de32007-01-18 22:04:14 -0500585
586 if (++q->pidx == q->size) {
587 q->pidx = 0;
588 q->gen ^= 1;
589 }
Divy Le Ray26b38712009-03-12 21:13:43 +0000590
591 q->credits++;
592 q->pend_cred++;
593 ring_fl_db(adap, q);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500594}
595
596/**
597 * alloc_ring - allocate resources for an SGE descriptor ring
598 * @pdev: the PCI device
599 * @nelem: the number of descriptors
600 * @elem_size: the size of each descriptor
601 * @sw_size: the size of the SW state associated with each ring element
602 * @phys: the physical address of the allocated ring
603 * @metadata: address of the array holding the SW state for the ring
604 *
605 * Allocates resources for an SGE descriptor ring, such as Tx queues,
606 * free buffer lists, or response queues. Each SGE ring requires
607 * space for its HW descriptors plus, optionally, space for the SW state
608 * associated with each HW entry (the metadata). The function returns
609 * three values: the virtual address for the HW ring (the return value
610 * of the function), the physical address of the HW ring, and the address
611 * of the SW ring.
612 */
613static void *alloc_ring(struct pci_dev *pdev, size_t nelem, size_t elem_size,
Divy Le Raye0994eb2007-02-24 16:44:17 -0800614 size_t sw_size, dma_addr_t * phys, void *metadata)
Divy Le Ray4d22de32007-01-18 22:04:14 -0500615{
616 size_t len = nelem * elem_size;
617 void *s = NULL;
618 void *p = dma_alloc_coherent(&pdev->dev, len, phys, GFP_KERNEL);
619
620 if (!p)
621 return NULL;
Divy Le Ray52565542008-11-26 15:35:59 -0800622 if (sw_size && metadata) {
Divy Le Ray4d22de32007-01-18 22:04:14 -0500623 s = kcalloc(nelem, sw_size, GFP_KERNEL);
624
625 if (!s) {
626 dma_free_coherent(&pdev->dev, len, p, *phys);
627 return NULL;
628 }
Divy Le Ray4d22de32007-01-18 22:04:14 -0500629 *(void **)metadata = s;
Divy Le Ray52565542008-11-26 15:35:59 -0800630 }
Divy Le Ray4d22de32007-01-18 22:04:14 -0500631 memset(p, 0, len);
632 return p;
633}
634
635/**
Divy Le Ray204e2f92008-05-06 19:26:01 -0700636 * t3_reset_qset - reset a sge qset
637 * @q: the queue set
638 *
639 * Reset the qset structure.
640 * the NAPI structure is preserved in the event of
641 * the qset's reincarnation, for example during EEH recovery.
642 */
643static void t3_reset_qset(struct sge_qset *q)
644{
645 if (q->adap &&
646 !(q->adap->flags & NAPI_INIT)) {
647 memset(q, 0, sizeof(*q));
648 return;
649 }
650
651 q->adap = NULL;
652 memset(&q->rspq, 0, sizeof(q->rspq));
653 memset(q->fl, 0, sizeof(struct sge_fl) * SGE_RXQ_PER_SET);
654 memset(q->txq, 0, sizeof(struct sge_txq) * SGE_TXQ_PER_SET);
655 q->txq_stopped = 0;
Divy Le Ray20d3fc12008-10-08 17:36:03 -0700656 q->tx_reclaim_timer.function = NULL; /* for t3_stop_sge_timers() */
Divy Le Ray42c8ea12009-03-12 21:14:04 +0000657 q->rx_reclaim_timer.function = NULL;
Herbert Xu76620aa2009-04-16 02:02:07 -0700658 q->nomem = 0;
659 napi_free_frags(&q->napi);
Divy Le Ray204e2f92008-05-06 19:26:01 -0700660}
661
662
663/**
Divy Le Ray4d22de32007-01-18 22:04:14 -0500664 * free_qset - free the resources of an SGE queue set
665 * @adapter: the adapter owning the queue set
666 * @q: the queue set
667 *
668 * Release the HW and SW resources associated with an SGE queue set, such
669 * as HW contexts, packet buffers, and descriptor rings. Traffic to the
670 * queue set must be quiesced prior to calling this.
671 */
Stephen Hemminger9265fab2007-10-08 16:22:29 -0700672static void t3_free_qset(struct adapter *adapter, struct sge_qset *q)
Divy Le Ray4d22de32007-01-18 22:04:14 -0500673{
674 int i;
675 struct pci_dev *pdev = adapter->pdev;
676
Divy Le Ray4d22de32007-01-18 22:04:14 -0500677 for (i = 0; i < SGE_RXQ_PER_SET; ++i)
678 if (q->fl[i].desc) {
Roland Dreierb1186de2008-03-20 13:30:48 -0700679 spin_lock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500680 t3_sge_disable_fl(adapter, q->fl[i].cntxt_id);
Roland Dreierb1186de2008-03-20 13:30:48 -0700681 spin_unlock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500682 free_rx_bufs(pdev, &q->fl[i]);
683 kfree(q->fl[i].sdesc);
684 dma_free_coherent(&pdev->dev,
685 q->fl[i].size *
686 sizeof(struct rx_desc), q->fl[i].desc,
687 q->fl[i].phys_addr);
688 }
689
690 for (i = 0; i < SGE_TXQ_PER_SET; ++i)
691 if (q->txq[i].desc) {
Roland Dreierb1186de2008-03-20 13:30:48 -0700692 spin_lock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500693 t3_sge_enable_ecntxt(adapter, q->txq[i].cntxt_id, 0);
Roland Dreierb1186de2008-03-20 13:30:48 -0700694 spin_unlock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500695 if (q->txq[i].sdesc) {
696 free_tx_desc(adapter, &q->txq[i],
697 q->txq[i].in_use);
698 kfree(q->txq[i].sdesc);
699 }
700 dma_free_coherent(&pdev->dev,
701 q->txq[i].size *
702 sizeof(struct tx_desc),
703 q->txq[i].desc, q->txq[i].phys_addr);
704 __skb_queue_purge(&q->txq[i].sendq);
705 }
706
707 if (q->rspq.desc) {
Roland Dreierb1186de2008-03-20 13:30:48 -0700708 spin_lock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500709 t3_sge_disable_rspcntxt(adapter, q->rspq.cntxt_id);
Roland Dreierb1186de2008-03-20 13:30:48 -0700710 spin_unlock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500711 dma_free_coherent(&pdev->dev,
712 q->rspq.size * sizeof(struct rsp_desc),
713 q->rspq.desc, q->rspq.phys_addr);
714 }
715
Divy Le Ray204e2f92008-05-06 19:26:01 -0700716 t3_reset_qset(q);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500717}
718
719/**
720 * init_qset_cntxt - initialize an SGE queue set context info
721 * @qs: the queue set
722 * @id: the queue set id
723 *
724 * Initializes the TIDs and context ids for the queues of a queue set.
725 */
726static void init_qset_cntxt(struct sge_qset *qs, unsigned int id)
727{
728 qs->rspq.cntxt_id = id;
729 qs->fl[0].cntxt_id = 2 * id;
730 qs->fl[1].cntxt_id = 2 * id + 1;
731 qs->txq[TXQ_ETH].cntxt_id = FW_TUNNEL_SGEEC_START + id;
732 qs->txq[TXQ_ETH].token = FW_TUNNEL_TID_START + id;
733 qs->txq[TXQ_OFLD].cntxt_id = FW_OFLD_SGEEC_START + id;
734 qs->txq[TXQ_CTRL].cntxt_id = FW_CTRL_SGEEC_START + id;
735 qs->txq[TXQ_CTRL].token = FW_CTRL_TID_START + id;
736}
737
738/**
739 * sgl_len - calculates the size of an SGL of the given capacity
740 * @n: the number of SGL entries
741 *
742 * Calculates the number of flits needed for a scatter/gather list that
743 * can hold the given number of entries.
744 */
745static inline unsigned int sgl_len(unsigned int n)
746{
747 /* alternatively: 3 * (n / 2) + 2 * (n & 1) */
748 return (3 * n) / 2 + (n & 1);
749}
750
751/**
752 * flits_to_desc - returns the num of Tx descriptors for the given flits
753 * @n: the number of flits
754 *
755 * Calculates the number of Tx descriptors needed for the supplied number
756 * of flits.
757 */
758static inline unsigned int flits_to_desc(unsigned int n)
759{
760 BUG_ON(n >= ARRAY_SIZE(flit_desc_map));
761 return flit_desc_map[n];
762}
763
764/**
Divy Le Raycf992af2007-05-30 21:10:47 -0700765 * get_packet - return the next ingress packet buffer from a free list
766 * @adap: the adapter that received the packet
767 * @fl: the SGE free list holding the packet
768 * @len: the packet length including any SGE padding
769 * @drop_thres: # of remaining buffers before we start dropping packets
770 *
771 * Get the next packet from a free list and complete setup of the
772 * sk_buff. If the packet is small we make a copy and recycle the
773 * original buffer, otherwise we use the original buffer itself. If a
774 * positive drop threshold is supplied packets are dropped and their
775 * buffers recycled if (a) the number of remaining buffers is under the
776 * threshold and the packet is too big to copy, or (b) the packet should
777 * be copied but there is no memory for the copy.
778 */
779static struct sk_buff *get_packet(struct adapter *adap, struct sge_fl *fl,
780 unsigned int len, unsigned int drop_thres)
781{
782 struct sk_buff *skb = NULL;
783 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
784
785 prefetch(sd->skb->data);
786 fl->credits--;
787
788 if (len <= SGE_RX_COPY_THRES) {
789 skb = alloc_skb(len, GFP_ATOMIC);
790 if (likely(skb != NULL)) {
791 __skb_put(skb, len);
792 pci_dma_sync_single_for_cpu(adap->pdev,
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000793 dma_unmap_addr(sd, dma_addr), len,
Divy Le Raycf992af2007-05-30 21:10:47 -0700794 PCI_DMA_FROMDEVICE);
795 memcpy(skb->data, sd->skb->data, len);
796 pci_dma_sync_single_for_device(adap->pdev,
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000797 dma_unmap_addr(sd, dma_addr), len,
Divy Le Raycf992af2007-05-30 21:10:47 -0700798 PCI_DMA_FROMDEVICE);
799 } else if (!drop_thres)
800 goto use_orig_buf;
801recycle:
802 recycle_rx_buf(adap, fl, fl->cidx);
803 return skb;
804 }
805
Divy Le Ray26b38712009-03-12 21:13:43 +0000806 if (unlikely(fl->credits < drop_thres) &&
807 refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits - 1),
808 GFP_ATOMIC | __GFP_COMP) == 0)
Divy Le Raycf992af2007-05-30 21:10:47 -0700809 goto recycle;
810
811use_orig_buf:
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000812 pci_unmap_single(adap->pdev, dma_unmap_addr(sd, dma_addr),
Divy Le Raycf992af2007-05-30 21:10:47 -0700813 fl->buf_size, PCI_DMA_FROMDEVICE);
814 skb = sd->skb;
815 skb_put(skb, len);
816 __refill_fl(adap, fl);
817 return skb;
818}
819
820/**
821 * get_packet_pg - return the next ingress packet buffer from a free list
822 * @adap: the adapter that received the packet
823 * @fl: the SGE free list holding the packet
824 * @len: the packet length including any SGE padding
825 * @drop_thres: # of remaining buffers before we start dropping packets
826 *
827 * Get the next packet from a free list populated with page chunks.
828 * If the packet is small we make a copy and recycle the original buffer,
829 * otherwise we attach the original buffer as a page fragment to a fresh
830 * sk_buff. If a positive drop threshold is supplied packets are dropped
831 * and their buffers recycled if (a) the number of remaining buffers is
832 * under the threshold and the packet is too big to copy, or (b) there's
833 * no system memory.
834 *
835 * Note: this function is similar to @get_packet but deals with Rx buffers
836 * that are page chunks rather than sk_buffs.
837 */
838static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl,
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700839 struct sge_rspq *q, unsigned int len,
840 unsigned int drop_thres)
Divy Le Raycf992af2007-05-30 21:10:47 -0700841{
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700842 struct sk_buff *newskb, *skb;
Divy Le Raycf992af2007-05-30 21:10:47 -0700843 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
844
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +0000845 dma_addr_t dma_addr = dma_unmap_addr(sd, dma_addr);
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700846
Divy Le Ray5e68b772009-03-26 16:39:29 +0000847 newskb = skb = q->pg_skb;
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700848 if (!skb && (len <= SGE_RX_COPY_THRES)) {
849 newskb = alloc_skb(len, GFP_ATOMIC);
850 if (likely(newskb != NULL)) {
851 __skb_put(newskb, len);
Divy Le Ray5e68b772009-03-26 16:39:29 +0000852 pci_dma_sync_single_for_cpu(adap->pdev, dma_addr, len,
Divy Le Raycf992af2007-05-30 21:10:47 -0700853 PCI_DMA_FROMDEVICE);
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700854 memcpy(newskb->data, sd->pg_chunk.va, len);
Divy Le Ray5e68b772009-03-26 16:39:29 +0000855 pci_dma_sync_single_for_device(adap->pdev, dma_addr,
856 len,
857 PCI_DMA_FROMDEVICE);
Divy Le Raycf992af2007-05-30 21:10:47 -0700858 } else if (!drop_thres)
859 return NULL;
860recycle:
861 fl->credits--;
862 recycle_rx_buf(adap, fl, fl->cidx);
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700863 q->rx_recycle_buf++;
864 return newskb;
Divy Le Raycf992af2007-05-30 21:10:47 -0700865 }
866
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700867 if (unlikely(q->rx_recycle_buf || (!skb && fl->credits <= drop_thres)))
Divy Le Raycf992af2007-05-30 21:10:47 -0700868 goto recycle;
869
Divy Le Ray5e68b772009-03-26 16:39:29 +0000870 prefetch(sd->pg_chunk.p_cnt);
871
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700872 if (!skb)
Divy Le Rayb47385b2008-05-21 18:56:26 -0700873 newskb = alloc_skb(SGE_RX_PULL_LEN, GFP_ATOMIC);
Divy Le Ray5e68b772009-03-26 16:39:29 +0000874
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700875 if (unlikely(!newskb)) {
Divy Le Raycf992af2007-05-30 21:10:47 -0700876 if (!drop_thres)
877 return NULL;
878 goto recycle;
879 }
880
Divy Le Ray5e68b772009-03-26 16:39:29 +0000881 pci_dma_sync_single_for_cpu(adap->pdev, dma_addr, len,
882 PCI_DMA_FROMDEVICE);
883 (*sd->pg_chunk.p_cnt)--;
Divy Le Ray70e3bb52009-11-17 16:38:28 +0000884 if (!*sd->pg_chunk.p_cnt && sd->pg_chunk.page != fl->pg_chunk.page)
Divy Le Ray5e68b772009-03-26 16:39:29 +0000885 pci_unmap_page(adap->pdev,
Divy Le Ray10b6d952009-05-28 11:23:02 +0000886 sd->pg_chunk.mapping,
Divy Le Ray5e68b772009-03-26 16:39:29 +0000887 fl->alloc_size,
888 PCI_DMA_FROMDEVICE);
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700889 if (!skb) {
890 __skb_put(newskb, SGE_RX_PULL_LEN);
891 memcpy(newskb->data, sd->pg_chunk.va, SGE_RX_PULL_LEN);
892 skb_fill_page_desc(newskb, 0, sd->pg_chunk.page,
893 sd->pg_chunk.offset + SGE_RX_PULL_LEN,
894 len - SGE_RX_PULL_LEN);
895 newskb->len = len;
896 newskb->data_len = len - SGE_RX_PULL_LEN;
Divy Le Ray8f435802009-03-12 21:13:54 +0000897 newskb->truesize += newskb->data_len;
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700898 } else {
899 skb_fill_page_desc(newskb, skb_shinfo(newskb)->nr_frags,
900 sd->pg_chunk.page,
901 sd->pg_chunk.offset, len);
902 newskb->len += len;
903 newskb->data_len += len;
Divy Le Ray8f435802009-03-12 21:13:54 +0000904 newskb->truesize += len;
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700905 }
Divy Le Raycf992af2007-05-30 21:10:47 -0700906
907 fl->credits--;
908 /*
909 * We do not refill FLs here, we let the caller do it to overlap a
910 * prefetch.
911 */
Divy Le Ray7385ecf2008-05-21 18:56:21 -0700912 return newskb;
Divy Le Raycf992af2007-05-30 21:10:47 -0700913}
914
915/**
Divy Le Ray4d22de32007-01-18 22:04:14 -0500916 * get_imm_packet - return the next ingress packet buffer from a response
917 * @resp: the response descriptor containing the packet data
918 *
919 * Return a packet containing the immediate data of the given response.
920 */
921static inline struct sk_buff *get_imm_packet(const struct rsp_desc *resp)
922{
923 struct sk_buff *skb = alloc_skb(IMMED_PKT_SIZE, GFP_ATOMIC);
924
925 if (skb) {
926 __skb_put(skb, IMMED_PKT_SIZE);
Arnaldo Carvalho de Melo27d7ff42007-03-31 11:55:19 -0300927 skb_copy_to_linear_data(skb, resp->imm_data, IMMED_PKT_SIZE);
Divy Le Ray4d22de32007-01-18 22:04:14 -0500928 }
929 return skb;
930}
931
932/**
933 * calc_tx_descs - calculate the number of Tx descriptors for a packet
934 * @skb: the packet
935 *
936 * Returns the number of Tx descriptors needed for the given Ethernet
937 * packet. Ethernet packets require addition of WR and CPL headers.
938 */
939static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
940{
941 unsigned int flits;
942
943 if (skb->len <= WR_LEN - sizeof(struct cpl_tx_pkt))
944 return 1;
945
946 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 2;
947 if (skb_shinfo(skb)->gso_size)
948 flits++;
949 return flits_to_desc(flits);
950}
951
952/**
953 * make_sgl - populate a scatter/gather list for a packet
954 * @skb: the packet
955 * @sgp: the SGL to populate
956 * @start: start address of skb main body data to include in the SGL
957 * @len: length of skb main body data to include in the SGL
958 * @pdev: the PCI device
959 *
960 * Generates a scatter/gather list for the buffers that make up a packet
961 * and returns the SGL size in 8-byte words. The caller must size the SGL
962 * appropriately.
963 */
964static inline unsigned int make_sgl(const struct sk_buff *skb,
965 struct sg_ent *sgp, unsigned char *start,
966 unsigned int len, struct pci_dev *pdev)
967{
968 dma_addr_t mapping;
969 unsigned int i, j = 0, nfrags;
970
971 if (len) {
972 mapping = pci_map_single(pdev, start, len, PCI_DMA_TODEVICE);
973 sgp->len[0] = cpu_to_be32(len);
974 sgp->addr[0] = cpu_to_be64(mapping);
975 j = 1;
976 }
977
978 nfrags = skb_shinfo(skb)->nr_frags;
979 for (i = 0; i < nfrags; i++) {
980 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
981
982 mapping = pci_map_page(pdev, frag->page, frag->page_offset,
983 frag->size, PCI_DMA_TODEVICE);
984 sgp->len[j] = cpu_to_be32(frag->size);
985 sgp->addr[j] = cpu_to_be64(mapping);
986 j ^= 1;
987 if (j == 0)
988 ++sgp;
989 }
990 if (j)
991 sgp->len[j] = 0;
992 return ((nfrags + (len != 0)) * 3) / 2 + j;
993}
994
995/**
996 * check_ring_tx_db - check and potentially ring a Tx queue's doorbell
997 * @adap: the adapter
998 * @q: the Tx queue
999 *
1000 * Ring the doorbel if a Tx queue is asleep. There is a natural race,
1001 * where the HW is going to sleep just after we checked, however,
1002 * then the interrupt handler will detect the outstanding TX packet
1003 * and ring the doorbell for us.
1004 *
1005 * When GTS is disabled we unconditionally ring the doorbell.
1006 */
1007static inline void check_ring_tx_db(struct adapter *adap, struct sge_txq *q)
1008{
1009#if USE_GTS
1010 clear_bit(TXQ_LAST_PKT_DB, &q->flags);
1011 if (test_and_set_bit(TXQ_RUNNING, &q->flags) == 0) {
1012 set_bit(TXQ_LAST_PKT_DB, &q->flags);
1013 t3_write_reg(adap, A_SG_KDOORBELL,
1014 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1015 }
1016#else
1017 wmb(); /* write descriptors before telling HW */
1018 t3_write_reg(adap, A_SG_KDOORBELL,
1019 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1020#endif
1021}
1022
1023static inline void wr_gen2(struct tx_desc *d, unsigned int gen)
1024{
1025#if SGE_NUM_GENBITS == 2
1026 d->flit[TX_DESC_FLITS - 1] = cpu_to_be64(gen);
1027#endif
1028}
1029
1030/**
1031 * write_wr_hdr_sgl - write a WR header and, optionally, SGL
1032 * @ndesc: number of Tx descriptors spanned by the SGL
1033 * @skb: the packet corresponding to the WR
1034 * @d: first Tx descriptor to be written
1035 * @pidx: index of above descriptors
1036 * @q: the SGE Tx queue
1037 * @sgl: the SGL
1038 * @flits: number of flits to the start of the SGL in the first descriptor
1039 * @sgl_flits: the SGL size in flits
1040 * @gen: the Tx descriptor generation
1041 * @wr_hi: top 32 bits of WR header based on WR type (big endian)
1042 * @wr_lo: low 32 bits of WR header based on WR type (big endian)
1043 *
1044 * Write a work request header and an associated SGL. If the SGL is
1045 * small enough to fit into one Tx descriptor it has already been written
1046 * and we just need to write the WR header. Otherwise we distribute the
1047 * SGL across the number of descriptors it spans.
1048 */
1049static void write_wr_hdr_sgl(unsigned int ndesc, struct sk_buff *skb,
1050 struct tx_desc *d, unsigned int pidx,
1051 const struct sge_txq *q,
1052 const struct sg_ent *sgl,
1053 unsigned int flits, unsigned int sgl_flits,
Al Virofb8e4442007-08-23 03:04:12 -04001054 unsigned int gen, __be32 wr_hi,
1055 __be32 wr_lo)
Divy Le Ray4d22de32007-01-18 22:04:14 -05001056{
1057 struct work_request_hdr *wrp = (struct work_request_hdr *)d;
1058 struct tx_sw_desc *sd = &q->sdesc[pidx];
1059
1060 sd->skb = skb;
1061 if (need_skb_unmap()) {
Divy Le Ray23561c92007-11-16 11:22:05 -08001062 sd->fragidx = 0;
1063 sd->addr_idx = 0;
1064 sd->sflit = flits;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001065 }
1066
1067 if (likely(ndesc == 1)) {
Divy Le Ray23561c92007-11-16 11:22:05 -08001068 sd->eop = 1;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001069 wrp->wr_hi = htonl(F_WR_SOP | F_WR_EOP | V_WR_DATATYPE(1) |
1070 V_WR_SGLSFLT(flits)) | wr_hi;
1071 wmb();
1072 wrp->wr_lo = htonl(V_WR_LEN(flits + sgl_flits) |
1073 V_WR_GEN(gen)) | wr_lo;
1074 wr_gen2(d, gen);
1075 } else {
1076 unsigned int ogen = gen;
1077 const u64 *fp = (const u64 *)sgl;
1078 struct work_request_hdr *wp = wrp;
1079
1080 wrp->wr_hi = htonl(F_WR_SOP | V_WR_DATATYPE(1) |
1081 V_WR_SGLSFLT(flits)) | wr_hi;
1082
1083 while (sgl_flits) {
1084 unsigned int avail = WR_FLITS - flits;
1085
1086 if (avail > sgl_flits)
1087 avail = sgl_flits;
1088 memcpy(&d->flit[flits], fp, avail * sizeof(*fp));
1089 sgl_flits -= avail;
1090 ndesc--;
1091 if (!sgl_flits)
1092 break;
1093
1094 fp += avail;
1095 d++;
Divy Le Ray23561c92007-11-16 11:22:05 -08001096 sd->eop = 0;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001097 sd++;
1098 if (++pidx == q->size) {
1099 pidx = 0;
1100 gen ^= 1;
1101 d = q->desc;
1102 sd = q->sdesc;
1103 }
1104
1105 sd->skb = skb;
1106 wrp = (struct work_request_hdr *)d;
1107 wrp->wr_hi = htonl(V_WR_DATATYPE(1) |
1108 V_WR_SGLSFLT(1)) | wr_hi;
1109 wrp->wr_lo = htonl(V_WR_LEN(min(WR_FLITS,
1110 sgl_flits + 1)) |
1111 V_WR_GEN(gen)) | wr_lo;
1112 wr_gen2(d, gen);
1113 flits = 1;
1114 }
Divy Le Ray23561c92007-11-16 11:22:05 -08001115 sd->eop = 1;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001116 wrp->wr_hi |= htonl(F_WR_EOP);
1117 wmb();
1118 wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo;
1119 wr_gen2((struct tx_desc *)wp, ogen);
1120 WARN_ON(ndesc != 0);
1121 }
1122}
1123
1124/**
1125 * write_tx_pkt_wr - write a TX_PKT work request
1126 * @adap: the adapter
1127 * @skb: the packet to send
1128 * @pi: the egress interface
1129 * @pidx: index of the first Tx descriptor to write
1130 * @gen: the generation value to use
1131 * @q: the Tx queue
1132 * @ndesc: number of descriptors the packet will occupy
1133 * @compl: the value of the COMPL bit to use
1134 *
1135 * Generate a TX_PKT work request to send the supplied packet.
1136 */
1137static void write_tx_pkt_wr(struct adapter *adap, struct sk_buff *skb,
1138 const struct port_info *pi,
1139 unsigned int pidx, unsigned int gen,
1140 struct sge_txq *q, unsigned int ndesc,
1141 unsigned int compl)
1142{
1143 unsigned int flits, sgl_flits, cntrl, tso_info;
1144 struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
1145 struct tx_desc *d = &q->desc[pidx];
1146 struct cpl_tx_pkt *cpl = (struct cpl_tx_pkt *)d;
1147
Divy Le Ray3fa58c882009-03-26 16:39:14 +00001148 cpl->len = htonl(skb->len);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001149 cntrl = V_TXPKT_INTF(pi->port_id);
1150
Jesse Grosseab6d182010-10-20 13:56:03 +00001151 if (vlan_tx_tag_present(skb))
Divy Le Ray4d22de32007-01-18 22:04:14 -05001152 cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(vlan_tx_tag_get(skb));
1153
1154 tso_info = V_LSO_MSS(skb_shinfo(skb)->gso_size);
1155 if (tso_info) {
1156 int eth_type;
1157 struct cpl_tx_pkt_lso *hdr = (struct cpl_tx_pkt_lso *)cpl;
1158
1159 d->flit[2] = 0;
1160 cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT_LSO);
1161 hdr->cntrl = htonl(cntrl);
Arnaldo Carvalho de Melobbe735e2007-03-10 22:16:10 -03001162 eth_type = skb_network_offset(skb) == ETH_HLEN ?
Divy Le Ray4d22de32007-01-18 22:04:14 -05001163 CPL_ETH_II : CPL_ETH_II_VLAN;
1164 tso_info |= V_LSO_ETH_TYPE(eth_type) |
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07001165 V_LSO_IPHDR_WORDS(ip_hdr(skb)->ihl) |
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07001166 V_LSO_TCPHDR_WORDS(tcp_hdr(skb)->doff);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001167 hdr->lso_info = htonl(tso_info);
1168 flits = 3;
1169 } else {
1170 cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT);
1171 cntrl |= F_TXPKT_IPCSUM_DIS; /* SW calculates IP csum */
1172 cntrl |= V_TXPKT_L4CSUM_DIS(skb->ip_summed != CHECKSUM_PARTIAL);
1173 cpl->cntrl = htonl(cntrl);
1174
1175 if (skb->len <= WR_LEN - sizeof(*cpl)) {
1176 q->sdesc[pidx].skb = NULL;
1177 if (!skb->data_len)
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03001178 skb_copy_from_linear_data(skb, &d->flit[2],
1179 skb->len);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001180 else
1181 skb_copy_bits(skb, 0, &d->flit[2], skb->len);
1182
1183 flits = (skb->len + 7) / 8 + 2;
1184 cpl->wr.wr_hi = htonl(V_WR_BCNTLFLT(skb->len & 7) |
1185 V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT)
1186 | F_WR_SOP | F_WR_EOP | compl);
1187 wmb();
1188 cpl->wr.wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(gen) |
1189 V_WR_TID(q->token));
1190 wr_gen2(d, gen);
1191 kfree_skb(skb);
1192 return;
1193 }
1194
1195 flits = 2;
1196 }
1197
1198 sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
1199 sgl_flits = make_sgl(skb, sgp, skb->data, skb_headlen(skb), adap->pdev);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001200
1201 write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits, gen,
1202 htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | compl),
1203 htonl(V_WR_TID(q->token)));
1204}
1205
Divy Le Ray82ad3322008-12-16 01:09:39 -08001206static inline void t3_stop_tx_queue(struct netdev_queue *txq,
1207 struct sge_qset *qs, struct sge_txq *q)
Krishna Kumara8cc21f2008-01-30 12:30:16 +05301208{
Divy Le Ray82ad3322008-12-16 01:09:39 -08001209 netif_tx_stop_queue(txq);
Krishna Kumara8cc21f2008-01-30 12:30:16 +05301210 set_bit(TXQ_ETH, &qs->txq_stopped);
1211 q->stops++;
1212}
1213
Divy Le Ray4d22de32007-01-18 22:04:14 -05001214/**
1215 * eth_xmit - add a packet to the Ethernet Tx queue
1216 * @skb: the packet
1217 * @dev: the egress net device
1218 *
1219 * Add a packet to an SGE Tx queue. Runs with softirqs disabled.
1220 */
Stephen Hemminger613573252009-08-31 19:50:58 +00001221netdev_tx_t t3_eth_xmit(struct sk_buff *skb, struct net_device *dev)
Divy Le Ray4d22de32007-01-18 22:04:14 -05001222{
Divy Le Ray82ad3322008-12-16 01:09:39 -08001223 int qidx;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001224 unsigned int ndesc, pidx, credits, gen, compl;
1225 const struct port_info *pi = netdev_priv(dev);
Divy Le Ray5fbf8162007-08-29 19:15:47 -07001226 struct adapter *adap = pi->adapter;
Divy Le Ray82ad3322008-12-16 01:09:39 -08001227 struct netdev_queue *txq;
1228 struct sge_qset *qs;
1229 struct sge_txq *q;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001230
1231 /*
1232 * The chip min packet length is 9 octets but play safe and reject
1233 * anything shorter than an Ethernet header.
1234 */
1235 if (unlikely(skb->len < ETH_HLEN)) {
1236 dev_kfree_skb(skb);
1237 return NETDEV_TX_OK;
1238 }
1239
Divy Le Ray82ad3322008-12-16 01:09:39 -08001240 qidx = skb_get_queue_mapping(skb);
1241 qs = &pi->qs[qidx];
1242 q = &qs->txq[TXQ_ETH];
1243 txq = netdev_get_tx_queue(dev, qidx);
1244
Divy Le Ray42c8ea12009-03-12 21:14:04 +00001245 reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001246
1247 credits = q->size - q->in_use;
1248 ndesc = calc_tx_descs(skb);
1249
1250 if (unlikely(credits < ndesc)) {
Divy Le Ray82ad3322008-12-16 01:09:39 -08001251 t3_stop_tx_queue(txq, qs, q);
Krishna Kumara8cc21f2008-01-30 12:30:16 +05301252 dev_err(&adap->pdev->dev,
1253 "%s: Tx ring %u full while queue awake!\n",
1254 dev->name, q->cntxt_id & 7);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001255 return NETDEV_TX_BUSY;
1256 }
1257
1258 q->in_use += ndesc;
Divy Le Raycd7e9032008-03-13 00:13:30 -07001259 if (unlikely(credits - ndesc < q->stop_thres)) {
Divy Le Ray82ad3322008-12-16 01:09:39 -08001260 t3_stop_tx_queue(txq, qs, q);
Divy Le Raycd7e9032008-03-13 00:13:30 -07001261
1262 if (should_restart_tx(q) &&
1263 test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
1264 q->restarts++;
Krishna Kumar0d9a40d2009-10-14 19:54:19 +00001265 netif_tx_start_queue(txq);
Divy Le Raycd7e9032008-03-13 00:13:30 -07001266 }
1267 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05001268
1269 gen = q->gen;
1270 q->unacked += ndesc;
1271 compl = (q->unacked & 8) << (S_WR_COMPL - 3);
1272 q->unacked &= 7;
1273 pidx = q->pidx;
1274 q->pidx += ndesc;
1275 if (q->pidx >= q->size) {
1276 q->pidx -= q->size;
1277 q->gen ^= 1;
1278 }
1279
1280 /* update port statistics */
1281 if (skb->ip_summed == CHECKSUM_COMPLETE)
1282 qs->port_stats[SGE_PSTAT_TX_CSUM]++;
1283 if (skb_shinfo(skb)->gso_size)
1284 qs->port_stats[SGE_PSTAT_TSO]++;
Jesse Grosseab6d182010-10-20 13:56:03 +00001285 if (vlan_tx_tag_present(skb))
Divy Le Ray4d22de32007-01-18 22:04:14 -05001286 qs->port_stats[SGE_PSTAT_VLANINS]++;
1287
Divy Le Ray4d22de32007-01-18 22:04:14 -05001288 /*
1289 * We do not use Tx completion interrupts to free DMAd Tx packets.
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001290 * This is good for performance but means that we rely on new Tx
Divy Le Ray4d22de32007-01-18 22:04:14 -05001291 * packets arriving to run the destructors of completed packets,
1292 * which open up space in their sockets' send queues. Sometimes
1293 * we do not get such new packets causing Tx to stall. A single
1294 * UDP transmitter is a good example of this situation. We have
1295 * a clean up timer that periodically reclaims completed packets
1296 * but it doesn't run often enough (nor do we want it to) to prevent
1297 * lengthy stalls. A solution to this problem is to run the
1298 * destructor early, after the packet is queued but before it's DMAd.
1299 * A cons is that we lie to socket memory accounting, but the amount
1300 * of extra memory is reasonable (limited by the number of Tx
1301 * descriptors), the packets do actually get freed quickly by new
1302 * packets almost always, and for protocols like TCP that wait for
1303 * acks to really free up the data the extra memory is even less.
1304 * On the positive side we run the destructors on the sending CPU
1305 * rather than on a potentially different completing CPU, usually a
1306 * good thing. We also run them without holding our Tx queue lock,
1307 * unlike what reclaim_completed_tx() would otherwise do.
1308 *
1309 * Run the destructor before telling the DMA engine about the packet
1310 * to make sure it doesn't complete and get freed prematurely.
1311 */
1312 if (likely(!skb_shared(skb)))
1313 skb_orphan(skb);
1314
1315 write_tx_pkt_wr(adap, skb, pi, pidx, gen, q, ndesc, compl);
1316 check_ring_tx_db(adap, q);
1317 return NETDEV_TX_OK;
1318}
1319
1320/**
1321 * write_imm - write a packet into a Tx descriptor as immediate data
1322 * @d: the Tx descriptor to write
1323 * @skb: the packet
1324 * @len: the length of packet data to write as immediate data
1325 * @gen: the generation bit value to write
1326 *
1327 * Writes a packet as immediate data into a Tx descriptor. The packet
1328 * contains a work request at its beginning. We must write the packet
Divy Le Ray27186dc2007-08-21 20:49:15 -07001329 * carefully so the SGE doesn't read it accidentally before it's written
1330 * in its entirety.
Divy Le Ray4d22de32007-01-18 22:04:14 -05001331 */
1332static inline void write_imm(struct tx_desc *d, struct sk_buff *skb,
1333 unsigned int len, unsigned int gen)
1334{
1335 struct work_request_hdr *from = (struct work_request_hdr *)skb->data;
1336 struct work_request_hdr *to = (struct work_request_hdr *)d;
1337
Divy Le Ray27186dc2007-08-21 20:49:15 -07001338 if (likely(!skb->data_len))
1339 memcpy(&to[1], &from[1], len - sizeof(*from));
1340 else
1341 skb_copy_bits(skb, sizeof(*from), &to[1], len - sizeof(*from));
1342
Divy Le Ray4d22de32007-01-18 22:04:14 -05001343 to->wr_hi = from->wr_hi | htonl(F_WR_SOP | F_WR_EOP |
1344 V_WR_BCNTLFLT(len & 7));
1345 wmb();
1346 to->wr_lo = from->wr_lo | htonl(V_WR_GEN(gen) |
1347 V_WR_LEN((len + 7) / 8));
1348 wr_gen2(d, gen);
1349 kfree_skb(skb);
1350}
1351
1352/**
1353 * check_desc_avail - check descriptor availability on a send queue
1354 * @adap: the adapter
1355 * @q: the send queue
1356 * @skb: the packet needing the descriptors
1357 * @ndesc: the number of Tx descriptors needed
1358 * @qid: the Tx queue number in its queue set (TXQ_OFLD or TXQ_CTRL)
1359 *
1360 * Checks if the requested number of Tx descriptors is available on an
1361 * SGE send queue. If the queue is already suspended or not enough
1362 * descriptors are available the packet is queued for later transmission.
1363 * Must be called with the Tx queue locked.
1364 *
1365 * Returns 0 if enough descriptors are available, 1 if there aren't
1366 * enough descriptors and the packet has been queued, and 2 if the caller
1367 * needs to retry because there weren't enough descriptors at the
1368 * beginning of the call but some freed up in the mean time.
1369 */
1370static inline int check_desc_avail(struct adapter *adap, struct sge_txq *q,
1371 struct sk_buff *skb, unsigned int ndesc,
1372 unsigned int qid)
1373{
1374 if (unlikely(!skb_queue_empty(&q->sendq))) {
1375 addq_exit:__skb_queue_tail(&q->sendq, skb);
1376 return 1;
1377 }
1378 if (unlikely(q->size - q->in_use < ndesc)) {
1379 struct sge_qset *qs = txq_to_qset(q, qid);
1380
1381 set_bit(qid, &qs->txq_stopped);
1382 smp_mb__after_clear_bit();
1383
1384 if (should_restart_tx(q) &&
1385 test_and_clear_bit(qid, &qs->txq_stopped))
1386 return 2;
1387
1388 q->stops++;
1389 goto addq_exit;
1390 }
1391 return 0;
1392}
1393
1394/**
1395 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1396 * @q: the SGE control Tx queue
1397 *
1398 * This is a variant of reclaim_completed_tx() that is used for Tx queues
1399 * that send only immediate data (presently just the control queues) and
1400 * thus do not have any sk_buffs to release.
1401 */
1402static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1403{
1404 unsigned int reclaim = q->processed - q->cleaned;
1405
1406 q->in_use -= reclaim;
1407 q->cleaned += reclaim;
1408}
1409
1410static inline int immediate(const struct sk_buff *skb)
1411{
Divy Le Ray27186dc2007-08-21 20:49:15 -07001412 return skb->len <= WR_LEN;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001413}
1414
1415/**
1416 * ctrl_xmit - send a packet through an SGE control Tx queue
1417 * @adap: the adapter
1418 * @q: the control queue
1419 * @skb: the packet
1420 *
1421 * Send a packet through an SGE control Tx queue. Packets sent through
1422 * a control queue must fit entirely as immediate data in a single Tx
1423 * descriptor and have no page fragments.
1424 */
1425static int ctrl_xmit(struct adapter *adap, struct sge_txq *q,
1426 struct sk_buff *skb)
1427{
1428 int ret;
1429 struct work_request_hdr *wrp = (struct work_request_hdr *)skb->data;
1430
1431 if (unlikely(!immediate(skb))) {
1432 WARN_ON(1);
1433 dev_kfree_skb(skb);
1434 return NET_XMIT_SUCCESS;
1435 }
1436
1437 wrp->wr_hi |= htonl(F_WR_SOP | F_WR_EOP);
1438 wrp->wr_lo = htonl(V_WR_TID(q->token));
1439
1440 spin_lock(&q->lock);
1441 again:reclaim_completed_tx_imm(q);
1442
1443 ret = check_desc_avail(adap, q, skb, 1, TXQ_CTRL);
1444 if (unlikely(ret)) {
1445 if (ret == 1) {
1446 spin_unlock(&q->lock);
1447 return NET_XMIT_CN;
1448 }
1449 goto again;
1450 }
1451
1452 write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
1453
1454 q->in_use++;
1455 if (++q->pidx >= q->size) {
1456 q->pidx = 0;
1457 q->gen ^= 1;
1458 }
1459 spin_unlock(&q->lock);
1460 wmb();
1461 t3_write_reg(adap, A_SG_KDOORBELL,
1462 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1463 return NET_XMIT_SUCCESS;
1464}
1465
1466/**
1467 * restart_ctrlq - restart a suspended control queue
1468 * @qs: the queue set cotaining the control queue
1469 *
1470 * Resumes transmission on a suspended Tx control queue.
1471 */
1472static void restart_ctrlq(unsigned long data)
1473{
1474 struct sk_buff *skb;
1475 struct sge_qset *qs = (struct sge_qset *)data;
1476 struct sge_txq *q = &qs->txq[TXQ_CTRL];
Divy Le Ray4d22de32007-01-18 22:04:14 -05001477
1478 spin_lock(&q->lock);
1479 again:reclaim_completed_tx_imm(q);
1480
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001481 while (q->in_use < q->size &&
1482 (skb = __skb_dequeue(&q->sendq)) != NULL) {
Divy Le Ray4d22de32007-01-18 22:04:14 -05001483
1484 write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
1485
1486 if (++q->pidx >= q->size) {
1487 q->pidx = 0;
1488 q->gen ^= 1;
1489 }
1490 q->in_use++;
1491 }
1492
1493 if (!skb_queue_empty(&q->sendq)) {
1494 set_bit(TXQ_CTRL, &qs->txq_stopped);
1495 smp_mb__after_clear_bit();
1496
1497 if (should_restart_tx(q) &&
1498 test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped))
1499 goto again;
1500 q->stops++;
1501 }
1502
1503 spin_unlock(&q->lock);
Divy Le Rayafefce62007-11-16 11:22:21 -08001504 wmb();
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001505 t3_write_reg(qs->adap, A_SG_KDOORBELL,
Divy Le Ray4d22de32007-01-18 22:04:14 -05001506 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1507}
1508
Divy Le Ray14ab9892007-01-30 19:43:50 -08001509/*
1510 * Send a management message through control queue 0
1511 */
1512int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
1513{
Divy Le Ray204e2f92008-05-06 19:26:01 -07001514 int ret;
Divy Le Raybc4b6b522007-12-17 18:47:41 -08001515 local_bh_disable();
1516 ret = ctrl_xmit(adap, &adap->sge.qs[0].txq[TXQ_CTRL], skb);
1517 local_bh_enable();
1518
1519 return ret;
Divy Le Ray14ab9892007-01-30 19:43:50 -08001520}
1521
Divy Le Ray4d22de32007-01-18 22:04:14 -05001522/**
Divy Le Ray99d7cf32007-02-24 16:44:06 -08001523 * deferred_unmap_destructor - unmap a packet when it is freed
1524 * @skb: the packet
1525 *
1526 * This is the packet destructor used for Tx packets that need to remain
1527 * mapped until they are freed rather than until their Tx descriptors are
1528 * freed.
1529 */
1530static void deferred_unmap_destructor(struct sk_buff *skb)
1531{
1532 int i;
1533 const dma_addr_t *p;
1534 const struct skb_shared_info *si;
1535 const struct deferred_unmap_info *dui;
Divy Le Ray99d7cf32007-02-24 16:44:06 -08001536
1537 dui = (struct deferred_unmap_info *)skb->head;
1538 p = dui->addr;
1539
Divy Le Ray23561c92007-11-16 11:22:05 -08001540 if (skb->tail - skb->transport_header)
1541 pci_unmap_single(dui->pdev, *p++,
1542 skb->tail - skb->transport_header,
1543 PCI_DMA_TODEVICE);
Divy Le Ray99d7cf32007-02-24 16:44:06 -08001544
1545 si = skb_shinfo(skb);
1546 for (i = 0; i < si->nr_frags; i++)
1547 pci_unmap_page(dui->pdev, *p++, si->frags[i].size,
1548 PCI_DMA_TODEVICE);
1549}
1550
1551static void setup_deferred_unmapping(struct sk_buff *skb, struct pci_dev *pdev,
1552 const struct sg_ent *sgl, int sgl_flits)
1553{
1554 dma_addr_t *p;
1555 struct deferred_unmap_info *dui;
1556
1557 dui = (struct deferred_unmap_info *)skb->head;
1558 dui->pdev = pdev;
1559 for (p = dui->addr; sgl_flits >= 3; sgl++, sgl_flits -= 3) {
1560 *p++ = be64_to_cpu(sgl->addr[0]);
1561 *p++ = be64_to_cpu(sgl->addr[1]);
1562 }
1563 if (sgl_flits)
1564 *p = be64_to_cpu(sgl->addr[0]);
1565}
1566
1567/**
Divy Le Ray4d22de32007-01-18 22:04:14 -05001568 * write_ofld_wr - write an offload work request
1569 * @adap: the adapter
1570 * @skb: the packet to send
1571 * @q: the Tx queue
1572 * @pidx: index of the first Tx descriptor to write
1573 * @gen: the generation value to use
1574 * @ndesc: number of descriptors the packet will occupy
1575 *
1576 * Write an offload work request to send the supplied packet. The packet
1577 * data already carry the work request with most fields populated.
1578 */
1579static void write_ofld_wr(struct adapter *adap, struct sk_buff *skb,
1580 struct sge_txq *q, unsigned int pidx,
1581 unsigned int gen, unsigned int ndesc)
1582{
1583 unsigned int sgl_flits, flits;
1584 struct work_request_hdr *from;
1585 struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
1586 struct tx_desc *d = &q->desc[pidx];
1587
1588 if (immediate(skb)) {
1589 q->sdesc[pidx].skb = NULL;
1590 write_imm(d, skb, skb->len, gen);
1591 return;
1592 }
1593
1594 /* Only TX_DATA builds SGLs */
1595
1596 from = (struct work_request_hdr *)skb->data;
Arnaldo Carvalho de Meloea2ae172007-04-25 17:55:53 -07001597 memcpy(&d->flit[1], &from[1],
1598 skb_transport_offset(skb) - sizeof(*from));
Divy Le Ray4d22de32007-01-18 22:04:14 -05001599
Arnaldo Carvalho de Meloea2ae172007-04-25 17:55:53 -07001600 flits = skb_transport_offset(skb) / 8;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001601 sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
Arnaldo Carvalho de Melo9c702202007-04-25 18:04:18 -07001602 sgl_flits = make_sgl(skb, sgp, skb_transport_header(skb),
Arnaldo Carvalho de Melo27a884d2007-04-19 20:29:13 -07001603 skb->tail - skb->transport_header,
Divy Le Ray4d22de32007-01-18 22:04:14 -05001604 adap->pdev);
Divy Le Ray99d7cf32007-02-24 16:44:06 -08001605 if (need_skb_unmap()) {
1606 setup_deferred_unmapping(skb, adap->pdev, sgp, sgl_flits);
1607 skb->destructor = deferred_unmap_destructor;
Divy Le Ray99d7cf32007-02-24 16:44:06 -08001608 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05001609
1610 write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits,
1611 gen, from->wr_hi, from->wr_lo);
1612}
1613
1614/**
1615 * calc_tx_descs_ofld - calculate # of Tx descriptors for an offload packet
1616 * @skb: the packet
1617 *
1618 * Returns the number of Tx descriptors needed for the given offload
1619 * packet. These packets are already fully constructed.
1620 */
1621static inline unsigned int calc_tx_descs_ofld(const struct sk_buff *skb)
1622{
Divy Le Ray27186dc2007-08-21 20:49:15 -07001623 unsigned int flits, cnt;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001624
Divy Le Ray27186dc2007-08-21 20:49:15 -07001625 if (skb->len <= WR_LEN)
Divy Le Ray4d22de32007-01-18 22:04:14 -05001626 return 1; /* packet fits as immediate data */
1627
Arnaldo Carvalho de Meloea2ae172007-04-25 17:55:53 -07001628 flits = skb_transport_offset(skb) / 8; /* headers */
Divy Le Ray27186dc2007-08-21 20:49:15 -07001629 cnt = skb_shinfo(skb)->nr_frags;
Arnaldo Carvalho de Melo27a884d2007-04-19 20:29:13 -07001630 if (skb->tail != skb->transport_header)
Divy Le Ray4d22de32007-01-18 22:04:14 -05001631 cnt++;
1632 return flits_to_desc(flits + sgl_len(cnt));
1633}
1634
1635/**
1636 * ofld_xmit - send a packet through an offload queue
1637 * @adap: the adapter
1638 * @q: the Tx offload queue
1639 * @skb: the packet
1640 *
1641 * Send an offload packet through an SGE offload queue.
1642 */
1643static int ofld_xmit(struct adapter *adap, struct sge_txq *q,
1644 struct sk_buff *skb)
1645{
1646 int ret;
1647 unsigned int ndesc = calc_tx_descs_ofld(skb), pidx, gen;
1648
1649 spin_lock(&q->lock);
Divy Le Ray42c8ea12009-03-12 21:14:04 +00001650again: reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001651
1652 ret = check_desc_avail(adap, q, skb, ndesc, TXQ_OFLD);
1653 if (unlikely(ret)) {
1654 if (ret == 1) {
1655 skb->priority = ndesc; /* save for restart */
1656 spin_unlock(&q->lock);
1657 return NET_XMIT_CN;
1658 }
1659 goto again;
1660 }
1661
1662 gen = q->gen;
1663 q->in_use += ndesc;
1664 pidx = q->pidx;
1665 q->pidx += ndesc;
1666 if (q->pidx >= q->size) {
1667 q->pidx -= q->size;
1668 q->gen ^= 1;
1669 }
1670 spin_unlock(&q->lock);
1671
1672 write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
1673 check_ring_tx_db(adap, q);
1674 return NET_XMIT_SUCCESS;
1675}
1676
1677/**
1678 * restart_offloadq - restart a suspended offload queue
1679 * @qs: the queue set cotaining the offload queue
1680 *
1681 * Resumes transmission on a suspended Tx offload queue.
1682 */
1683static void restart_offloadq(unsigned long data)
1684{
1685 struct sk_buff *skb;
1686 struct sge_qset *qs = (struct sge_qset *)data;
1687 struct sge_txq *q = &qs->txq[TXQ_OFLD];
Divy Le Ray5fbf8162007-08-29 19:15:47 -07001688 const struct port_info *pi = netdev_priv(qs->netdev);
1689 struct adapter *adap = pi->adapter;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001690
1691 spin_lock(&q->lock);
Divy Le Ray42c8ea12009-03-12 21:14:04 +00001692again: reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001693
1694 while ((skb = skb_peek(&q->sendq)) != NULL) {
1695 unsigned int gen, pidx;
1696 unsigned int ndesc = skb->priority;
1697
1698 if (unlikely(q->size - q->in_use < ndesc)) {
1699 set_bit(TXQ_OFLD, &qs->txq_stopped);
1700 smp_mb__after_clear_bit();
1701
1702 if (should_restart_tx(q) &&
1703 test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped))
1704 goto again;
1705 q->stops++;
1706 break;
1707 }
1708
1709 gen = q->gen;
1710 q->in_use += ndesc;
1711 pidx = q->pidx;
1712 q->pidx += ndesc;
1713 if (q->pidx >= q->size) {
1714 q->pidx -= q->size;
1715 q->gen ^= 1;
1716 }
1717 __skb_unlink(skb, &q->sendq);
1718 spin_unlock(&q->lock);
1719
1720 write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
1721 spin_lock(&q->lock);
1722 }
1723 spin_unlock(&q->lock);
1724
1725#if USE_GTS
1726 set_bit(TXQ_RUNNING, &q->flags);
1727 set_bit(TXQ_LAST_PKT_DB, &q->flags);
1728#endif
Divy Le Rayafefce62007-11-16 11:22:21 -08001729 wmb();
Divy Le Ray4d22de32007-01-18 22:04:14 -05001730 t3_write_reg(adap, A_SG_KDOORBELL,
1731 F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
1732}
1733
1734/**
1735 * queue_set - return the queue set a packet should use
1736 * @skb: the packet
1737 *
1738 * Maps a packet to the SGE queue set it should use. The desired queue
1739 * set is carried in bits 1-3 in the packet's priority.
1740 */
1741static inline int queue_set(const struct sk_buff *skb)
1742{
1743 return skb->priority >> 1;
1744}
1745
1746/**
1747 * is_ctrl_pkt - return whether an offload packet is a control packet
1748 * @skb: the packet
1749 *
1750 * Determines whether an offload packet should use an OFLD or a CTRL
1751 * Tx queue. This is indicated by bit 0 in the packet's priority.
1752 */
1753static inline int is_ctrl_pkt(const struct sk_buff *skb)
1754{
1755 return skb->priority & 1;
1756}
1757
1758/**
1759 * t3_offload_tx - send an offload packet
1760 * @tdev: the offload device to send to
1761 * @skb: the packet
1762 *
1763 * Sends an offload packet. We use the packet priority to select the
1764 * appropriate Tx queue as follows: bit 0 indicates whether the packet
1765 * should be sent as regular or control, bits 1-3 select the queue set.
1766 */
1767int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
1768{
1769 struct adapter *adap = tdev2adap(tdev);
1770 struct sge_qset *qs = &adap->sge.qs[queue_set(skb)];
1771
1772 if (unlikely(is_ctrl_pkt(skb)))
1773 return ctrl_xmit(adap, &qs->txq[TXQ_CTRL], skb);
1774
1775 return ofld_xmit(adap, &qs->txq[TXQ_OFLD], skb);
1776}
1777
1778/**
1779 * offload_enqueue - add an offload packet to an SGE offload receive queue
1780 * @q: the SGE response queue
1781 * @skb: the packet
1782 *
1783 * Add a new offload packet to an SGE response queue's offload packet
1784 * queue. If the packet is the first on the queue it schedules the RX
1785 * softirq to process the queue.
1786 */
1787static inline void offload_enqueue(struct sge_rspq *q, struct sk_buff *skb)
1788{
David S. Miller147e70e2008-09-22 01:29:52 -07001789 int was_empty = skb_queue_empty(&q->rx_queue);
1790
1791 __skb_queue_tail(&q->rx_queue, skb);
1792
1793 if (was_empty) {
Divy Le Ray4d22de32007-01-18 22:04:14 -05001794 struct sge_qset *qs = rspq_to_qset(q);
1795
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001796 napi_schedule(&qs->napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001797 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05001798}
1799
1800/**
1801 * deliver_partial_bundle - deliver a (partial) bundle of Rx offload pkts
1802 * @tdev: the offload device that will be receiving the packets
1803 * @q: the SGE response queue that assembled the bundle
1804 * @skbs: the partial bundle
1805 * @n: the number of packets in the bundle
1806 *
1807 * Delivers a (partial) bundle of Rx offload packets to an offload device.
1808 */
1809static inline void deliver_partial_bundle(struct t3cdev *tdev,
1810 struct sge_rspq *q,
1811 struct sk_buff *skbs[], int n)
1812{
1813 if (n) {
1814 q->offload_bundles++;
1815 tdev->recv(tdev, skbs, n);
1816 }
1817}
1818
1819/**
1820 * ofld_poll - NAPI handler for offload packets in interrupt mode
1821 * @dev: the network device doing the polling
1822 * @budget: polling budget
1823 *
1824 * The NAPI handler for offload packets when a response queue is serviced
1825 * by the hard interrupt handler, i.e., when it's operating in non-polling
1826 * mode. Creates small packet batches and sends them through the offload
1827 * receive handler. Batches need to be of modest size as we do prefetches
1828 * on the packets in each.
1829 */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001830static int ofld_poll(struct napi_struct *napi, int budget)
Divy Le Ray4d22de32007-01-18 22:04:14 -05001831{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001832 struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001833 struct sge_rspq *q = &qs->rspq;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001834 struct adapter *adapter = qs->adap;
1835 int work_done = 0;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001836
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001837 while (work_done < budget) {
David S. Miller147e70e2008-09-22 01:29:52 -07001838 struct sk_buff *skb, *tmp, *skbs[RX_BUNDLE_SIZE];
1839 struct sk_buff_head queue;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001840 int ngathered;
1841
1842 spin_lock_irq(&q->lock);
David S. Miller147e70e2008-09-22 01:29:52 -07001843 __skb_queue_head_init(&queue);
1844 skb_queue_splice_init(&q->rx_queue, &queue);
1845 if (skb_queue_empty(&queue)) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001846 napi_complete(napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001847 spin_unlock_irq(&q->lock);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001848 return work_done;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001849 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05001850 spin_unlock_irq(&q->lock);
1851
David S. Miller147e70e2008-09-22 01:29:52 -07001852 ngathered = 0;
1853 skb_queue_walk_safe(&queue, skb, tmp) {
1854 if (work_done >= budget)
1855 break;
1856 work_done++;
1857
1858 __skb_unlink(skb, &queue);
1859 prefetch(skb->data);
1860 skbs[ngathered] = skb;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001861 if (++ngathered == RX_BUNDLE_SIZE) {
1862 q->offload_bundles++;
1863 adapter->tdev.recv(&adapter->tdev, skbs,
1864 ngathered);
1865 ngathered = 0;
1866 }
1867 }
David S. Miller147e70e2008-09-22 01:29:52 -07001868 if (!skb_queue_empty(&queue)) {
1869 /* splice remaining packets back onto Rx queue */
Divy Le Ray4d22de32007-01-18 22:04:14 -05001870 spin_lock_irq(&q->lock);
David S. Miller147e70e2008-09-22 01:29:52 -07001871 skb_queue_splice(&queue, &q->rx_queue);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001872 spin_unlock_irq(&q->lock);
1873 }
1874 deliver_partial_bundle(&adapter->tdev, q, skbs, ngathered);
1875 }
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001876
1877 return work_done;
Divy Le Ray4d22de32007-01-18 22:04:14 -05001878}
1879
1880/**
1881 * rx_offload - process a received offload packet
1882 * @tdev: the offload device receiving the packet
1883 * @rq: the response queue that received the packet
1884 * @skb: the packet
1885 * @rx_gather: a gather list of packets if we are building a bundle
1886 * @gather_idx: index of the next available slot in the bundle
1887 *
1888 * Process an ingress offload pakcet and add it to the offload ingress
1889 * queue. Returns the index of the next available slot in the bundle.
1890 */
1891static inline int rx_offload(struct t3cdev *tdev, struct sge_rspq *rq,
1892 struct sk_buff *skb, struct sk_buff *rx_gather[],
1893 unsigned int gather_idx)
1894{
Arnaldo Carvalho de Melo459a98e2007-03-19 15:30:44 -07001895 skb_reset_mac_header(skb);
Arnaldo Carvalho de Meloc1d2bbe2007-04-10 20:45:18 -07001896 skb_reset_network_header(skb);
Arnaldo Carvalho de Melobadff6d2007-03-13 13:06:52 -03001897 skb_reset_transport_header(skb);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001898
1899 if (rq->polling) {
1900 rx_gather[gather_idx++] = skb;
1901 if (gather_idx == RX_BUNDLE_SIZE) {
1902 tdev->recv(tdev, rx_gather, RX_BUNDLE_SIZE);
1903 gather_idx = 0;
1904 rq->offload_bundles++;
1905 }
1906 } else
1907 offload_enqueue(rq, skb);
1908
1909 return gather_idx;
1910}
1911
1912/**
Divy Le Ray4d22de32007-01-18 22:04:14 -05001913 * restart_tx - check whether to restart suspended Tx queues
1914 * @qs: the queue set to resume
1915 *
1916 * Restarts suspended Tx queues of an SGE queue set if they have enough
1917 * free resources to resume operation.
1918 */
1919static void restart_tx(struct sge_qset *qs)
1920{
1921 if (test_bit(TXQ_ETH, &qs->txq_stopped) &&
1922 should_restart_tx(&qs->txq[TXQ_ETH]) &&
1923 test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
1924 qs->txq[TXQ_ETH].restarts++;
1925 if (netif_running(qs->netdev))
Divy Le Ray82ad3322008-12-16 01:09:39 -08001926 netif_tx_wake_queue(qs->tx_q);
Divy Le Ray4d22de32007-01-18 22:04:14 -05001927 }
1928
1929 if (test_bit(TXQ_OFLD, &qs->txq_stopped) &&
1930 should_restart_tx(&qs->txq[TXQ_OFLD]) &&
1931 test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped)) {
1932 qs->txq[TXQ_OFLD].restarts++;
1933 tasklet_schedule(&qs->txq[TXQ_OFLD].qresume_tsk);
1934 }
1935 if (test_bit(TXQ_CTRL, &qs->txq_stopped) &&
1936 should_restart_tx(&qs->txq[TXQ_CTRL]) &&
1937 test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped)) {
1938 qs->txq[TXQ_CTRL].restarts++;
1939 tasklet_schedule(&qs->txq[TXQ_CTRL].qresume_tsk);
1940 }
1941}
1942
1943/**
Karen Xiea109a5b2008-12-18 22:56:20 -08001944 * cxgb3_arp_process - process an ARP request probing a private IP address
1945 * @adapter: the adapter
1946 * @skb: the skbuff containing the ARP request
1947 *
1948 * Check if the ARP request is probing the private IP address
1949 * dedicated to iSCSI, generate an ARP reply if so.
1950 */
Karen Xief14d42f2009-10-08 09:11:05 +00001951static void cxgb3_arp_process(struct port_info *pi, struct sk_buff *skb)
Karen Xiea109a5b2008-12-18 22:56:20 -08001952{
1953 struct net_device *dev = skb->dev;
Karen Xiea109a5b2008-12-18 22:56:20 -08001954 struct arphdr *arp;
1955 unsigned char *arp_ptr;
1956 unsigned char *sha;
1957 __be32 sip, tip;
1958
1959 if (!dev)
1960 return;
1961
1962 skb_reset_network_header(skb);
1963 arp = arp_hdr(skb);
1964
1965 if (arp->ar_op != htons(ARPOP_REQUEST))
1966 return;
1967
1968 arp_ptr = (unsigned char *)(arp + 1);
1969 sha = arp_ptr;
1970 arp_ptr += dev->addr_len;
1971 memcpy(&sip, arp_ptr, sizeof(sip));
1972 arp_ptr += sizeof(sip);
1973 arp_ptr += dev->addr_len;
1974 memcpy(&tip, arp_ptr, sizeof(tip));
1975
Karen Xiea109a5b2008-12-18 22:56:20 -08001976 if (tip != pi->iscsi_ipv4addr)
1977 return;
1978
1979 arp_send(ARPOP_REPLY, ETH_P_ARP, sip, dev, tip, sha,
Karen Xief14d42f2009-10-08 09:11:05 +00001980 pi->iscsic.mac_addr, sha);
Karen Xiea109a5b2008-12-18 22:56:20 -08001981
1982}
1983
1984static inline int is_arp(struct sk_buff *skb)
1985{
1986 return skb->protocol == htons(ETH_P_ARP);
1987}
1988
Karen Xief14d42f2009-10-08 09:11:05 +00001989static void cxgb3_process_iscsi_prov_pack(struct port_info *pi,
1990 struct sk_buff *skb)
1991{
1992 if (is_arp(skb)) {
1993 cxgb3_arp_process(pi, skb);
1994 return;
1995 }
1996
1997 if (pi->iscsic.recv)
1998 pi->iscsic.recv(pi, skb);
1999
2000}
2001
Karen Xiea109a5b2008-12-18 22:56:20 -08002002/**
Divy Le Ray4d22de32007-01-18 22:04:14 -05002003 * rx_eth - process an ingress ethernet packet
2004 * @adap: the adapter
2005 * @rq: the response queue that received the packet
2006 * @skb: the packet
2007 * @pad: amount of padding at the start of the buffer
2008 *
2009 * Process an ingress ethernet pakcet and deliver it to the stack.
2010 * The padding is 2 if the packet was delivered in an Rx buffer and 0
2011 * if it was immediate data in a response.
2012 */
2013static void rx_eth(struct adapter *adap, struct sge_rspq *rq,
Divy Le Rayb47385b2008-05-21 18:56:26 -07002014 struct sk_buff *skb, int pad, int lro)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002015{
2016 struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)(skb->data + pad);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002017 struct sge_qset *qs = rspq_to_qset(rq);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002018 struct port_info *pi;
2019
Divy Le Ray4d22de32007-01-18 22:04:14 -05002020 skb_pull(skb, sizeof(*p) + pad);
Arnaldo Carvalho de Melo4c13eb62007-04-25 17:40:23 -07002021 skb->protocol = eth_type_trans(skb, adap->port[p->iff]);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002022 pi = netdev_priv(skb->dev);
Michał Mirosławd2fe2752011-04-17 00:15:46 +00002023 if ((skb->dev->features & NETIF_F_RXCSUM) && p->csum_valid &&
Divy Le Ray5e68b772009-03-26 16:39:29 +00002024 p->csum == htons(0xffff) && !p->fragment) {
Karen Xiea109a5b2008-12-18 22:56:20 -08002025 qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002026 skb->ip_summed = CHECKSUM_UNNECESSARY;
2027 } else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07002028 skb_checksum_none_assert(skb);
David S. Miller0c8dfc82009-01-27 16:22:32 -08002029 skb_record_rx_queue(skb, qs - &adap->sge.qs[0]);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002030
2031 if (unlikely(p->vlan_valid)) {
2032 struct vlan_group *grp = pi->vlan_grp;
2033
Divy Le Rayb47385b2008-05-21 18:56:26 -07002034 qs->port_stats[SGE_PSTAT_VLANEX]++;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002035 if (likely(grp))
Divy Le Rayb47385b2008-05-21 18:56:26 -07002036 if (lro)
Herbert Xu7be2df42009-01-21 14:39:13 -08002037 vlan_gro_receive(&qs->napi, grp,
2038 ntohs(p->vlan), skb);
Karen Xiea109a5b2008-12-18 22:56:20 -08002039 else {
Karen Xief14d42f2009-10-08 09:11:05 +00002040 if (unlikely(pi->iscsic.flags)) {
Karen Xiea109a5b2008-12-18 22:56:20 -08002041 unsigned short vtag = ntohs(p->vlan) &
2042 VLAN_VID_MASK;
2043 skb->dev = vlan_group_get_device(grp,
2044 vtag);
Karen Xief14d42f2009-10-08 09:11:05 +00002045 cxgb3_process_iscsi_prov_pack(pi, skb);
Karen Xiea109a5b2008-12-18 22:56:20 -08002046 }
Divy Le Rayb47385b2008-05-21 18:56:26 -07002047 __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan),
2048 rq->polling);
Karen Xiea109a5b2008-12-18 22:56:20 -08002049 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05002050 else
2051 dev_kfree_skb_any(skb);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002052 } else if (rq->polling) {
2053 if (lro)
Herbert Xu7be2df42009-01-21 14:39:13 -08002054 napi_gro_receive(&qs->napi, skb);
Karen Xiea109a5b2008-12-18 22:56:20 -08002055 else {
Karen Xief14d42f2009-10-08 09:11:05 +00002056 if (unlikely(pi->iscsic.flags))
2057 cxgb3_process_iscsi_prov_pack(pi, skb);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002058 netif_receive_skb(skb);
Karen Xiea109a5b2008-12-18 22:56:20 -08002059 }
Divy Le Rayb47385b2008-05-21 18:56:26 -07002060 } else
Divy Le Ray4d22de32007-01-18 22:04:14 -05002061 netif_rx(skb);
2062}
2063
Divy Le Rayb47385b2008-05-21 18:56:26 -07002064static inline int is_eth_tcp(u32 rss)
2065{
2066 return G_HASHTYPE(ntohl(rss)) == RSS_HASH_4_TUPLE;
2067}
2068
2069/**
Divy Le Rayb47385b2008-05-21 18:56:26 -07002070 * lro_add_page - add a page chunk to an LRO session
2071 * @adap: the adapter
2072 * @qs: the associated queue set
2073 * @fl: the free list containing the page chunk to add
2074 * @len: packet length
2075 * @complete: Indicates the last fragment of a frame
2076 *
2077 * Add a received packet contained in a page chunk to an existing LRO
2078 * session.
2079 */
2080static void lro_add_page(struct adapter *adap, struct sge_qset *qs,
2081 struct sge_fl *fl, int len, int complete)
2082{
2083 struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
Divy Le Ray2d171882010-02-08 22:37:24 -08002084 struct port_info *pi = netdev_priv(qs->netdev);
Herbert Xu76620aa2009-04-16 02:02:07 -07002085 struct sk_buff *skb = NULL;
Divy Le Rayb47385b2008-05-21 18:56:26 -07002086 struct cpl_rx_pkt *cpl;
Herbert Xu76620aa2009-04-16 02:02:07 -07002087 struct skb_frag_struct *rx_frag;
2088 int nr_frags;
Divy Le Rayb47385b2008-05-21 18:56:26 -07002089 int offset = 0;
2090
Herbert Xu76620aa2009-04-16 02:02:07 -07002091 if (!qs->nomem) {
2092 skb = napi_get_frags(&qs->napi);
2093 qs->nomem = !skb;
Divy Le Rayb47385b2008-05-21 18:56:26 -07002094 }
2095
2096 fl->credits--;
2097
Divy Le Ray5e68b772009-03-26 16:39:29 +00002098 pci_dma_sync_single_for_cpu(adap->pdev,
FUJITA Tomonori56e3b9d2010-04-12 14:32:12 +00002099 dma_unmap_addr(sd, dma_addr),
Divy Le Ray5e68b772009-03-26 16:39:29 +00002100 fl->buf_size - SGE_PG_RSVD,
2101 PCI_DMA_FROMDEVICE);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002102
Divy Le Ray5e68b772009-03-26 16:39:29 +00002103 (*sd->pg_chunk.p_cnt)--;
Divy Le Ray70e3bb52009-11-17 16:38:28 +00002104 if (!*sd->pg_chunk.p_cnt && sd->pg_chunk.page != fl->pg_chunk.page)
Divy Le Ray5e68b772009-03-26 16:39:29 +00002105 pci_unmap_page(adap->pdev,
Divy Le Ray10b6d952009-05-28 11:23:02 +00002106 sd->pg_chunk.mapping,
Divy Le Ray5e68b772009-03-26 16:39:29 +00002107 fl->alloc_size,
2108 PCI_DMA_FROMDEVICE);
2109
Herbert Xu76620aa2009-04-16 02:02:07 -07002110 if (!skb) {
2111 put_page(sd->pg_chunk.page);
2112 if (complete)
2113 qs->nomem = 0;
2114 return;
2115 }
2116
2117 rx_frag = skb_shinfo(skb)->frags;
2118 nr_frags = skb_shinfo(skb)->nr_frags;
2119
2120 if (!nr_frags) {
2121 offset = 2 + sizeof(struct cpl_rx_pkt);
Divy Le Ray2d171882010-02-08 22:37:24 -08002122 cpl = qs->lro_va = sd->pg_chunk.va + 2;
Herbert Xu76620aa2009-04-16 02:02:07 -07002123
Michał Mirosławd2fe2752011-04-17 00:15:46 +00002124 if ((qs->netdev->features & NETIF_F_RXCSUM) &&
Divy Le Ray2d171882010-02-08 22:37:24 -08002125 cpl->csum_valid && cpl->csum == htons(0xffff)) {
2126 skb->ip_summed = CHECKSUM_UNNECESSARY;
2127 qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++;
2128 } else
2129 skb->ip_summed = CHECKSUM_NONE;
2130 } else
2131 cpl = qs->lro_va;
2132
2133 len -= offset;
Divy Le Rayb2b964f2009-03-12 21:13:59 +00002134
Divy Le Rayb47385b2008-05-21 18:56:26 -07002135 rx_frag += nr_frags;
2136 rx_frag->page = sd->pg_chunk.page;
2137 rx_frag->page_offset = sd->pg_chunk.offset + offset;
2138 rx_frag->size = len;
Divy Le Rayb47385b2008-05-21 18:56:26 -07002139
Herbert Xu76620aa2009-04-16 02:02:07 -07002140 skb->len += len;
2141 skb->data_len += len;
2142 skb->truesize += len;
2143 skb_shinfo(skb)->nr_frags++;
Divy Le Ray5e68b772009-03-26 16:39:29 +00002144
Divy Le Rayb47385b2008-05-21 18:56:26 -07002145 if (!complete)
2146 return;
2147
Krishna Kumar10e85f72009-10-23 01:13:21 +00002148 skb_record_rx_queue(skb, qs - &adap->sge.qs[0]);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002149
2150 if (unlikely(cpl->vlan_valid)) {
Divy Le Rayb47385b2008-05-21 18:56:26 -07002151 struct vlan_group *grp = pi->vlan_grp;
2152
2153 if (likely(grp != NULL)) {
Herbert Xu76620aa2009-04-16 02:02:07 -07002154 vlan_gro_frags(&qs->napi, grp, ntohs(cpl->vlan));
2155 return;
Divy Le Rayb47385b2008-05-21 18:56:26 -07002156 }
2157 }
Herbert Xu76620aa2009-04-16 02:02:07 -07002158 napi_gro_frags(&qs->napi);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002159}
2160
Divy Le Ray4d22de32007-01-18 22:04:14 -05002161/**
2162 * handle_rsp_cntrl_info - handles control information in a response
2163 * @qs: the queue set corresponding to the response
2164 * @flags: the response control flags
Divy Le Ray4d22de32007-01-18 22:04:14 -05002165 *
2166 * Handles the control information of an SGE response, such as GTS
2167 * indications and completion credits for the queue set's Tx queues.
Divy Le Ray6195c712007-01-30 19:43:56 -08002168 * HW coalesces credits, we don't do any extra SW coalescing.
Divy Le Ray4d22de32007-01-18 22:04:14 -05002169 */
Divy Le Ray6195c712007-01-30 19:43:56 -08002170static inline void handle_rsp_cntrl_info(struct sge_qset *qs, u32 flags)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002171{
2172 unsigned int credits;
2173
2174#if USE_GTS
2175 if (flags & F_RSPD_TXQ0_GTS)
2176 clear_bit(TXQ_RUNNING, &qs->txq[TXQ_ETH].flags);
2177#endif
2178
Divy Le Ray4d22de32007-01-18 22:04:14 -05002179 credits = G_RSPD_TXQ0_CR(flags);
2180 if (credits)
2181 qs->txq[TXQ_ETH].processed += credits;
2182
Divy Le Ray6195c712007-01-30 19:43:56 -08002183 credits = G_RSPD_TXQ2_CR(flags);
2184 if (credits)
2185 qs->txq[TXQ_CTRL].processed += credits;
2186
Divy Le Ray4d22de32007-01-18 22:04:14 -05002187# if USE_GTS
2188 if (flags & F_RSPD_TXQ1_GTS)
2189 clear_bit(TXQ_RUNNING, &qs->txq[TXQ_OFLD].flags);
2190# endif
Divy Le Ray6195c712007-01-30 19:43:56 -08002191 credits = G_RSPD_TXQ1_CR(flags);
2192 if (credits)
2193 qs->txq[TXQ_OFLD].processed += credits;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002194}
2195
2196/**
2197 * check_ring_db - check if we need to ring any doorbells
2198 * @adapter: the adapter
2199 * @qs: the queue set whose Tx queues are to be examined
2200 * @sleeping: indicates which Tx queue sent GTS
2201 *
2202 * Checks if some of a queue set's Tx queues need to ring their doorbells
2203 * to resume transmission after idling while they still have unprocessed
2204 * descriptors.
2205 */
2206static void check_ring_db(struct adapter *adap, struct sge_qset *qs,
2207 unsigned int sleeping)
2208{
2209 if (sleeping & F_RSPD_TXQ0_GTS) {
2210 struct sge_txq *txq = &qs->txq[TXQ_ETH];
2211
2212 if (txq->cleaned + txq->in_use != txq->processed &&
2213 !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
2214 set_bit(TXQ_RUNNING, &txq->flags);
2215 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
2216 V_EGRCNTX(txq->cntxt_id));
2217 }
2218 }
2219
2220 if (sleeping & F_RSPD_TXQ1_GTS) {
2221 struct sge_txq *txq = &qs->txq[TXQ_OFLD];
2222
2223 if (txq->cleaned + txq->in_use != txq->processed &&
2224 !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
2225 set_bit(TXQ_RUNNING, &txq->flags);
2226 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
2227 V_EGRCNTX(txq->cntxt_id));
2228 }
2229 }
2230}
2231
2232/**
2233 * is_new_response - check if a response is newly written
2234 * @r: the response descriptor
2235 * @q: the response queue
2236 *
2237 * Returns true if a response descriptor contains a yet unprocessed
2238 * response.
2239 */
2240static inline int is_new_response(const struct rsp_desc *r,
2241 const struct sge_rspq *q)
2242{
2243 return (r->intr_gen & F_RSPD_GEN2) == q->gen;
2244}
2245
Divy Le Ray7385ecf2008-05-21 18:56:21 -07002246static inline void clear_rspq_bufstate(struct sge_rspq * const q)
2247{
2248 q->pg_skb = NULL;
2249 q->rx_recycle_buf = 0;
2250}
2251
Divy Le Ray4d22de32007-01-18 22:04:14 -05002252#define RSPD_GTS_MASK (F_RSPD_TXQ0_GTS | F_RSPD_TXQ1_GTS)
2253#define RSPD_CTRL_MASK (RSPD_GTS_MASK | \
2254 V_RSPD_TXQ0_CR(M_RSPD_TXQ0_CR) | \
2255 V_RSPD_TXQ1_CR(M_RSPD_TXQ1_CR) | \
2256 V_RSPD_TXQ2_CR(M_RSPD_TXQ2_CR))
2257
2258/* How long to delay the next interrupt in case of memory shortage, in 0.1us. */
2259#define NOMEM_INTR_DELAY 2500
2260
2261/**
2262 * process_responses - process responses from an SGE response queue
2263 * @adap: the adapter
2264 * @qs: the queue set to which the response queue belongs
2265 * @budget: how many responses can be processed in this round
2266 *
2267 * Process responses from an SGE response queue up to the supplied budget.
2268 * Responses include received packets as well as credits and other events
2269 * for the queues that belong to the response queue's queue set.
2270 * A negative budget is effectively unlimited.
2271 *
2272 * Additionally choose the interrupt holdoff time for the next interrupt
2273 * on this queue. If the system is under memory shortage use a fairly
2274 * long delay to help recovery.
2275 */
2276static int process_responses(struct adapter *adap, struct sge_qset *qs,
2277 int budget)
2278{
2279 struct sge_rspq *q = &qs->rspq;
2280 struct rsp_desc *r = &q->desc[q->cidx];
2281 int budget_left = budget;
Divy Le Ray6195c712007-01-30 19:43:56 -08002282 unsigned int sleeping = 0;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002283 struct sk_buff *offload_skbs[RX_BUNDLE_SIZE];
2284 int ngathered = 0;
2285
2286 q->next_holdoff = q->holdoff_tmr;
2287
2288 while (likely(budget_left && is_new_response(r, q))) {
Michał Mirosławd2fe2752011-04-17 00:15:46 +00002289 int packet_complete, eth, ethpad = 2;
2290 int lro = !!(qs->netdev->features & NETIF_F_GRO);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002291 struct sk_buff *skb = NULL;
Divy Le Ray2e026442010-02-01 10:29:29 +00002292 u32 len, flags;
2293 __be32 rss_hi, rss_lo;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002294
Divy Le Ray2e026442010-02-01 10:29:29 +00002295 rmb();
Divy Le Ray4d22de32007-01-18 22:04:14 -05002296 eth = r->rss_hdr.opcode == CPL_RX_PKT;
Divy Le Ray2e026442010-02-01 10:29:29 +00002297 rss_hi = *(const __be32 *)r;
2298 rss_lo = r->rss_hdr.rss_hash_val;
2299 flags = ntohl(r->flags);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002300
2301 if (unlikely(flags & F_RSPD_ASYNC_NOTIF)) {
2302 skb = alloc_skb(AN_PKT_SIZE, GFP_ATOMIC);
2303 if (!skb)
2304 goto no_mem;
2305
2306 memcpy(__skb_put(skb, AN_PKT_SIZE), r, AN_PKT_SIZE);
2307 skb->data[0] = CPL_ASYNC_NOTIF;
2308 rss_hi = htonl(CPL_ASYNC_NOTIF << 24);
2309 q->async_notif++;
2310 } else if (flags & F_RSPD_IMM_DATA_VALID) {
2311 skb = get_imm_packet(r);
2312 if (unlikely(!skb)) {
Divy Le Raycf992af2007-05-30 21:10:47 -07002313no_mem:
Divy Le Ray4d22de32007-01-18 22:04:14 -05002314 q->next_holdoff = NOMEM_INTR_DELAY;
2315 q->nomem++;
2316 /* consume one credit since we tried */
2317 budget_left--;
2318 break;
2319 }
2320 q->imm_data++;
Divy Le Raye0994eb2007-02-24 16:44:17 -08002321 ethpad = 0;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002322 } else if ((len = ntohl(r->len_cq)) != 0) {
Divy Le Raycf992af2007-05-30 21:10:47 -07002323 struct sge_fl *fl;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002324
Divy Le Ray65ab8382009-02-04 16:31:39 -08002325 lro &= eth && is_eth_tcp(rss_hi);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002326
Divy Le Raycf992af2007-05-30 21:10:47 -07002327 fl = (len & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0];
2328 if (fl->use_pages) {
2329 void *addr = fl->sdesc[fl->cidx].pg_chunk.va;
Divy Le Raye0994eb2007-02-24 16:44:17 -08002330
Divy Le Raycf992af2007-05-30 21:10:47 -07002331 prefetch(addr);
2332#if L1_CACHE_BYTES < 128
2333 prefetch(addr + L1_CACHE_BYTES);
2334#endif
Divy Le Raye0994eb2007-02-24 16:44:17 -08002335 __refill_fl(adap, fl);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002336 if (lro > 0) {
2337 lro_add_page(adap, qs, fl,
2338 G_RSPD_LEN(len),
2339 flags & F_RSPD_EOP);
2340 goto next_fl;
2341 }
Divy Le Raye0994eb2007-02-24 16:44:17 -08002342
Divy Le Ray7385ecf2008-05-21 18:56:21 -07002343 skb = get_packet_pg(adap, fl, q,
2344 G_RSPD_LEN(len),
2345 eth ?
2346 SGE_RX_DROP_THRES : 0);
2347 q->pg_skb = skb;
Divy Le Raycf992af2007-05-30 21:10:47 -07002348 } else
Divy Le Raye0994eb2007-02-24 16:44:17 -08002349 skb = get_packet(adap, fl, G_RSPD_LEN(len),
2350 eth ? SGE_RX_DROP_THRES : 0);
Divy Le Raycf992af2007-05-30 21:10:47 -07002351 if (unlikely(!skb)) {
2352 if (!eth)
2353 goto no_mem;
2354 q->rx_drops++;
2355 } else if (unlikely(r->rss_hdr.opcode == CPL_TRACE_PKT))
2356 __skb_pull(skb, 2);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002357next_fl:
Divy Le Ray4d22de32007-01-18 22:04:14 -05002358 if (++fl->cidx == fl->size)
2359 fl->cidx = 0;
2360 } else
2361 q->pure_rsps++;
2362
2363 if (flags & RSPD_CTRL_MASK) {
2364 sleeping |= flags & RSPD_GTS_MASK;
Divy Le Ray6195c712007-01-30 19:43:56 -08002365 handle_rsp_cntrl_info(qs, flags);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002366 }
2367
2368 r++;
2369 if (unlikely(++q->cidx == q->size)) {
2370 q->cidx = 0;
2371 q->gen ^= 1;
2372 r = q->desc;
2373 }
2374 prefetch(r);
2375
2376 if (++q->credits >= (q->size / 4)) {
2377 refill_rspq(adap, q, q->credits);
2378 q->credits = 0;
2379 }
2380
Divy Le Ray7385ecf2008-05-21 18:56:21 -07002381 packet_complete = flags &
2382 (F_RSPD_EOP | F_RSPD_IMM_DATA_VALID |
2383 F_RSPD_ASYNC_NOTIF);
2384
2385 if (skb != NULL && packet_complete) {
Divy Le Ray4d22de32007-01-18 22:04:14 -05002386 if (eth)
Divy Le Rayb47385b2008-05-21 18:56:26 -07002387 rx_eth(adap, q, skb, ethpad, lro);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002388 else {
Divy Le Rayafefce62007-11-16 11:22:21 -08002389 q->offload_pkts++;
Divy Le Raycf992af2007-05-30 21:10:47 -07002390 /* Preserve the RSS info in csum & priority */
2391 skb->csum = rss_hi;
2392 skb->priority = rss_lo;
2393 ngathered = rx_offload(&adap->tdev, q, skb,
2394 offload_skbs,
Divy Le Raye0994eb2007-02-24 16:44:17 -08002395 ngathered);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002396 }
Divy Le Ray7385ecf2008-05-21 18:56:21 -07002397
2398 if (flags & F_RSPD_EOP)
Divy Le Rayb47385b2008-05-21 18:56:26 -07002399 clear_rspq_bufstate(q);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002400 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05002401 --budget_left;
2402 }
2403
Divy Le Ray4d22de32007-01-18 22:04:14 -05002404 deliver_partial_bundle(&adap->tdev, q, offload_skbs, ngathered);
Divy Le Rayb47385b2008-05-21 18:56:26 -07002405
Divy Le Ray4d22de32007-01-18 22:04:14 -05002406 if (sleeping)
2407 check_ring_db(adap, qs, sleeping);
2408
2409 smp_mb(); /* commit Tx queue .processed updates */
2410 if (unlikely(qs->txq_stopped != 0))
2411 restart_tx(qs);
2412
2413 budget -= budget_left;
2414 return budget;
2415}
2416
2417static inline int is_pure_response(const struct rsp_desc *r)
2418{
Roland Dreierc5419e62008-11-28 21:55:42 -08002419 __be32 n = r->flags & htonl(F_RSPD_ASYNC_NOTIF | F_RSPD_IMM_DATA_VALID);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002420
2421 return (n | r->len_cq) == 0;
2422}
2423
2424/**
2425 * napi_rx_handler - the NAPI handler for Rx processing
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002426 * @napi: the napi instance
Divy Le Ray4d22de32007-01-18 22:04:14 -05002427 * @budget: how many packets we can process in this round
2428 *
2429 * Handler for new data events when using NAPI.
2430 */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002431static int napi_rx_handler(struct napi_struct *napi, int budget)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002432{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002433 struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
2434 struct adapter *adap = qs->adap;
2435 int work_done = process_responses(adap, qs, budget);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002436
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002437 if (likely(work_done < budget)) {
2438 napi_complete(napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002439
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002440 /*
2441 * Because we don't atomically flush the following
2442 * write it is possible that in very rare cases it can
2443 * reach the device in a way that races with a new
2444 * response being written plus an error interrupt
2445 * causing the NAPI interrupt handler below to return
2446 * unhandled status to the OS. To protect against
2447 * this would require flushing the write and doing
2448 * both the write and the flush with interrupts off.
2449 * Way too expensive and unjustifiable given the
2450 * rarity of the race.
2451 *
2452 * The race cannot happen at all with MSI-X.
2453 */
2454 t3_write_reg(adap, A_SG_GTS, V_RSPQ(qs->rspq.cntxt_id) |
2455 V_NEWTIMER(qs->rspq.next_holdoff) |
2456 V_NEWINDEX(qs->rspq.cidx));
2457 }
2458 return work_done;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002459}
2460
2461/*
2462 * Returns true if the device is already scheduled for polling.
2463 */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002464static inline int napi_is_scheduled(struct napi_struct *napi)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002465{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002466 return test_bit(NAPI_STATE_SCHED, &napi->state);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002467}
2468
2469/**
2470 * process_pure_responses - process pure responses from a response queue
2471 * @adap: the adapter
2472 * @qs: the queue set owning the response queue
2473 * @r: the first pure response to process
2474 *
2475 * A simpler version of process_responses() that handles only pure (i.e.,
2476 * non data-carrying) responses. Such respones are too light-weight to
2477 * justify calling a softirq under NAPI, so we handle them specially in
2478 * the interrupt handler. The function is called with a pointer to a
2479 * response, which the caller must ensure is a valid pure response.
2480 *
2481 * Returns 1 if it encounters a valid data-carrying response, 0 otherwise.
2482 */
2483static int process_pure_responses(struct adapter *adap, struct sge_qset *qs,
2484 struct rsp_desc *r)
2485{
2486 struct sge_rspq *q = &qs->rspq;
Divy Le Ray6195c712007-01-30 19:43:56 -08002487 unsigned int sleeping = 0;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002488
2489 do {
2490 u32 flags = ntohl(r->flags);
2491
2492 r++;
2493 if (unlikely(++q->cidx == q->size)) {
2494 q->cidx = 0;
2495 q->gen ^= 1;
2496 r = q->desc;
2497 }
2498 prefetch(r);
2499
2500 if (flags & RSPD_CTRL_MASK) {
2501 sleeping |= flags & RSPD_GTS_MASK;
Divy Le Ray6195c712007-01-30 19:43:56 -08002502 handle_rsp_cntrl_info(qs, flags);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002503 }
2504
2505 q->pure_rsps++;
2506 if (++q->credits >= (q->size / 4)) {
2507 refill_rspq(adap, q, q->credits);
2508 q->credits = 0;
2509 }
Divy Le Ray2e026442010-02-01 10:29:29 +00002510 if (!is_new_response(r, q))
2511 break;
2512 rmb();
2513 } while (is_pure_response(r));
Divy Le Ray4d22de32007-01-18 22:04:14 -05002514
Divy Le Ray4d22de32007-01-18 22:04:14 -05002515 if (sleeping)
2516 check_ring_db(adap, qs, sleeping);
2517
2518 smp_mb(); /* commit Tx queue .processed updates */
2519 if (unlikely(qs->txq_stopped != 0))
2520 restart_tx(qs);
2521
2522 return is_new_response(r, q);
2523}
2524
2525/**
2526 * handle_responses - decide what to do with new responses in NAPI mode
2527 * @adap: the adapter
2528 * @q: the response queue
2529 *
2530 * This is used by the NAPI interrupt handlers to decide what to do with
2531 * new SGE responses. If there are no new responses it returns -1. If
2532 * there are new responses and they are pure (i.e., non-data carrying)
2533 * it handles them straight in hard interrupt context as they are very
2534 * cheap and don't deliver any packets. Finally, if there are any data
2535 * signaling responses it schedules the NAPI handler. Returns 1 if it
2536 * schedules NAPI, 0 if all new responses were pure.
2537 *
2538 * The caller must ascertain NAPI is not already running.
2539 */
2540static inline int handle_responses(struct adapter *adap, struct sge_rspq *q)
2541{
2542 struct sge_qset *qs = rspq_to_qset(q);
2543 struct rsp_desc *r = &q->desc[q->cidx];
2544
2545 if (!is_new_response(r, q))
2546 return -1;
Divy Le Ray2e026442010-02-01 10:29:29 +00002547 rmb();
Divy Le Ray4d22de32007-01-18 22:04:14 -05002548 if (is_pure_response(r) && process_pure_responses(adap, qs, r) == 0) {
2549 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
2550 V_NEWTIMER(q->holdoff_tmr) | V_NEWINDEX(q->cidx));
2551 return 0;
2552 }
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002553 napi_schedule(&qs->napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002554 return 1;
2555}
2556
2557/*
2558 * The MSI-X interrupt handler for an SGE response queue for the non-NAPI case
2559 * (i.e., response queue serviced in hard interrupt).
2560 */
stephen hemmingera5190b42010-10-15 12:43:10 +00002561static irqreturn_t t3_sge_intr_msix(int irq, void *cookie)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002562{
2563 struct sge_qset *qs = cookie;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002564 struct adapter *adap = qs->adap;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002565 struct sge_rspq *q = &qs->rspq;
2566
2567 spin_lock(&q->lock);
2568 if (process_responses(adap, qs, -1) == 0)
2569 q->unhandled_irqs++;
2570 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
2571 V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
2572 spin_unlock(&q->lock);
2573 return IRQ_HANDLED;
2574}
2575
2576/*
2577 * The MSI-X interrupt handler for an SGE response queue for the NAPI case
2578 * (i.e., response queue serviced by NAPI polling).
2579 */
Stephen Hemminger9265fab2007-10-08 16:22:29 -07002580static irqreturn_t t3_sge_intr_msix_napi(int irq, void *cookie)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002581{
2582 struct sge_qset *qs = cookie;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002583 struct sge_rspq *q = &qs->rspq;
2584
2585 spin_lock(&q->lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002586
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002587 if (handle_responses(qs->adap, q) < 0)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002588 q->unhandled_irqs++;
2589 spin_unlock(&q->lock);
2590 return IRQ_HANDLED;
2591}
2592
2593/*
2594 * The non-NAPI MSI interrupt handler. This needs to handle data events from
2595 * SGE response queues as well as error and other async events as they all use
2596 * the same MSI vector. We use one SGE response queue per port in this mode
2597 * and protect all response queues with queue 0's lock.
2598 */
2599static irqreturn_t t3_intr_msi(int irq, void *cookie)
2600{
2601 int new_packets = 0;
2602 struct adapter *adap = cookie;
2603 struct sge_rspq *q = &adap->sge.qs[0].rspq;
2604
2605 spin_lock(&q->lock);
2606
2607 if (process_responses(adap, &adap->sge.qs[0], -1)) {
2608 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
2609 V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
2610 new_packets = 1;
2611 }
2612
2613 if (adap->params.nports == 2 &&
2614 process_responses(adap, &adap->sge.qs[1], -1)) {
2615 struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
2616
2617 t3_write_reg(adap, A_SG_GTS, V_RSPQ(q1->cntxt_id) |
2618 V_NEWTIMER(q1->next_holdoff) |
2619 V_NEWINDEX(q1->cidx));
2620 new_packets = 1;
2621 }
2622
2623 if (!new_packets && t3_slow_intr_handler(adap) == 0)
2624 q->unhandled_irqs++;
2625
2626 spin_unlock(&q->lock);
2627 return IRQ_HANDLED;
2628}
2629
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002630static int rspq_check_napi(struct sge_qset *qs)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002631{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002632 struct sge_rspq *q = &qs->rspq;
2633
2634 if (!napi_is_scheduled(&qs->napi) &&
2635 is_new_response(&q->desc[q->cidx], q)) {
2636 napi_schedule(&qs->napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002637 return 1;
2638 }
2639 return 0;
2640}
2641
2642/*
2643 * The MSI interrupt handler for the NAPI case (i.e., response queues serviced
2644 * by NAPI polling). Handles data events from SGE response queues as well as
2645 * error and other async events as they all use the same MSI vector. We use
2646 * one SGE response queue per port in this mode and protect all response
2647 * queues with queue 0's lock.
2648 */
Stephen Hemminger9265fab2007-10-08 16:22:29 -07002649static irqreturn_t t3_intr_msi_napi(int irq, void *cookie)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002650{
2651 int new_packets;
2652 struct adapter *adap = cookie;
2653 struct sge_rspq *q = &adap->sge.qs[0].rspq;
2654
2655 spin_lock(&q->lock);
2656
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002657 new_packets = rspq_check_napi(&adap->sge.qs[0]);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002658 if (adap->params.nports == 2)
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002659 new_packets += rspq_check_napi(&adap->sge.qs[1]);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002660 if (!new_packets && t3_slow_intr_handler(adap) == 0)
2661 q->unhandled_irqs++;
2662
2663 spin_unlock(&q->lock);
2664 return IRQ_HANDLED;
2665}
2666
2667/*
2668 * A helper function that processes responses and issues GTS.
2669 */
2670static inline int process_responses_gts(struct adapter *adap,
2671 struct sge_rspq *rq)
2672{
2673 int work;
2674
2675 work = process_responses(adap, rspq_to_qset(rq), -1);
2676 t3_write_reg(adap, A_SG_GTS, V_RSPQ(rq->cntxt_id) |
2677 V_NEWTIMER(rq->next_holdoff) | V_NEWINDEX(rq->cidx));
2678 return work;
2679}
2680
2681/*
2682 * The legacy INTx interrupt handler. This needs to handle data events from
2683 * SGE response queues as well as error and other async events as they all use
2684 * the same interrupt pin. We use one SGE response queue per port in this mode
2685 * and protect all response queues with queue 0's lock.
2686 */
2687static irqreturn_t t3_intr(int irq, void *cookie)
2688{
2689 int work_done, w0, w1;
2690 struct adapter *adap = cookie;
2691 struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
2692 struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
2693
2694 spin_lock(&q0->lock);
2695
2696 w0 = is_new_response(&q0->desc[q0->cidx], q0);
2697 w1 = adap->params.nports == 2 &&
2698 is_new_response(&q1->desc[q1->cidx], q1);
2699
2700 if (likely(w0 | w1)) {
2701 t3_write_reg(adap, A_PL_CLI, 0);
2702 t3_read_reg(adap, A_PL_CLI); /* flush */
2703
2704 if (likely(w0))
2705 process_responses_gts(adap, q0);
2706
2707 if (w1)
2708 process_responses_gts(adap, q1);
2709
2710 work_done = w0 | w1;
2711 } else
2712 work_done = t3_slow_intr_handler(adap);
2713
2714 spin_unlock(&q0->lock);
2715 return IRQ_RETVAL(work_done != 0);
2716}
2717
2718/*
2719 * Interrupt handler for legacy INTx interrupts for T3B-based cards.
2720 * Handles data events from SGE response queues as well as error and other
2721 * async events as they all use the same interrupt pin. We use one SGE
2722 * response queue per port in this mode and protect all response queues with
2723 * queue 0's lock.
2724 */
2725static irqreturn_t t3b_intr(int irq, void *cookie)
2726{
2727 u32 map;
2728 struct adapter *adap = cookie;
2729 struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
2730
2731 t3_write_reg(adap, A_PL_CLI, 0);
2732 map = t3_read_reg(adap, A_SG_DATA_INTR);
2733
2734 if (unlikely(!map)) /* shared interrupt, most likely */
2735 return IRQ_NONE;
2736
2737 spin_lock(&q0->lock);
2738
2739 if (unlikely(map & F_ERRINTR))
2740 t3_slow_intr_handler(adap);
2741
2742 if (likely(map & 1))
2743 process_responses_gts(adap, q0);
2744
2745 if (map & 2)
2746 process_responses_gts(adap, &adap->sge.qs[1].rspq);
2747
2748 spin_unlock(&q0->lock);
2749 return IRQ_HANDLED;
2750}
2751
2752/*
2753 * NAPI interrupt handler for legacy INTx interrupts for T3B-based cards.
2754 * Handles data events from SGE response queues as well as error and other
2755 * async events as they all use the same interrupt pin. We use one SGE
2756 * response queue per port in this mode and protect all response queues with
2757 * queue 0's lock.
2758 */
2759static irqreturn_t t3b_intr_napi(int irq, void *cookie)
2760{
2761 u32 map;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002762 struct adapter *adap = cookie;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002763 struct sge_qset *qs0 = &adap->sge.qs[0];
2764 struct sge_rspq *q0 = &qs0->rspq;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002765
2766 t3_write_reg(adap, A_PL_CLI, 0);
2767 map = t3_read_reg(adap, A_SG_DATA_INTR);
2768
2769 if (unlikely(!map)) /* shared interrupt, most likely */
2770 return IRQ_NONE;
2771
2772 spin_lock(&q0->lock);
2773
2774 if (unlikely(map & F_ERRINTR))
2775 t3_slow_intr_handler(adap);
2776
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002777 if (likely(map & 1))
2778 napi_schedule(&qs0->napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002779
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002780 if (map & 2)
2781 napi_schedule(&adap->sge.qs[1].napi);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002782
2783 spin_unlock(&q0->lock);
2784 return IRQ_HANDLED;
2785}
2786
2787/**
2788 * t3_intr_handler - select the top-level interrupt handler
2789 * @adap: the adapter
2790 * @polling: whether using NAPI to service response queues
2791 *
2792 * Selects the top-level interrupt handler based on the type of interrupts
2793 * (MSI-X, MSI, or legacy) and whether NAPI will be used to service the
2794 * response queues.
2795 */
Jeff Garzik7c239972007-10-19 03:12:20 -04002796irq_handler_t t3_intr_handler(struct adapter *adap, int polling)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002797{
2798 if (adap->flags & USING_MSIX)
2799 return polling ? t3_sge_intr_msix_napi : t3_sge_intr_msix;
2800 if (adap->flags & USING_MSI)
2801 return polling ? t3_intr_msi_napi : t3_intr_msi;
2802 if (adap->params.rev > 0)
2803 return polling ? t3b_intr_napi : t3b_intr;
2804 return t3_intr;
2805}
2806
Divy Le Rayb8819552007-12-17 18:47:31 -08002807#define SGE_PARERR (F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
2808 F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
2809 V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
2810 F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
2811 F_HIRCQPARITYERROR)
2812#define SGE_FRAMINGERR (F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR)
2813#define SGE_FATALERR (SGE_PARERR | SGE_FRAMINGERR | F_RSPQCREDITOVERFOW | \
2814 F_RSPQDISABLED)
2815
Divy Le Ray4d22de32007-01-18 22:04:14 -05002816/**
2817 * t3_sge_err_intr_handler - SGE async event interrupt handler
2818 * @adapter: the adapter
2819 *
2820 * Interrupt handler for SGE asynchronous (non-data) events.
2821 */
2822void t3_sge_err_intr_handler(struct adapter *adapter)
2823{
Divy Le Rayfc882192009-03-12 21:14:09 +00002824 unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE) &
2825 ~F_FLEMPTY;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002826
Divy Le Rayb8819552007-12-17 18:47:31 -08002827 if (status & SGE_PARERR)
2828 CH_ALERT(adapter, "SGE parity error (0x%x)\n",
2829 status & SGE_PARERR);
2830 if (status & SGE_FRAMINGERR)
2831 CH_ALERT(adapter, "SGE framing error (0x%x)\n",
2832 status & SGE_FRAMINGERR);
2833
Divy Le Ray4d22de32007-01-18 22:04:14 -05002834 if (status & F_RSPQCREDITOVERFOW)
2835 CH_ALERT(adapter, "SGE response queue credit overflow\n");
2836
2837 if (status & F_RSPQDISABLED) {
2838 v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS);
2839
2840 CH_ALERT(adapter,
2841 "packet delivered to disabled response queue "
2842 "(0x%x)\n", (v >> S_RSPQ0DISABLED) & 0xff);
2843 }
2844
Divy Le Ray6e3f03b2007-08-21 20:49:10 -07002845 if (status & (F_HIPIODRBDROPERR | F_LOPIODRBDROPERR))
Steve Wisee998f242010-01-27 17:03:34 +00002846 queue_work(cxgb3_wq, &adapter->db_drop_task);
2847
2848 if (status & (F_HIPRIORITYDBFULL | F_LOPRIORITYDBFULL))
2849 queue_work(cxgb3_wq, &adapter->db_full_task);
2850
2851 if (status & (F_HIPRIORITYDBEMPTY | F_LOPRIORITYDBEMPTY))
2852 queue_work(cxgb3_wq, &adapter->db_empty_task);
Divy Le Ray6e3f03b2007-08-21 20:49:10 -07002853
Divy Le Ray4d22de32007-01-18 22:04:14 -05002854 t3_write_reg(adapter, A_SG_INT_CAUSE, status);
Divy Le Rayb8819552007-12-17 18:47:31 -08002855 if (status & SGE_FATALERR)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002856 t3_fatal_err(adapter);
2857}
2858
2859/**
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002860 * sge_timer_tx - perform periodic maintenance of an SGE qset
Divy Le Ray4d22de32007-01-18 22:04:14 -05002861 * @data: the SGE queue set to maintain
2862 *
2863 * Runs periodically from a timer to perform maintenance of an SGE queue
2864 * set. It performs two tasks:
2865 *
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002866 * Cleans up any completed Tx descriptors that may still be pending.
Divy Le Ray4d22de32007-01-18 22:04:14 -05002867 * Normal descriptor cleanup happens when new packets are added to a Tx
2868 * queue so this timer is relatively infrequent and does any cleanup only
2869 * if the Tx queue has not seen any new packets in a while. We make a
2870 * best effort attempt to reclaim descriptors, in that we don't wait
2871 * around if we cannot get a queue's lock (which most likely is because
2872 * someone else is queueing new packets and so will also handle the clean
2873 * up). Since control queues use immediate data exclusively we don't
2874 * bother cleaning them up here.
2875 *
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002876 */
2877static void sge_timer_tx(unsigned long data)
2878{
2879 struct sge_qset *qs = (struct sge_qset *)data;
2880 struct port_info *pi = netdev_priv(qs->netdev);
2881 struct adapter *adap = pi->adapter;
2882 unsigned int tbd[SGE_TXQ_PER_SET] = {0, 0};
2883 unsigned long next_period;
2884
Divy Le Rayc3a8c5b2009-05-29 12:52:38 +00002885 if (__netif_tx_trylock(qs->tx_q)) {
2886 tbd[TXQ_ETH] = reclaim_completed_tx(adap, &qs->txq[TXQ_ETH],
2887 TX_RECLAIM_TIMER_CHUNK);
2888 __netif_tx_unlock(qs->tx_q);
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002889 }
Divy Le Rayc3a8c5b2009-05-29 12:52:38 +00002890
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002891 if (spin_trylock(&qs->txq[TXQ_OFLD].lock)) {
2892 tbd[TXQ_OFLD] = reclaim_completed_tx(adap, &qs->txq[TXQ_OFLD],
2893 TX_RECLAIM_TIMER_CHUNK);
2894 spin_unlock(&qs->txq[TXQ_OFLD].lock);
2895 }
2896
2897 next_period = TX_RECLAIM_PERIOD >>
Divy Le Rayc3a8c5b2009-05-29 12:52:38 +00002898 (max(tbd[TXQ_ETH], tbd[TXQ_OFLD]) /
2899 TX_RECLAIM_TIMER_CHUNK);
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002900 mod_timer(&qs->tx_reclaim_timer, jiffies + next_period);
2901}
2902
2903/*
2904 * sge_timer_rx - perform periodic maintenance of an SGE qset
2905 * @data: the SGE queue set to maintain
2906 *
2907 * a) Replenishes Rx queues that have run out due to memory shortage.
Divy Le Ray4d22de32007-01-18 22:04:14 -05002908 * Normally new Rx buffers are added when existing ones are consumed but
2909 * when out of memory a queue can become empty. We try to add only a few
2910 * buffers here, the queue will be replenished fully as these new buffers
2911 * are used up if memory shortage has subsided.
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002912 *
2913 * b) Return coalesced response queue credits in case a response queue is
2914 * starved.
2915 *
Divy Le Ray4d22de32007-01-18 22:04:14 -05002916 */
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002917static void sge_timer_rx(unsigned long data)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002918{
2919 spinlock_t *lock;
2920 struct sge_qset *qs = (struct sge_qset *)data;
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002921 struct port_info *pi = netdev_priv(qs->netdev);
2922 struct adapter *adap = pi->adapter;
2923 u32 status;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002924
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002925 lock = adap->params.rev > 0 ?
2926 &qs->rspq.lock : &adap->sge.qs[0].rspq.lock;
Divy Le Raybae73f42007-02-24 16:44:12 -08002927
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002928 if (!spin_trylock_irq(lock))
2929 goto out;
Divy Le Raybae73f42007-02-24 16:44:12 -08002930
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002931 if (napi_is_scheduled(&qs->napi))
2932 goto unlock;
2933
2934 if (adap->params.rev < 4) {
2935 status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS);
2936
2937 if (status & (1 << qs->rspq.cntxt_id)) {
2938 qs->rspq.starved++;
2939 if (qs->rspq.credits) {
2940 qs->rspq.credits--;
2941 refill_rspq(adap, &qs->rspq, 1);
2942 qs->rspq.restarted++;
2943 t3_write_reg(adap, A_SG_RSPQ_FL_STATUS,
2944 1 << qs->rspq.cntxt_id);
Divy Le Raybae73f42007-02-24 16:44:12 -08002945 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05002946 }
Divy Le Ray4d22de32007-01-18 22:04:14 -05002947 }
Divy Le Ray42c8ea12009-03-12 21:14:04 +00002948
2949 if (qs->fl[0].credits < qs->fl[0].size)
2950 __refill_fl(adap, &qs->fl[0]);
2951 if (qs->fl[1].credits < qs->fl[1].size)
2952 __refill_fl(adap, &qs->fl[1]);
2953
2954unlock:
2955 spin_unlock_irq(lock);
2956out:
2957 mod_timer(&qs->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD);
Divy Le Ray4d22de32007-01-18 22:04:14 -05002958}
2959
2960/**
2961 * t3_update_qset_coalesce - update coalescing settings for a queue set
2962 * @qs: the SGE queue set
2963 * @p: new queue set parameters
2964 *
2965 * Update the coalescing settings for an SGE queue set. Nothing is done
2966 * if the queue set is not initialized yet.
2967 */
2968void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p)
2969{
Divy Le Ray4d22de32007-01-18 22:04:14 -05002970 qs->rspq.holdoff_tmr = max(p->coalesce_usecs * 10, 1U);/* can't be 0 */
2971 qs->rspq.polling = p->polling;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002972 qs->napi.poll = p->polling ? napi_rx_handler : ofld_poll;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002973}
2974
2975/**
2976 * t3_sge_alloc_qset - initialize an SGE queue set
2977 * @adapter: the adapter
2978 * @id: the queue set id
2979 * @nports: how many Ethernet ports will be using this queue set
2980 * @irq_vec_idx: the IRQ vector index for response queue interrupts
2981 * @p: configuration parameters for this queue set
2982 * @ntxq: number of Tx queues for the queue set
2983 * @netdev: net device associated with this queue set
Divy Le Ray82ad3322008-12-16 01:09:39 -08002984 * @netdevq: net device TX queue associated with this queue set
Divy Le Ray4d22de32007-01-18 22:04:14 -05002985 *
2986 * Allocate resources and initialize an SGE queue set. A queue set
2987 * comprises a response queue, two Rx free-buffer queues, and up to 3
2988 * Tx queues. The Tx queues are assigned roles in the order Ethernet
2989 * queue, offload queue, and control queue.
2990 */
2991int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
2992 int irq_vec_idx, const struct qset_params *p,
Divy Le Ray82ad3322008-12-16 01:09:39 -08002993 int ntxq, struct net_device *dev,
2994 struct netdev_queue *netdevq)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002995{
Divy Le Rayb1fb1f22008-05-21 18:56:16 -07002996 int i, avail, ret = -ENOMEM;
Divy Le Ray4d22de32007-01-18 22:04:14 -05002997 struct sge_qset *q = &adapter->sge.qs[id];
2998
2999 init_qset_cntxt(q, id);
Divy Le Ray42c8ea12009-03-12 21:14:04 +00003000 setup_timer(&q->tx_reclaim_timer, sge_timer_tx, (unsigned long)q);
3001 setup_timer(&q->rx_reclaim_timer, sge_timer_rx, (unsigned long)q);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003002
3003 q->fl[0].desc = alloc_ring(adapter->pdev, p->fl_size,
3004 sizeof(struct rx_desc),
3005 sizeof(struct rx_sw_desc),
3006 &q->fl[0].phys_addr, &q->fl[0].sdesc);
3007 if (!q->fl[0].desc)
3008 goto err;
3009
3010 q->fl[1].desc = alloc_ring(adapter->pdev, p->jumbo_size,
3011 sizeof(struct rx_desc),
3012 sizeof(struct rx_sw_desc),
3013 &q->fl[1].phys_addr, &q->fl[1].sdesc);
3014 if (!q->fl[1].desc)
3015 goto err;
3016
3017 q->rspq.desc = alloc_ring(adapter->pdev, p->rspq_size,
3018 sizeof(struct rsp_desc), 0,
3019 &q->rspq.phys_addr, NULL);
3020 if (!q->rspq.desc)
3021 goto err;
3022
3023 for (i = 0; i < ntxq; ++i) {
3024 /*
3025 * The control queue always uses immediate data so does not
3026 * need to keep track of any sk_buffs.
3027 */
3028 size_t sz = i == TXQ_CTRL ? 0 : sizeof(struct tx_sw_desc);
3029
3030 q->txq[i].desc = alloc_ring(adapter->pdev, p->txq_size[i],
3031 sizeof(struct tx_desc), sz,
3032 &q->txq[i].phys_addr,
3033 &q->txq[i].sdesc);
3034 if (!q->txq[i].desc)
3035 goto err;
3036
3037 q->txq[i].gen = 1;
3038 q->txq[i].size = p->txq_size[i];
3039 spin_lock_init(&q->txq[i].lock);
3040 skb_queue_head_init(&q->txq[i].sendq);
3041 }
3042
3043 tasklet_init(&q->txq[TXQ_OFLD].qresume_tsk, restart_offloadq,
3044 (unsigned long)q);
3045 tasklet_init(&q->txq[TXQ_CTRL].qresume_tsk, restart_ctrlq,
3046 (unsigned long)q);
3047
3048 q->fl[0].gen = q->fl[1].gen = 1;
3049 q->fl[0].size = p->fl_size;
3050 q->fl[1].size = p->jumbo_size;
3051
3052 q->rspq.gen = 1;
3053 q->rspq.size = p->rspq_size;
3054 spin_lock_init(&q->rspq.lock);
David S. Miller147e70e2008-09-22 01:29:52 -07003055 skb_queue_head_init(&q->rspq.rx_queue);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003056
3057 q->txq[TXQ_ETH].stop_thres = nports *
3058 flits_to_desc(sgl_len(MAX_SKB_FRAGS + 1) + 3);
3059
Divy Le Raycf992af2007-05-30 21:10:47 -07003060#if FL0_PG_CHUNK_SIZE > 0
3061 q->fl[0].buf_size = FL0_PG_CHUNK_SIZE;
Divy Le Raye0994eb2007-02-24 16:44:17 -08003062#else
Divy Le Raycf992af2007-05-30 21:10:47 -07003063 q->fl[0].buf_size = SGE_RX_SM_BUF_SIZE + sizeof(struct cpl_rx_data);
Divy Le Raye0994eb2007-02-24 16:44:17 -08003064#endif
Divy Le Ray7385ecf2008-05-21 18:56:21 -07003065#if FL1_PG_CHUNK_SIZE > 0
3066 q->fl[1].buf_size = FL1_PG_CHUNK_SIZE;
3067#else
Divy Le Raycf992af2007-05-30 21:10:47 -07003068 q->fl[1].buf_size = is_offload(adapter) ?
3069 (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
3070 MAX_FRAME_SIZE + 2 + sizeof(struct cpl_rx_pkt);
Divy Le Ray7385ecf2008-05-21 18:56:21 -07003071#endif
3072
3073 q->fl[0].use_pages = FL0_PG_CHUNK_SIZE > 0;
3074 q->fl[1].use_pages = FL1_PG_CHUNK_SIZE > 0;
3075 q->fl[0].order = FL0_PG_ORDER;
3076 q->fl[1].order = FL1_PG_ORDER;
Divy Le Ray5e68b772009-03-26 16:39:29 +00003077 q->fl[0].alloc_size = FL0_PG_ALLOC_SIZE;
3078 q->fl[1].alloc_size = FL1_PG_ALLOC_SIZE;
Divy Le Ray4d22de32007-01-18 22:04:14 -05003079
Roland Dreierb1186de2008-03-20 13:30:48 -07003080 spin_lock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003081
3082 /* FL threshold comparison uses < */
3083 ret = t3_sge_init_rspcntxt(adapter, q->rspq.cntxt_id, irq_vec_idx,
3084 q->rspq.phys_addr, q->rspq.size,
Divy Le Ray5e68b772009-03-26 16:39:29 +00003085 q->fl[0].buf_size - SGE_PG_RSVD, 1, 0);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003086 if (ret)
3087 goto err_unlock;
3088
3089 for (i = 0; i < SGE_RXQ_PER_SET; ++i) {
3090 ret = t3_sge_init_flcntxt(adapter, q->fl[i].cntxt_id, 0,
3091 q->fl[i].phys_addr, q->fl[i].size,
Divy Le Ray5e68b772009-03-26 16:39:29 +00003092 q->fl[i].buf_size - SGE_PG_RSVD,
3093 p->cong_thres, 1, 0);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003094 if (ret)
3095 goto err_unlock;
3096 }
3097
3098 ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_ETH].cntxt_id, USE_GTS,
3099 SGE_CNTXT_ETH, id, q->txq[TXQ_ETH].phys_addr,
3100 q->txq[TXQ_ETH].size, q->txq[TXQ_ETH].token,
3101 1, 0);
3102 if (ret)
3103 goto err_unlock;
3104
3105 if (ntxq > 1) {
3106 ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_OFLD].cntxt_id,
3107 USE_GTS, SGE_CNTXT_OFLD, id,
3108 q->txq[TXQ_OFLD].phys_addr,
3109 q->txq[TXQ_OFLD].size, 0, 1, 0);
3110 if (ret)
3111 goto err_unlock;
3112 }
3113
3114 if (ntxq > 2) {
3115 ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_CTRL].cntxt_id, 0,
3116 SGE_CNTXT_CTRL, id,
3117 q->txq[TXQ_CTRL].phys_addr,
3118 q->txq[TXQ_CTRL].size,
3119 q->txq[TXQ_CTRL].token, 1, 0);
3120 if (ret)
3121 goto err_unlock;
3122 }
3123
Roland Dreierb1186de2008-03-20 13:30:48 -07003124 spin_unlock_irq(&adapter->sge.reg_lock);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003125
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003126 q->adap = adapter;
3127 q->netdev = dev;
Divy Le Ray82ad3322008-12-16 01:09:39 -08003128 q->tx_q = netdevq;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003129 t3_update_qset_coalesce(q, p);
Divy Le Rayb47385b2008-05-21 18:56:26 -07003130
Divy Le Ray7385ecf2008-05-21 18:56:21 -07003131 avail = refill_fl(adapter, &q->fl[0], q->fl[0].size,
3132 GFP_KERNEL | __GFP_COMP);
Divy Le Rayb1fb1f22008-05-21 18:56:16 -07003133 if (!avail) {
3134 CH_ALERT(adapter, "free list queue 0 initialization failed\n");
3135 goto err;
3136 }
3137 if (avail < q->fl[0].size)
3138 CH_WARN(adapter, "free list queue 0 enabled with %d credits\n",
3139 avail);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003140
Divy Le Ray7385ecf2008-05-21 18:56:21 -07003141 avail = refill_fl(adapter, &q->fl[1], q->fl[1].size,
3142 GFP_KERNEL | __GFP_COMP);
Divy Le Rayb1fb1f22008-05-21 18:56:16 -07003143 if (avail < q->fl[1].size)
3144 CH_WARN(adapter, "free list queue 1 enabled with %d credits\n",
3145 avail);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003146 refill_rspq(adapter, &q->rspq, q->rspq.size - 1);
3147
3148 t3_write_reg(adapter, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) |
3149 V_NEWTIMER(q->rspq.holdoff_tmr));
3150
Divy Le Ray4d22de32007-01-18 22:04:14 -05003151 return 0;
3152
Divy Le Rayb1fb1f22008-05-21 18:56:16 -07003153err_unlock:
Roland Dreierb1186de2008-03-20 13:30:48 -07003154 spin_unlock_irq(&adapter->sge.reg_lock);
Divy Le Rayb1fb1f22008-05-21 18:56:16 -07003155err:
Divy Le Ray4d22de32007-01-18 22:04:14 -05003156 t3_free_qset(adapter, q);
3157 return ret;
3158}
3159
3160/**
Divy Le Ray31563782009-03-26 16:39:09 +00003161 * t3_start_sge_timers - start SGE timer call backs
3162 * @adap: the adapter
3163 *
3164 * Starts each SGE queue set's timer call back
3165 */
3166void t3_start_sge_timers(struct adapter *adap)
3167{
3168 int i;
3169
3170 for (i = 0; i < SGE_QSETS; ++i) {
3171 struct sge_qset *q = &adap->sge.qs[i];
3172
3173 if (q->tx_reclaim_timer.function)
3174 mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
3175
3176 if (q->rx_reclaim_timer.function)
3177 mod_timer(&q->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD);
3178 }
3179}
3180
3181/**
Divy Le Ray0ca41c02008-09-25 14:05:28 +00003182 * t3_stop_sge_timers - stop SGE timer call backs
3183 * @adap: the adapter
3184 *
3185 * Stops each SGE queue set's timer call back
3186 */
3187void t3_stop_sge_timers(struct adapter *adap)
3188{
3189 int i;
3190
3191 for (i = 0; i < SGE_QSETS; ++i) {
3192 struct sge_qset *q = &adap->sge.qs[i];
3193
3194 if (q->tx_reclaim_timer.function)
3195 del_timer_sync(&q->tx_reclaim_timer);
Divy Le Ray42c8ea12009-03-12 21:14:04 +00003196 if (q->rx_reclaim_timer.function)
3197 del_timer_sync(&q->rx_reclaim_timer);
Divy Le Ray0ca41c02008-09-25 14:05:28 +00003198 }
3199}
3200
3201/**
Divy Le Ray4d22de32007-01-18 22:04:14 -05003202 * t3_free_sge_resources - free SGE resources
3203 * @adap: the adapter
3204 *
3205 * Frees resources used by the SGE queue sets.
3206 */
3207void t3_free_sge_resources(struct adapter *adap)
3208{
3209 int i;
3210
3211 for (i = 0; i < SGE_QSETS; ++i)
3212 t3_free_qset(adap, &adap->sge.qs[i]);
3213}
3214
3215/**
3216 * t3_sge_start - enable SGE
3217 * @adap: the adapter
3218 *
3219 * Enables the SGE for DMAs. This is the last step in starting packet
3220 * transfers.
3221 */
3222void t3_sge_start(struct adapter *adap)
3223{
3224 t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, F_GLOBALENABLE);
3225}
3226
3227/**
3228 * t3_sge_stop - disable SGE operation
3229 * @adap: the adapter
3230 *
3231 * Disables the DMA engine. This can be called in emeregencies (e.g.,
3232 * from error interrupts) or from normal process context. In the latter
3233 * case it also disables any pending queue restart tasklets. Note that
3234 * if it is called in interrupt context it cannot disable the restart
3235 * tasklets as it cannot wait, however the tasklets will have no effect
3236 * since the doorbells are disabled and the driver will call this again
3237 * later from process context, at which time the tasklets will be stopped
3238 * if they are still running.
3239 */
3240void t3_sge_stop(struct adapter *adap)
3241{
3242 t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, 0);
3243 if (!in_interrupt()) {
3244 int i;
3245
3246 for (i = 0; i < SGE_QSETS; ++i) {
3247 struct sge_qset *qs = &adap->sge.qs[i];
3248
3249 tasklet_kill(&qs->txq[TXQ_OFLD].qresume_tsk);
3250 tasklet_kill(&qs->txq[TXQ_CTRL].qresume_tsk);
3251 }
3252 }
3253}
3254
3255/**
3256 * t3_sge_init - initialize SGE
3257 * @adap: the adapter
3258 * @p: the SGE parameters
3259 *
3260 * Performs SGE initialization needed every time after a chip reset.
3261 * We do not initialize any of the queue sets here, instead the driver
3262 * top-level must request those individually. We also do not enable DMA
3263 * here, that should be done after the queues have been set up.
3264 */
3265void t3_sge_init(struct adapter *adap, struct sge_params *p)
3266{
3267 unsigned int ctrl, ups = ffs(pci_resource_len(adap->pdev, 2) >> 12);
3268
3269 ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |
Divy Le Rayb8819552007-12-17 18:47:31 -08003270 F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN |
Divy Le Ray4d22de32007-01-18 22:04:14 -05003271 V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS |
3272 V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING;
3273#if SGE_NUM_GENBITS == 1
3274 ctrl |= F_EGRGENCTRL;
3275#endif
3276 if (adap->params.rev > 0) {
3277 if (!(adap->flags & (USING_MSIX | USING_MSI)))
3278 ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;
Divy Le Ray4d22de32007-01-18 22:04:14 -05003279 }
3280 t3_write_reg(adap, A_SG_CONTROL, ctrl);
3281 t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) |
3282 V_LORCQDRBTHRSH(512));
3283 t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10);
3284 t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) |
Divy Le Ray6195c712007-01-30 19:43:56 -08003285 V_TIMEOUT(200 * core_ticks_per_usec(adap)));
Divy Le Rayb8819552007-12-17 18:47:31 -08003286 t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH,
3287 adap->params.rev < T3_REV_C ? 1000 : 500);
Divy Le Ray4d22de32007-01-18 22:04:14 -05003288 t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256);
3289 t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000);
3290 t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256);
3291 t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff));
3292 t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024);
3293}
3294
3295/**
3296 * t3_sge_prep - one-time SGE initialization
3297 * @adap: the associated adapter
3298 * @p: SGE parameters
3299 *
3300 * Performs one-time initialization of SGE SW state. Includes determining
3301 * defaults for the assorted SGE parameters, which admins can change until
3302 * they are used to initialize the SGE.
3303 */
Roland Dreier7b9b0942008-01-29 14:45:11 -08003304void t3_sge_prep(struct adapter *adap, struct sge_params *p)
Divy Le Ray4d22de32007-01-18 22:04:14 -05003305{
3306 int i;
3307
3308 p->max_pkt_size = (16 * 1024) - sizeof(struct cpl_rx_data) -
3309 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3310
3311 for (i = 0; i < SGE_QSETS; ++i) {
3312 struct qset_params *q = p->qset + i;
3313
3314 q->polling = adap->params.rev > 0;
3315 q->coalesce_usecs = 5;
3316 q->rspq_size = 1024;
Divy Le Raye0994eb2007-02-24 16:44:17 -08003317 q->fl_size = 1024;
Divy Le Ray7385ecf2008-05-21 18:56:21 -07003318 q->jumbo_size = 512;
Divy Le Ray4d22de32007-01-18 22:04:14 -05003319 q->txq_size[TXQ_ETH] = 1024;
3320 q->txq_size[TXQ_OFLD] = 1024;
3321 q->txq_size[TXQ_CTRL] = 256;
3322 q->cong_thres = 0;
3323 }
3324
3325 spin_lock_init(&adap->sge.reg_lock);
3326}