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Bruce Allanfe2ddfb52011-12-21 09:47:10 +00001/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
Bruce Allanf5e261e2012-01-01 16:00:03 +00004 Copyright(c) 1999 - 2012 Intel Corporation.
Bruce Allanfe2ddfb52011-12-21 09:47:10 +00005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31enum e1000_mng_mode {
32 e1000_mng_mode_none = 0,
33 e1000_mng_mode_asf,
34 e1000_mng_mode_pt,
35 e1000_mng_mode_ipmi,
36 e1000_mng_mode_host_if_only
37};
38
39#define E1000_FACTPS_MNGCG 0x20000000
40
41/* Intel(R) Active Management Technology signature */
42#define E1000_IAMT_SIGNATURE 0x544D4149
43
44/**
45 * e1000_calculate_checksum - Calculate checksum for buffer
46 * @buffer: pointer to EEPROM
47 * @length: size of EEPROM to calculate a checksum for
48 *
49 * Calculates the checksum for some buffer on a specified length. The
50 * checksum calculated is returned.
51 **/
52static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
53{
54 u32 i;
55 u8 sum = 0;
56
57 if (!buffer)
58 return 0;
59
60 for (i = 0; i < length; i++)
61 sum += buffer[i];
62
63 return (u8)(0 - sum);
64}
65
66/**
67 * e1000_mng_enable_host_if - Checks host interface is enabled
68 * @hw: pointer to the HW structure
69 *
70 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
71 *
72 * This function checks whether the HOST IF is enabled for command operation
73 * and also checks whether the previous command is completed. It busy waits
74 * in case of previous command is not completed.
75 **/
76static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
77{
78 u32 hicr;
79 u8 i;
80
Bruce Allan668018d2012-01-31 07:02:56 +000081 if (!hw->mac.arc_subsystem_valid) {
Bruce Allanfe2ddfb52011-12-21 09:47:10 +000082 e_dbg("ARC subsystem not valid.\n");
83 return -E1000_ERR_HOST_INTERFACE_COMMAND;
84 }
85
86 /* Check that the host interface is enabled. */
87 hicr = er32(HICR);
Bruce Allan04499ec2012-04-13 00:08:31 +000088 if (!(hicr & E1000_HICR_EN)) {
Bruce Allanfe2ddfb52011-12-21 09:47:10 +000089 e_dbg("E1000_HOST_EN bit disabled.\n");
90 return -E1000_ERR_HOST_INTERFACE_COMMAND;
91 }
92 /* check the previous command is completed */
93 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
94 hicr = er32(HICR);
95 if (!(hicr & E1000_HICR_C))
96 break;
97 mdelay(1);
98 }
99
100 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
101 e_dbg("Previous command timeout failed .\n");
102 return -E1000_ERR_HOST_INTERFACE_COMMAND;
103 }
104
105 return 0;
106}
107
108/**
Bruce Allan48768322012-02-22 09:02:32 +0000109 * e1000e_check_mng_mode_generic - Generic check management mode
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000110 * @hw: pointer to the HW structure
111 *
112 * Reads the firmware semaphore register and returns true (>0) if
113 * manageability is enabled, else false (0).
114 **/
115bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
116{
117 u32 fwsm = er32(FWSM);
118
119 return (fwsm & E1000_FWSM_MODE_MASK) ==
120 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
121}
122
123/**
124 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
125 * @hw: pointer to the HW structure
126 *
127 * Enables packet filtering on transmit packets if manageability is enabled
128 * and host interface is enabled.
129 **/
130bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
131{
132 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
133 u32 *buffer = (u32 *)&hw->mng_cookie;
134 u32 offset;
135 s32 ret_val, hdr_csum, csum;
136 u8 i, len;
137
138 hw->mac.tx_pkt_filtering = true;
139
140 /* No manageability, no filtering */
Bruce Allan48768322012-02-22 09:02:32 +0000141 if (!hw->mac.ops.check_mng_mode(hw)) {
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000142 hw->mac.tx_pkt_filtering = false;
Bruce Allan5015e532012-02-08 02:55:56 +0000143 return hw->mac.tx_pkt_filtering;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000144 }
145
Bruce Allane921eb12012-11-28 09:28:37 +0000146 /* If we can't read from the host interface for whatever
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000147 * reason, disable filtering.
148 */
149 ret_val = e1000_mng_enable_host_if(hw);
150 if (ret_val) {
151 hw->mac.tx_pkt_filtering = false;
Bruce Allan5015e532012-02-08 02:55:56 +0000152 return hw->mac.tx_pkt_filtering;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000153 }
154
155 /* Read in the header. Length and offset are in dwords. */
156 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
157 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
158 for (i = 0; i < len; i++)
159 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF,
160 offset + i);
161 hdr_csum = hdr->checksum;
162 hdr->checksum = 0;
163 csum = e1000_calculate_checksum((u8 *)hdr,
164 E1000_MNG_DHCP_COOKIE_LENGTH);
Bruce Allane921eb12012-11-28 09:28:37 +0000165 /* If either the checksums or signature don't match, then
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000166 * the cookie area isn't considered valid, in which case we
167 * take the safe route of assuming Tx filtering is enabled.
168 */
169 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
170 hw->mac.tx_pkt_filtering = true;
Bruce Allan5015e532012-02-08 02:55:56 +0000171 return hw->mac.tx_pkt_filtering;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000172 }
173
174 /* Cookie area is valid, make the final check for filtering. */
Bruce Allan5015e532012-02-08 02:55:56 +0000175 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000176 hw->mac.tx_pkt_filtering = false;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000177
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000178 return hw->mac.tx_pkt_filtering;
179}
180
181/**
182 * e1000_mng_write_cmd_header - Writes manageability command header
183 * @hw: pointer to the HW structure
184 * @hdr: pointer to the host interface command header
185 *
186 * Writes the command header after does the checksum calculation.
187 **/
188static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
189 struct e1000_host_mng_command_header *hdr)
190{
191 u16 i, length = sizeof(struct e1000_host_mng_command_header);
192
193 /* Write the whole command header structure with new checksum. */
194
195 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
196
197 length >>= 2;
198 /* Write the relevant command block into the ram area. */
199 for (i = 0; i < length; i++) {
200 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i));
201 e1e_flush();
202 }
203
204 return 0;
205}
206
207/**
208 * e1000_mng_host_if_write - Write to the manageability host interface
209 * @hw: pointer to the HW structure
210 * @buffer: pointer to the host interface buffer
211 * @length: size of the buffer
212 * @offset: location in the buffer to write to
213 * @sum: sum of the data (not checksum)
214 *
215 * This function writes the buffer content at the offset given on the host if.
216 * It also does alignment considerations to do the writes in most efficient
217 * way. Also fills up the sum of the buffer in *buffer parameter.
218 **/
219static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
220 u16 length, u16 offset, u8 *sum)
221{
222 u8 *tmp;
223 u8 *bufptr = buffer;
224 u32 data = 0;
225 u16 remaining, i, j, prev_bytes;
226
227 /* sum = only sum of the data and it is not checksum */
228
229 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
230 return -E1000_ERR_PARAM;
231
232 tmp = (u8 *)&data;
233 prev_bytes = offset & 0x3;
234 offset >>= 2;
235
236 if (prev_bytes) {
237 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
238 for (j = prev_bytes; j < sizeof(u32); j++) {
239 *(tmp + j) = *bufptr++;
240 *sum += *(tmp + j);
241 }
242 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
243 length -= j - prev_bytes;
244 offset++;
245 }
246
247 remaining = length & 0x3;
248 length -= remaining;
249
250 /* Calculate length in DWORDs */
251 length >>= 2;
252
Bruce Allane921eb12012-11-28 09:28:37 +0000253 /* The device driver writes the relevant command block into the
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000254 * ram area.
255 */
256 for (i = 0; i < length; i++) {
257 for (j = 0; j < sizeof(u32); j++) {
258 *(tmp + j) = *bufptr++;
259 *sum += *(tmp + j);
260 }
261
262 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
263 }
264 if (remaining) {
265 for (j = 0; j < sizeof(u32); j++) {
266 if (j < remaining)
267 *(tmp + j) = *bufptr++;
268 else
269 *(tmp + j) = 0;
270
271 *sum += *(tmp + j);
272 }
273 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
274 }
275
276 return 0;
277}
278
279/**
280 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
281 * @hw: pointer to the HW structure
282 * @buffer: pointer to the host interface
283 * @length: size of the buffer
284 *
285 * Writes the DHCP information to the host interface.
286 **/
287s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
288{
289 struct e1000_host_mng_command_header hdr;
290 s32 ret_val;
291 u32 hicr;
292
293 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
294 hdr.command_length = length;
295 hdr.reserved1 = 0;
296 hdr.reserved2 = 0;
297 hdr.checksum = 0;
298
299 /* Enable the host interface */
300 ret_val = e1000_mng_enable_host_if(hw);
301 if (ret_val)
302 return ret_val;
303
304 /* Populate the host interface with the contents of "buffer". */
305 ret_val = e1000_mng_host_if_write(hw, buffer, length,
306 sizeof(hdr), &(hdr.checksum));
307 if (ret_val)
308 return ret_val;
309
310 /* Write the manageability command header */
311 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
312 if (ret_val)
313 return ret_val;
314
315 /* Tell the ARC a new command is pending. */
316 hicr = er32(HICR);
317 ew32(HICR, hicr | E1000_HICR_C);
318
319 return 0;
320}
321
322/**
323 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
324 * @hw: pointer to the HW structure
325 *
326 * Verifies the hardware needs to leave interface enabled so that frames can
327 * be directed to and from the management interface.
328 **/
329bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
330{
331 u32 manc;
332 u32 fwsm, factps;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000333
334 manc = er32(MANC);
335
336 if (!(manc & E1000_MANC_RCV_TCO_EN))
Bruce Allan5015e532012-02-08 02:55:56 +0000337 return false;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000338
339 if (hw->mac.has_fwsm) {
340 fwsm = er32(FWSM);
341 factps = er32(FACTPS);
342
343 if (!(factps & E1000_FACTPS_MNGCG) &&
344 ((fwsm & E1000_FWSM_MODE_MASK) ==
Bruce Allan5015e532012-02-08 02:55:56 +0000345 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
346 return true;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000347 } else if ((hw->mac.type == e1000_82574) ||
348 (hw->mac.type == e1000_82583)) {
349 u16 data;
350
351 factps = er32(FACTPS);
352 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
353
354 if (!(factps & E1000_FACTPS_MNGCG) &&
355 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
Bruce Allan5015e532012-02-08 02:55:56 +0000356 (e1000_mng_mode_pt << 13)))
357 return true;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000358 } else if ((manc & E1000_MANC_SMBUS_EN) &&
359 !(manc & E1000_MANC_ASF_EN)) {
Bruce Allan5015e532012-02-08 02:55:56 +0000360 return true;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000361 }
362
Bruce Allan5015e532012-02-08 02:55:56 +0000363 return false;
Bruce Allanfe2ddfb52011-12-21 09:47:10 +0000364}