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gerrit-public.fairphone.software / kernel / msm-5.4 / dd04c17bfa3d9398aaf2bc47eafbacbcc2c6a4ba / . / arch / arm / boot / dts / imx53.dtsi
blob: 81617d801f96cdffc60a3904145475717a23e7d4 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
Philipp Zabelc60dc1d2013-04-09 19:18:47 +0200[diff] [blame]30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]33 };
34
35 tzic: tz-interrupt-controller@0fffc000 {
36 compatible = "fsl,imx53-tzic", "fsl,tzic";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0x0fffc000 0x4000>;
40 };
41
42 clocks {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 ckil {
47 compatible = "fsl,imx-ckil", "fixed-clock";
48 clock-frequency = <32768>;
49 };
50
51 ckih1 {
52 compatible = "fsl,imx-ckih1", "fixed-clock";
53 clock-frequency = <22579200>;
54 };
55
56 ckih2 {
57 compatible = "fsl,imx-ckih2", "fixed-clock";
58 clock-frequency = <0>;
59 };
60
61 osc {
62 compatible = "fsl,imx-osc", "fixed-clock";
63 clock-frequency = <24000000>;
64 };
65 };
66
67 soc {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 interrupt-parent = <&tzic>;
72 ranges;
73
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]74 ipu: ipu@18000000 {
75 #crtc-cells = <1>;
76 compatible = "fsl,imx53-ipu";
77 reg = <0x18000000 0x080000000>;
78 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]79 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
80 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]81 resets = <&src 2>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]82 };
83
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]84 aips@50000000 { /* AIPS1 */
85 compatible = "fsl,aips-bus", "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0x50000000 0x10000000>;
89 ranges;
90
91 spba@50000000 {
92 compatible = "fsl,spba-bus", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0x50000000 0x40000>;
96 ranges;
97
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]98 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]99 compatible = "fsl,imx53-esdhc";
100 reg = <0x50004000 0x4000>;
101 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]102 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
103 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]104 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]105 status = "disabled";
106 };
107
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]108 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]109 compatible = "fsl,imx53-esdhc";
110 reg = <0x50008000 0x4000>;
111 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]112 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
113 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]114 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]115 status = "disabled";
116 };
117
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]118 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]119 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
120 reg = <0x5000c000 0x4000>;
121 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]122 clocks = <&clks 32>, <&clks 33>;
123 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]124 status = "disabled";
125 };
126
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]127 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
131 reg = <0x50010000 0x4000>;
132 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]133 clocks = <&clks 51>, <&clks 52>;
134 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]135 status = "disabled";
136 };
137
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]138 ssi2: ssi@50014000 {
139 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
140 reg = <0x50014000 0x4000>;
141 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]142 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]143 fsl,fifo-depth = <15>;
144 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
145 status = "disabled";
146 };
147
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]148 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]149 compatible = "fsl,imx53-esdhc";
150 reg = <0x50020000 0x4000>;
151 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]152 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
153 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]154 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]155 status = "disabled";
156 };
157
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]158 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]159 compatible = "fsl,imx53-esdhc";
160 reg = <0x50024000 0x4000>;
161 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]162 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
163 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]164 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]165 status = "disabled";
166 };
167 };
168
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]169 usbphy0: usbphy@0 {
170 compatible = "usb-nop-xceiv";
171 clocks = <&clks 124>;
172 clock-names = "main_clk";
173 status = "okay";
174 };
175
176 usbphy1: usbphy@1 {
177 compatible = "usb-nop-xceiv";
178 clocks = <&clks 125>;
179 clock-names = "main_clk";
180 status = "okay";
181 };
182
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]183 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
185 reg = <0x53f80000 0x0200>;
186 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]187 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]188 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]189 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]190 status = "disabled";
191 };
192
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]193 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]194 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
195 reg = <0x53f80200 0x0200>;
196 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]197 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]198 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]199 fsl,usbphy = <&usbphy1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]200 status = "disabled";
201 };
202
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]203 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]204 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
205 reg = <0x53f80400 0x0200>;
206 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]207 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]208 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]209 status = "disabled";
210 };
211
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]212 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]213 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
214 reg = <0x53f80600 0x0200>;
215 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]216 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]217 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]218 status = "disabled";
219 };
220
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]221 usbmisc: usbmisc@53f80800 {
222 #index-cells = <1>;
223 compatible = "fsl,imx53-usbmisc";
224 reg = <0x53f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]225 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]226 };
227
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]228 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]229 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]230 reg = <0x53f84000 0x4000>;
231 interrupts = <50 51>;
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]235 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]236 };
237
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]238 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]239 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]240 reg = <0x53f88000 0x4000>;
241 interrupts = <52 53>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]245 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]246 };
247
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]248 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]249 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]250 reg = <0x53f8c000 0x4000>;
251 interrupts = <54 55>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]255 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]256 };
257
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]258 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]259 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]260 reg = <0x53f90000 0x4000>;
261 interrupts = <56 57>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]265 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]266 };
267
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]268 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]269 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
270 reg = <0x53f98000 0x4000>;
271 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]272 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]273 };
274
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]275 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]276 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
277 reg = <0x53f9c000 0x4000>;
278 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]279 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]280 status = "disabled";
281 };
282
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]283 gpt: timer@53fa0000 {
284 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
285 reg = <0x53fa0000 0x4000>;
286 interrupts = <39>;
287 clocks = <&clks 36>, <&clks 41>;
288 clock-names = "ipg", "per";
289 };
290
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]291 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]292 compatible = "fsl,imx53-iomuxc";
293 reg = <0x53fa8000 0x4000>;
294
295 audmux {
296 pinctrl_audmux_1: audmuxgrp-1 {
297 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]298 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
299 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
300 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
301 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]302 >;
303 };
Marek Vasutdd04c172013-04-21 23:30:01 +0200[diff] [blame^]304
305 pinctrl_audmux_2: audmuxgrp-2 {
306 fsl,pins = <
307 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
308 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
309 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
310 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
311 >;
312 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]313 };
314
315 fec {
316 pinctrl_fec_1: fecgrp-1 {
317 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]318 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
319 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
320 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
321 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
322 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
323 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
324 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
325 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
326 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
327 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]328 >;
329 };
330 };
331
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]332 csi {
333 pinctrl_csi_1: csigrp-1 {
334 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]335 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
336 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
337 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
338 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
339 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
340 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
341 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
342 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
343 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
344 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
345 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
346 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
347 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
348 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
349 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
350 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
351 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
352 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
353 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
354 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
355 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]356 >;
357 };
358 };
359
360 cspi {
361 pinctrl_cspi_1: cspigrp-1 {
362 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]363 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
364 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
365 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]366 >;
367 };
368 };
369
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]370 ecspi1 {
371 pinctrl_ecspi1_1: ecspi1grp-1 {
372 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]373 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
374 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
375 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]376 >;
377 };
378 };
379
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]380 esdhc1 {
381 pinctrl_esdhc1_1: esdhc1grp-1 {
382 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]383 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
384 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
385 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
386 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
387 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
388 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]389 >;
390 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]391
392 pinctrl_esdhc1_2: esdhc1grp-2 {
393 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]394 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
395 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
396 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
397 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
398 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
399 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
400 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
401 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
402 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
403 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]404 >;
405 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]406 };
407
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]408 esdhc2 {
409 pinctrl_esdhc2_1: esdhc2grp-1 {
410 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]411 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
412 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
413 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
414 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
415 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
416 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]417 >;
418 };
419 };
420
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]421 esdhc3 {
422 pinctrl_esdhc3_1: esdhc3grp-1 {
423 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]424 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
425 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
426 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
427 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
428 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
429 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
430 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
431 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
432 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
433 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]434 >;
435 };
436 };
437
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]438 can1 {
439 pinctrl_can1_1: can1grp-1 {
440 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]441 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
442 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]443 >;
444 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]445
446 pinctrl_can1_2: can1grp-2 {
447 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]448 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
449 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]450 >;
451 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]452 };
453
454 can2 {
455 pinctrl_can2_1: can2grp-1 {
456 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]457 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
458 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]459 >;
460 };
461 };
462
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]463 i2c1 {
464 pinctrl_i2c1_1: i2c1grp-1 {
465 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]466 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
467 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]468 >;
469 };
470 };
471
472 i2c2 {
473 pinctrl_i2c2_1: i2c2grp-1 {
474 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]475 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
476 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]477 >;
478 };
479 };
480
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]481 i2c3 {
482 pinctrl_i2c3_1: i2c3grp-1 {
483 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]484 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
485 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]486 >;
487 };
488 };
489
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]490 owire {
491 pinctrl_owire_1: owiregrp-1 {
492 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]493 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]494 >;
495 };
496 };
497
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]498 uart1 {
499 pinctrl_uart1_1: uart1grp-1 {
500 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]501 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
502 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]503 >;
504 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]505
506 pinctrl_uart1_2: uart1grp-2 {
507 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]508 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
509 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]510 >;
511 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]512 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]513
514 uart2 {
515 pinctrl_uart2_1: uart2grp-1 {
516 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]517 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
518 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]519 >;
520 };
521 };
522
523 uart3 {
524 pinctrl_uart3_1: uart3grp-1 {
525 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]526 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
527 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
528 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
529 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]530 >;
531 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]532
533 pinctrl_uart3_2: uart3grp-2 {
534 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]535 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
536 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]537 >;
538 };
539
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]540 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]541
542 uart4 {
543 pinctrl_uart4_1: uart4grp-1 {
544 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]545 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
546 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]547 >;
548 };
549 };
550
551 uart5 {
552 pinctrl_uart5_1: uart5grp-1 {
553 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]554 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
555 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]556 >;
557 };
558 };
559
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]560 };
561
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame]562 gpr: iomuxc-gpr@53fa8000 {
563 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
564 reg = <0x53fa8000 0xc>;
565 };
566
Philipp Zabel420714a2013-03-27 18:30:44 +0100[diff] [blame]567 ldb: ldb@53fa8008 {
568 #address-cells = <1>;
569 #size-cells = <0>;
570 compatible = "fsl,imx53-ldb";
571 reg = <0x53fa8008 0x4>;
572 gpr = <&gpr>;
573 clocks = <&clks 122>, <&clks 120>,
574 <&clks 115>, <&clks 116>,
575 <&clks 123>, <&clks 85>;
576 clock-names = "di0_pll", "di1_pll",
577 "di0_sel", "di1_sel",
578 "di0", "di1";
579 status = "disabled";
580
581 lvds-channel@0 {
582 reg = <0>;
583 crtcs = <&ipu 0>;
584 status = "disabled";
585 };
586
587 lvds-channel@1 {
588 reg = <1>;
589 crtcs = <&ipu 1>;
590 status = "disabled";
591 };
592 };
593
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]594 pwm1: pwm@53fb4000 {
595 #pwm-cells = <2>;
596 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
597 reg = <0x53fb4000 0x4000>;
598 clocks = <&clks 37>, <&clks 38>;
599 clock-names = "ipg", "per";
600 interrupts = <61>;
601 };
602
603 pwm2: pwm@53fb8000 {
604 #pwm-cells = <2>;
605 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
606 reg = <0x53fb8000 0x4000>;
607 clocks = <&clks 39>, <&clks 40>;
608 clock-names = "ipg", "per";
609 interrupts = <94>;
610 };
611
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]612 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]613 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
614 reg = <0x53fbc000 0x4000>;
615 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]616 clocks = <&clks 28>, <&clks 29>;
617 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]618 status = "disabled";
619 };
620
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]621 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]622 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
623 reg = <0x53fc0000 0x4000>;
624 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]625 clocks = <&clks 30>, <&clks 31>;
626 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]627 status = "disabled";
628 };
629
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]630 can1: can@53fc8000 {
631 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
632 reg = <0x53fc8000 0x4000>;
633 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]634 clocks = <&clks 158>, <&clks 157>;
635 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]636 status = "disabled";
637 };
638
639 can2: can@53fcc000 {
640 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
641 reg = <0x53fcc000 0x4000>;
642 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]643 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]644 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]645 status = "disabled";
646 };
647
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]648 src: src@53fd0000 {
649 compatible = "fsl,imx53-src", "fsl,imx51-src";
650 reg = <0x53fd0000 0x4000>;
651 #reset-cells = <1>;
652 };
653
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]654 clks: ccm@53fd4000{
655 compatible = "fsl,imx53-ccm";
656 reg = <0x53fd4000 0x4000>;
657 interrupts = <0 71 0x04 0 72 0x04>;
658 #clock-cells = <1>;
659 };
660
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]661 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]662 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]663 reg = <0x53fdc000 0x4000>;
664 interrupts = <103 104>;
665 gpio-controller;
666 #gpio-cells = <2>;
667 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]668 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]669 };
670
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]671 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]672 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]673 reg = <0x53fe0000 0x4000>;
674 interrupts = <105 106>;
675 gpio-controller;
676 #gpio-cells = <2>;
677 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]678 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]679 };
680
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]681 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]682 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]683 reg = <0x53fe4000 0x4000>;
684 interrupts = <107 108>;
685 gpio-controller;
686 #gpio-cells = <2>;
687 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]688 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]689 };
690
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]691 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]692 #address-cells = <1>;
693 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]694 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]695 reg = <0x53fec000 0x4000>;
696 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]697 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]698 status = "disabled";
699 };
700
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]701 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]702 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
703 reg = <0x53ff0000 0x4000>;
704 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]705 clocks = <&clks 65>, <&clks 66>;
706 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]707 status = "disabled";
708 };
709 };
710
711 aips@60000000 { /* AIPS2 */
712 compatible = "fsl,aips-bus", "simple-bus";
713 #address-cells = <1>;
714 #size-cells = <1>;
715 reg = <0x60000000 0x10000000>;
716 ranges;
717
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]718 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]719 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
720 reg = <0x63f90000 0x4000>;
721 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]722 clocks = <&clks 67>, <&clks 68>;
723 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]724 status = "disabled";
725 };
726
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]727 owire: owire@63fa4000 {
728 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
729 reg = <0x63fa4000 0x4000>;
730 clocks = <&clks 159>;
731 status = "disabled";
732 };
733
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]734 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]735 #address-cells = <1>;
736 #size-cells = <0>;
737 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
738 reg = <0x63fac000 0x4000>;
739 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]740 clocks = <&clks 53>, <&clks 54>;
741 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]742 status = "disabled";
743 };
744
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]745 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]746 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
747 reg = <0x63fb0000 0x4000>;
748 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]749 clocks = <&clks 56>, <&clks 56>;
750 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]751 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]752 };
753
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]754 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]755 #address-cells = <1>;
756 #size-cells = <0>;
757 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
758 reg = <0x63fc0000 0x4000>;
759 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]760 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]761 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]762 status = "disabled";
763 };
764
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]765 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]766 #address-cells = <1>;
767 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]768 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]769 reg = <0x63fc4000 0x4000>;
770 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]771 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]772 status = "disabled";
773 };
774
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]775 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]776 #address-cells = <1>;
777 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]778 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]779 reg = <0x63fc8000 0x4000>;
780 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]781 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]782 status = "disabled";
783 };
784
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]785 ssi1: ssi@63fcc000 {
786 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
787 reg = <0x63fcc000 0x4000>;
788 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]789 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]790 fsl,fifo-depth = <15>;
791 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
792 status = "disabled";
793 };
794
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]795 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]796 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
797 reg = <0x63fd0000 0x4000>;
798 status = "disabled";
799 };
800
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]801 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]802 compatible = "fsl,imx53-nand";
803 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
804 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]805 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]806 status = "disabled";
807 };
808
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]809 ssi3: ssi@63fe8000 {
810 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
811 reg = <0x63fe8000 0x4000>;
812 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]813 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]814 fsl,fifo-depth = <15>;
815 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
816 status = "disabled";
817 };
818
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]819 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]820 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
821 reg = <0x63fec000 0x4000>;
822 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]823 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
824 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]825 status = "disabled";
826 };
827 };
828 };
829};