blob: 91ed5b61a6d90bcb42265ab0dbc36fbaeb5c65b3 [file] [log] [blame]
Paul Zimmerman7359d482013-03-11 17:47:59 -07001/*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/spinlock.h>
44#include <linux/interrupt.h>
Heiner Kallweit348becd2017-01-25 23:10:51 +010045#include <linux/platform_device.h>
Paul Zimmerman7359d482013-03-11 17:47:59 -070046#include <linux/dma-mapping.h>
47#include <linux/delay.h>
48#include <linux/io.h>
49#include <linux/slab.h>
50#include <linux/usb.h>
51
52#include <linux/usb/hcd.h>
53#include <linux/usb/ch11.h>
54
55#include "core.h"
56#include "hcd.h"
57
Chen Yu9156a7e2017-01-23 14:59:57 -080058static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
59
John Younb02038fa2016-02-23 19:55:00 -080060/*
61 * =========================================================================
62 * Host Core Layer Functions
63 * =========================================================================
64 */
65
66/**
67 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
68 * used in both device and host modes
69 *
70 * @hsotg: Programming view of the DWC_otg controller
71 */
72static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
73{
74 u32 intmsk;
75
76 /* Clear any pending OTG Interrupts */
77 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
78
79 /* Clear any pending interrupts */
80 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
81
82 /* Enable the interrupts in the GINTMSK */
83 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
84
John Youn95832c02017-01-23 14:57:26 -080085 if (!hsotg->params.host_dma)
John Younb02038fa2016-02-23 19:55:00 -080086 intmsk |= GINTSTS_RXFLVL;
John Youn95832c02017-01-23 14:57:26 -080087 if (!hsotg->params.external_id_pin_ctl)
John Younb02038fa2016-02-23 19:55:00 -080088 intmsk |= GINTSTS_CONIDSTSCHNG;
89
90 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
91 GINTSTS_SESSREQINT;
92
93 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
94}
95
96/*
97 * Initializes the FSLSPClkSel field of the HCFG register depending on the
98 * PHY type
99 */
100static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
101{
102 u32 hcfg, val;
103
104 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
105 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
John Youn95832c02017-01-23 14:57:26 -0800106 hsotg->params.ulpi_fs_ls) ||
John Younbea8e862016-11-03 17:55:53 -0700107 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
John Younb02038fa2016-02-23 19:55:00 -0800108 /* Full speed PHY */
109 val = HCFG_FSLSPCLKSEL_48_MHZ;
110 } else {
111 /* High speed PHY running at full speed or high speed */
112 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
113 }
114
115 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
116 hcfg = dwc2_readl(hsotg->regs + HCFG);
117 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
118 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
119 dwc2_writel(hcfg, hsotg->regs + HCFG);
120}
121
122static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
123{
124 u32 usbcfg, i2cctl;
125 int retval = 0;
126
127 /*
128 * core_init() is now called on every switch so only call the
129 * following for the first time through
130 */
131 if (select_phy) {
132 dev_dbg(hsotg->dev, "FS PHY selected\n");
133
134 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
135 if (!(usbcfg & GUSBCFG_PHYSEL)) {
136 usbcfg |= GUSBCFG_PHYSEL;
137 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
138
139 /* Reset after a PHY select */
140 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
141
142 if (retval) {
143 dev_err(hsotg->dev,
144 "%s: Reset failed, aborting", __func__);
145 return retval;
146 }
147 }
148 }
149
150 /*
151 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
152 * do this on HNP Dev/Host mode switches (done in dev_init and
153 * host_init).
154 */
155 if (dwc2_is_host_mode(hsotg))
156 dwc2_init_fs_ls_pclk_sel(hsotg);
157
John Youn95832c02017-01-23 14:57:26 -0800158 if (hsotg->params.i2c_enable) {
John Younb02038fa2016-02-23 19:55:00 -0800159 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
160
161 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
162 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
163 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
164 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
165
166 /* Program GI2CCTL.I2CEn */
167 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
168 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
169 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
170 i2cctl &= ~GI2CCTL_I2CEN;
171 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
172 i2cctl |= GI2CCTL_I2CEN;
173 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
174 }
175
176 return retval;
177}
178
179static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
180{
181 u32 usbcfg, usbcfg_old;
182 int retval = 0;
183
184 if (!select_phy)
185 return 0;
186
187 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
188 usbcfg_old = usbcfg;
189
190 /*
191 * HS PHY parameters. These parameters are preserved during soft reset
192 * so only program the first time. Do a soft reset immediately after
193 * setting phyif.
194 */
John Younbea8e862016-11-03 17:55:53 -0700195 switch (hsotg->params.phy_type) {
John Younb02038fa2016-02-23 19:55:00 -0800196 case DWC2_PHY_TYPE_PARAM_ULPI:
197 /* ULPI interface */
198 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
199 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
200 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
John Youn95832c02017-01-23 14:57:26 -0800201 if (hsotg->params.phy_ulpi_ddr)
John Younb02038fa2016-02-23 19:55:00 -0800202 usbcfg |= GUSBCFG_DDRSEL;
203 break;
204 case DWC2_PHY_TYPE_PARAM_UTMI:
205 /* UTMI+ interface */
206 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
207 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
John Younbea8e862016-11-03 17:55:53 -0700208 if (hsotg->params.phy_utmi_width == 16)
John Younb02038fa2016-02-23 19:55:00 -0800209 usbcfg |= GUSBCFG_PHYIF16;
210 break;
211 default:
212 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
213 break;
214 }
215
216 if (usbcfg != usbcfg_old) {
217 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
218
219 /* Reset after setting the PHY parameters */
220 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
221 if (retval) {
222 dev_err(hsotg->dev,
223 "%s: Reset failed, aborting", __func__);
224 return retval;
225 }
226 }
227
228 return retval;
229}
230
231static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
232{
233 u32 usbcfg;
234 int retval = 0;
235
Vardan Mikayelyan38e90022016-11-14 19:17:03 -0800236 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
237 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
John Younbea8e862016-11-03 17:55:53 -0700238 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
Vardan Mikayelyan38e90022016-11-14 19:17:03 -0800239 /* If FS/LS mode with FS/LS PHY */
John Younb02038fa2016-02-23 19:55:00 -0800240 retval = dwc2_fs_phy_init(hsotg, select_phy);
241 if (retval)
242 return retval;
243 } else {
244 /* High speed PHY */
245 retval = dwc2_hs_phy_init(hsotg, select_phy);
246 if (retval)
247 return retval;
248 }
249
250 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
251 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
John Youn95832c02017-01-23 14:57:26 -0800252 hsotg->params.ulpi_fs_ls) {
John Younb02038fa2016-02-23 19:55:00 -0800253 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
254 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
255 usbcfg |= GUSBCFG_ULPI_FS_LS;
256 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
257 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
258 } else {
259 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
260 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
261 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
262 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
263 }
264
265 return retval;
266}
267
268static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
269{
270 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
271
272 switch (hsotg->hw_params.arch) {
273 case GHWCFG2_EXT_DMA_ARCH:
274 dev_err(hsotg->dev, "External DMA Mode not supported\n");
275 return -EINVAL;
276
277 case GHWCFG2_INT_DMA_ARCH:
278 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
John Younbea8e862016-11-03 17:55:53 -0700279 if (hsotg->params.ahbcfg != -1) {
John Younb02038fa2016-02-23 19:55:00 -0800280 ahbcfg &= GAHBCFG_CTRL_MASK;
John Younbea8e862016-11-03 17:55:53 -0700281 ahbcfg |= hsotg->params.ahbcfg &
John Younb02038fa2016-02-23 19:55:00 -0800282 ~GAHBCFG_CTRL_MASK;
283 }
284 break;
285
286 case GHWCFG2_SLAVE_ONLY_ARCH:
287 default:
288 dev_dbg(hsotg->dev, "Slave Only Mode\n");
289 break;
290 }
291
John Youne7839f92016-11-03 17:56:07 -0700292 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n",
293 hsotg->params.host_dma,
John Younbea8e862016-11-03 17:55:53 -0700294 hsotg->params.dma_desc_enable);
John Younb02038fa2016-02-23 19:55:00 -0800295
John Youn95832c02017-01-23 14:57:26 -0800296 if (hsotg->params.host_dma) {
297 if (hsotg->params.dma_desc_enable)
John Younb02038fa2016-02-23 19:55:00 -0800298 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
299 else
300 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
301 } else {
302 dev_dbg(hsotg->dev, "Using Slave mode\n");
John Youn95832c02017-01-23 14:57:26 -0800303 hsotg->params.dma_desc_enable = false;
John Younb02038fa2016-02-23 19:55:00 -0800304 }
305
John Youn95832c02017-01-23 14:57:26 -0800306 if (hsotg->params.host_dma)
John Younb02038fa2016-02-23 19:55:00 -0800307 ahbcfg |= GAHBCFG_DMA_EN;
308
309 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
310
311 return 0;
312}
313
314static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
315{
316 u32 usbcfg;
317
318 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
319 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
320
321 switch (hsotg->hw_params.op_mode) {
322 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
John Younbea8e862016-11-03 17:55:53 -0700323 if (hsotg->params.otg_cap ==
John Younb02038fa2016-02-23 19:55:00 -0800324 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
325 usbcfg |= GUSBCFG_HNPCAP;
John Younbea8e862016-11-03 17:55:53 -0700326 if (hsotg->params.otg_cap !=
John Younb02038fa2016-02-23 19:55:00 -0800327 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
328 usbcfg |= GUSBCFG_SRPCAP;
329 break;
330
331 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
332 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
333 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
John Younbea8e862016-11-03 17:55:53 -0700334 if (hsotg->params.otg_cap !=
John Younb02038fa2016-02-23 19:55:00 -0800335 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
336 usbcfg |= GUSBCFG_SRPCAP;
337 break;
338
339 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
340 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
341 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
342 default:
343 break;
344 }
345
346 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
347}
348
349/**
350 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
351 *
352 * @hsotg: Programming view of DWC_otg controller
353 */
354static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
355{
356 u32 intmsk;
357
358 dev_dbg(hsotg->dev, "%s()\n", __func__);
359
360 /* Disable all interrupts */
361 dwc2_writel(0, hsotg->regs + GINTMSK);
362 dwc2_writel(0, hsotg->regs + HAINTMSK);
363
364 /* Enable the common interrupts */
365 dwc2_enable_common_interrupts(hsotg);
366
367 /* Enable host mode interrupts without disturbing common interrupts */
368 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
369 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
370 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
371}
372
373/**
374 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
375 *
376 * @hsotg: Programming view of DWC_otg controller
377 */
378static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
379{
380 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
381
382 /* Disable host mode interrupts without disturbing common interrupts */
383 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
384 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
385 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
386}
387
388/*
389 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
390 * For system that have a total fifo depth that is smaller than the default
391 * RX + TX fifo size.
392 *
393 * @hsotg: Programming view of DWC_otg controller
394 */
395static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
396{
John Younbea8e862016-11-03 17:55:53 -0700397 struct dwc2_core_params *params = &hsotg->params;
John Younb02038fa2016-02-23 19:55:00 -0800398 struct dwc2_hw_params *hw = &hsotg->hw_params;
399 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
400
401 total_fifo_size = hw->total_fifo_size;
402 rxfsiz = params->host_rx_fifo_size;
403 nptxfsiz = params->host_nperio_tx_fifo_size;
404 ptxfsiz = params->host_perio_tx_fifo_size;
405
406 /*
407 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
408 * allocation with support for high bandwidth endpoints. Synopsys
409 * defines MPS(Max Packet size) for a periodic EP=1024, and for
410 * non-periodic as 512.
411 */
412 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
413 /*
414 * For Buffer DMA mode/Scatter Gather DMA mode
415 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
416 * with n = number of host channel.
417 * 2 * ((1024/4) + 2) = 516
418 */
419 rxfsiz = 516 + hw->host_channels;
420
421 /*
422 * min non-periodic tx fifo depth
423 * 2 * (largest non-periodic USB packet used / 4)
424 * 2 * (512/4) = 256
425 */
426 nptxfsiz = 256;
427
428 /*
429 * min periodic tx fifo depth
430 * (largest packet size*MC)/4
431 * (1024 * 3)/4 = 768
432 */
433 ptxfsiz = 768;
434
435 params->host_rx_fifo_size = rxfsiz;
436 params->host_nperio_tx_fifo_size = nptxfsiz;
437 params->host_perio_tx_fifo_size = ptxfsiz;
438 }
439
440 /*
441 * If the summation of RX, NPTX and PTX fifo sizes is still
442 * bigger than the total_fifo_size, then we have a problem.
443 *
444 * We won't be able to allocate as many endpoints. Right now,
445 * we're just printing an error message, but ideally this FIFO
446 * allocation algorithm would be improved in the future.
447 *
448 * FIXME improve this FIFO allocation algorithm.
449 */
450 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
451 dev_err(hsotg->dev, "invalid fifo sizes\n");
452}
453
454static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
455{
John Younbea8e862016-11-03 17:55:53 -0700456 struct dwc2_core_params *params = &hsotg->params;
John Younb02038fa2016-02-23 19:55:00 -0800457 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
458
459 if (!params->enable_dynamic_fifo)
460 return;
461
462 dwc2_calculate_dynamic_fifo(hsotg);
463
464 /* Rx FIFO */
465 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
466 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
467 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
468 grxfsiz |= params->host_rx_fifo_size <<
469 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
470 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
471 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
472 dwc2_readl(hsotg->regs + GRXFSIZ));
473
474 /* Non-periodic Tx FIFO */
475 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
476 dwc2_readl(hsotg->regs + GNPTXFSIZ));
477 nptxfsiz = params->host_nperio_tx_fifo_size <<
478 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
479 nptxfsiz |= params->host_rx_fifo_size <<
480 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
481 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
482 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
483 dwc2_readl(hsotg->regs + GNPTXFSIZ));
484
485 /* Periodic Tx FIFO */
486 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
487 dwc2_readl(hsotg->regs + HPTXFSIZ));
488 hptxfsiz = params->host_perio_tx_fifo_size <<
489 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
490 hptxfsiz |= (params->host_rx_fifo_size +
491 params->host_nperio_tx_fifo_size) <<
492 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
493 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
494 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
495 dwc2_readl(hsotg->regs + HPTXFSIZ));
496
John Youn95832c02017-01-23 14:57:26 -0800497 if (hsotg->params.en_multiple_tx_fifo &&
Sevak Arakelyane1f411d2017-01-23 15:01:01 -0800498 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
John Younb02038fa2016-02-23 19:55:00 -0800499 /*
Sevak Arakelyane1f411d2017-01-23 15:01:01 -0800500 * This feature was implemented in 2.91a version
John Younb02038fa2016-02-23 19:55:00 -0800501 * Global DFIFOCFG calculation for Host mode -
502 * include RxFIFO, NPTXFIFO and HPTXFIFO
503 */
504 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
505 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
506 dfifocfg |= (params->host_rx_fifo_size +
507 params->host_nperio_tx_fifo_size +
508 params->host_perio_tx_fifo_size) <<
509 GDFIFOCFG_EPINFOBASE_SHIFT &
510 GDFIFOCFG_EPINFOBASE_MASK;
511 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
512 }
513}
514
515/**
516 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
517 * the HFIR register according to PHY type and speed
518 *
519 * @hsotg: Programming view of DWC_otg controller
520 *
521 * NOTE: The caller can modify the value of the HFIR register only after the
522 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
523 * has been set
524 */
525u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
526{
527 u32 usbcfg;
528 u32 hprt0;
529 int clock = 60; /* default value */
530
531 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
532 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
533
534 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
535 !(usbcfg & GUSBCFG_PHYIF16))
536 clock = 60;
537 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
538 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
539 clock = 48;
540 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
541 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
542 clock = 30;
543 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
544 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
545 clock = 60;
546 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
547 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
548 clock = 48;
549 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
550 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
551 clock = 48;
552 if ((usbcfg & GUSBCFG_PHYSEL) &&
553 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
554 clock = 48;
555
556 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
557 /* High speed case */
558 return 125 * clock - 1;
559
560 /* FS/LS case */
561 return 1000 * clock - 1;
562}
563
564/**
565 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
566 * buffer
567 *
568 * @core_if: Programming view of DWC_otg controller
569 * @dest: Destination buffer for the packet
570 * @bytes: Number of bytes to copy to the destination
571 */
572void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
573{
574 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
575 u32 *data_buf = (u32 *)dest;
576 int word_count = (bytes + 3) / 4;
577 int i;
578
579 /*
580 * Todo: Account for the case where dest is not dword aligned. This
581 * requires reading data from the FIFO into a u32 temp buffer, then
582 * moving it into the data buffer.
583 */
584
585 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
586
587 for (i = 0; i < word_count; i++, data_buf++)
588 *data_buf = dwc2_readl(fifo);
589}
590
Paul Zimmerman7359d482013-03-11 17:47:59 -0700591/**
592 * dwc2_dump_channel_info() - Prints the state of a host channel
593 *
594 * @hsotg: Programming view of DWC_otg controller
595 * @chan: Pointer to the channel to dump
596 *
597 * Must be called with interrupt disabled and spinlock held
598 *
599 * NOTE: This function will be removed once the peripheral controller code
600 * is integrated and the driver is stable
601 */
602static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
603 struct dwc2_host_chan *chan)
604{
605#ifdef VERBOSE_DEBUG
John Younbea8e862016-11-03 17:55:53 -0700606 int num_channels = hsotg->params.host_channels;
Paul Zimmerman7359d482013-03-11 17:47:59 -0700607 struct dwc2_qh *qh;
608 u32 hcchar;
609 u32 hcsplt;
610 u32 hctsiz;
611 u32 hc_dma;
612 int i;
613
John Younb02038fa2016-02-23 19:55:00 -0800614 if (!chan)
Paul Zimmerman7359d482013-03-11 17:47:59 -0700615 return;
616
Antti Seppälä95c8bc32015-08-20 21:41:07 +0300617 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
618 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
619 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
620 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
Paul Zimmerman7359d482013-03-11 17:47:59 -0700621
622 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
623 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
624 hcchar, hcsplt);
625 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
626 hctsiz, hc_dma);
627 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
628 chan->dev_addr, chan->ep_num, chan->ep_is_in);
629 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
630 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
631 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
632 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
633 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
634 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
635 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
636 (unsigned long)chan->xfer_dma);
637 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
638 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
639 dev_dbg(hsotg->dev, " NP inactive sched:\n");
640 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
641 qh_list_entry)
642 dev_dbg(hsotg->dev, " %p\n", qh);
643 dev_dbg(hsotg->dev, " NP active sched:\n");
644 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
645 qh_list_entry)
646 dev_dbg(hsotg->dev, " %p\n", qh);
647 dev_dbg(hsotg->dev, " Channels:\n");
648 for (i = 0; i < num_channels; i++) {
649 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
650
651 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
652 }
653#endif /* VERBOSE_DEBUG */
654}
655
Razmik Karapetyan4411beb2016-11-16 15:34:04 -0800656static int _dwc2_hcd_start(struct usb_hcd *hcd);
657
658static void dwc2_host_start(struct dwc2_hsotg *hsotg)
659{
660 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
661
662 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
663 _dwc2_hcd_start(hcd);
664}
665
666static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
667{
668 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
669
670 hcd->self.is_b_host = 0;
671}
672
673static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
674 int *hub_addr, int *hub_port)
675{
676 struct urb *urb = context;
677
678 if (urb->dev->tt)
679 *hub_addr = urb->dev->tt->hub->devnum;
680 else
681 *hub_addr = 0;
682 *hub_port = urb->dev->ttport;
683}
684
Paul Zimmerman7359d482013-03-11 17:47:59 -0700685/*
John Younb02038fa2016-02-23 19:55:00 -0800686 * =========================================================================
687 * Low Level Host Channel Access Functions
688 * =========================================================================
689 */
690
691static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
692 struct dwc2_host_chan *chan)
693{
694 u32 hcintmsk = HCINTMSK_CHHLTD;
695
696 switch (chan->ep_type) {
697 case USB_ENDPOINT_XFER_CONTROL:
698 case USB_ENDPOINT_XFER_BULK:
699 dev_vdbg(hsotg->dev, "control/bulk\n");
700 hcintmsk |= HCINTMSK_XFERCOMPL;
701 hcintmsk |= HCINTMSK_STALL;
702 hcintmsk |= HCINTMSK_XACTERR;
703 hcintmsk |= HCINTMSK_DATATGLERR;
704 if (chan->ep_is_in) {
705 hcintmsk |= HCINTMSK_BBLERR;
706 } else {
707 hcintmsk |= HCINTMSK_NAK;
708 hcintmsk |= HCINTMSK_NYET;
709 if (chan->do_ping)
710 hcintmsk |= HCINTMSK_ACK;
711 }
712
713 if (chan->do_split) {
714 hcintmsk |= HCINTMSK_NAK;
715 if (chan->complete_split)
716 hcintmsk |= HCINTMSK_NYET;
717 else
718 hcintmsk |= HCINTMSK_ACK;
719 }
720
721 if (chan->error_state)
722 hcintmsk |= HCINTMSK_ACK;
723 break;
724
725 case USB_ENDPOINT_XFER_INT:
726 if (dbg_perio())
727 dev_vdbg(hsotg->dev, "intr\n");
728 hcintmsk |= HCINTMSK_XFERCOMPL;
729 hcintmsk |= HCINTMSK_NAK;
730 hcintmsk |= HCINTMSK_STALL;
731 hcintmsk |= HCINTMSK_XACTERR;
732 hcintmsk |= HCINTMSK_DATATGLERR;
733 hcintmsk |= HCINTMSK_FRMOVRUN;
734
735 if (chan->ep_is_in)
736 hcintmsk |= HCINTMSK_BBLERR;
737 if (chan->error_state)
738 hcintmsk |= HCINTMSK_ACK;
739 if (chan->do_split) {
740 if (chan->complete_split)
741 hcintmsk |= HCINTMSK_NYET;
742 else
743 hcintmsk |= HCINTMSK_ACK;
744 }
745 break;
746
747 case USB_ENDPOINT_XFER_ISOC:
748 if (dbg_perio())
749 dev_vdbg(hsotg->dev, "isoc\n");
750 hcintmsk |= HCINTMSK_XFERCOMPL;
751 hcintmsk |= HCINTMSK_FRMOVRUN;
752 hcintmsk |= HCINTMSK_ACK;
753
754 if (chan->ep_is_in) {
755 hcintmsk |= HCINTMSK_XACTERR;
756 hcintmsk |= HCINTMSK_BBLERR;
757 }
758 break;
759 default:
760 dev_err(hsotg->dev, "## Unknown EP type ##\n");
761 break;
762 }
763
764 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
765 if (dbg_hc(chan))
766 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
767}
768
769static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
770 struct dwc2_host_chan *chan)
771{
772 u32 hcintmsk = HCINTMSK_CHHLTD;
773
774 /*
775 * For Descriptor DMA mode core halts the channel on AHB error.
776 * Interrupt is not required.
777 */
John Youn95832c02017-01-23 14:57:26 -0800778 if (!hsotg->params.dma_desc_enable) {
John Younb02038fa2016-02-23 19:55:00 -0800779 if (dbg_hc(chan))
780 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
781 hcintmsk |= HCINTMSK_AHBERR;
782 } else {
783 if (dbg_hc(chan))
784 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
785 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
786 hcintmsk |= HCINTMSK_XFERCOMPL;
787 }
788
789 if (chan->error_state && !chan->do_split &&
790 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
791 if (dbg_hc(chan))
792 dev_vdbg(hsotg->dev, "setting ACK\n");
793 hcintmsk |= HCINTMSK_ACK;
794 if (chan->ep_is_in) {
795 hcintmsk |= HCINTMSK_DATATGLERR;
796 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
797 hcintmsk |= HCINTMSK_NAK;
798 }
799 }
800
801 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
802 if (dbg_hc(chan))
803 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
804}
805
806static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
807 struct dwc2_host_chan *chan)
808{
809 u32 intmsk;
810
John Youn95832c02017-01-23 14:57:26 -0800811 if (hsotg->params.host_dma) {
John Younb02038fa2016-02-23 19:55:00 -0800812 if (dbg_hc(chan))
813 dev_vdbg(hsotg->dev, "DMA enabled\n");
814 dwc2_hc_enable_dma_ints(hsotg, chan);
815 } else {
816 if (dbg_hc(chan))
817 dev_vdbg(hsotg->dev, "DMA disabled\n");
818 dwc2_hc_enable_slave_ints(hsotg, chan);
819 }
820
821 /* Enable the top level host channel interrupt */
822 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
823 intmsk |= 1 << chan->hc_num;
824 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
825 if (dbg_hc(chan))
826 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
827
828 /* Make sure host channel interrupts are enabled */
829 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
830 intmsk |= GINTSTS_HCHINT;
831 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
832 if (dbg_hc(chan))
833 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
834}
835
836/**
837 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
838 * a specific endpoint
839 *
840 * @hsotg: Programming view of DWC_otg controller
841 * @chan: Information needed to initialize the host channel
842 *
843 * The HCCHARn register is set up with the characteristics specified in chan.
844 * Host channel interrupts that may need to be serviced while this transfer is
845 * in progress are enabled.
846 */
847static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
848{
849 u8 hc_num = chan->hc_num;
850 u32 hcintmsk;
851 u32 hcchar;
852 u32 hcsplt = 0;
853
854 if (dbg_hc(chan))
855 dev_vdbg(hsotg->dev, "%s()\n", __func__);
856
857 /* Clear old interrupt conditions for this host channel */
858 hcintmsk = 0xffffffff;
859 hcintmsk &= ~HCINTMSK_RESERVED14_31;
860 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
861
862 /* Enable channel interrupts required for this transfer */
863 dwc2_hc_enable_ints(hsotg, chan);
864
865 /*
866 * Program the HCCHARn register with the endpoint characteristics for
867 * the current transfer
868 */
869 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
870 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
871 if (chan->ep_is_in)
872 hcchar |= HCCHAR_EPDIR;
873 if (chan->speed == USB_SPEED_LOW)
874 hcchar |= HCCHAR_LSPDDEV;
875 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
876 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
877 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
878 if (dbg_hc(chan)) {
879 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
880 hc_num, hcchar);
881
882 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
883 __func__, hc_num);
884 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
885 chan->dev_addr);
886 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
887 chan->ep_num);
888 dev_vdbg(hsotg->dev, " Is In: %d\n",
889 chan->ep_is_in);
890 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
891 chan->speed == USB_SPEED_LOW);
892 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
893 chan->ep_type);
894 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
895 chan->max_packet);
896 }
897
898 /* Program the HCSPLT register for SPLITs */
899 if (chan->do_split) {
900 if (dbg_hc(chan))
901 dev_vdbg(hsotg->dev,
902 "Programming HC %d with split --> %s\n",
903 hc_num,
904 chan->complete_split ? "CSPLIT" : "SSPLIT");
905 if (chan->complete_split)
906 hcsplt |= HCSPLT_COMPSPLT;
907 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
908 HCSPLT_XACTPOS_MASK;
909 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
910 HCSPLT_HUBADDR_MASK;
911 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
912 HCSPLT_PRTADDR_MASK;
913 if (dbg_hc(chan)) {
914 dev_vdbg(hsotg->dev, " comp split %d\n",
915 chan->complete_split);
916 dev_vdbg(hsotg->dev, " xact pos %d\n",
917 chan->xact_pos);
918 dev_vdbg(hsotg->dev, " hub addr %d\n",
919 chan->hub_addr);
920 dev_vdbg(hsotg->dev, " hub port %d\n",
921 chan->hub_port);
922 dev_vdbg(hsotg->dev, " is_in %d\n",
923 chan->ep_is_in);
924 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
925 chan->max_packet);
926 dev_vdbg(hsotg->dev, " xferlen %d\n",
927 chan->xfer_len);
928 }
929 }
930
931 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
932}
933
934/**
935 * dwc2_hc_halt() - Attempts to halt a host channel
936 *
937 * @hsotg: Controller register interface
938 * @chan: Host channel to halt
939 * @halt_status: Reason for halting the channel
940 *
941 * This function should only be called in Slave mode or to abort a transfer in
942 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
943 * controller halts the channel when the transfer is complete or a condition
944 * occurs that requires application intervention.
945 *
946 * In slave mode, checks for a free request queue entry, then sets the Channel
947 * Enable and Channel Disable bits of the Host Channel Characteristics
948 * register of the specified channel to intiate the halt. If there is no free
949 * request queue entry, sets only the Channel Disable bit of the HCCHARn
950 * register to flush requests for this channel. In the latter case, sets a
951 * flag to indicate that the host channel needs to be halted when a request
952 * queue slot is open.
953 *
954 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
955 * HCCHARn register. The controller ensures there is space in the request
956 * queue before submitting the halt request.
957 *
958 * Some time may elapse before the core flushes any posted requests for this
959 * host channel and halts. The Channel Halted interrupt handler completes the
960 * deactivation of the host channel.
961 */
962void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
963 enum dwc2_halt_status halt_status)
964{
965 u32 nptxsts, hptxsts, hcchar;
966
967 if (dbg_hc(chan))
968 dev_vdbg(hsotg->dev, "%s()\n", __func__);
969 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
970 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
971
972 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
973 halt_status == DWC2_HC_XFER_AHB_ERR) {
974 /*
975 * Disable all channel interrupts except Ch Halted. The QTD
976 * and QH state associated with this transfer has been cleared
977 * (in the case of URB_DEQUEUE), so the channel needs to be
978 * shut down carefully to prevent crashes.
979 */
980 u32 hcintmsk = HCINTMSK_CHHLTD;
981
982 dev_vdbg(hsotg->dev, "dequeue/error\n");
983 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
984
985 /*
986 * Make sure no other interrupts besides halt are currently
987 * pending. Handling another interrupt could cause a crash due
988 * to the QTD and QH state.
989 */
990 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
991
992 /*
993 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
994 * even if the channel was already halted for some other
995 * reason
996 */
997 chan->halt_status = halt_status;
998
999 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1000 if (!(hcchar & HCCHAR_CHENA)) {
1001 /*
1002 * The channel is either already halted or it hasn't
1003 * started yet. In DMA mode, the transfer may halt if
1004 * it finishes normally or a condition occurs that
1005 * requires driver intervention. Don't want to halt
1006 * the channel again. In either Slave or DMA mode,
1007 * it's possible that the transfer has been assigned
1008 * to a channel, but not started yet when an URB is
1009 * dequeued. Don't want to halt a channel that hasn't
1010 * started yet.
1011 */
1012 return;
1013 }
1014 }
1015 if (chan->halt_pending) {
1016 /*
1017 * A halt has already been issued for this channel. This might
1018 * happen when a transfer is aborted by a higher level in
1019 * the stack.
1020 */
1021 dev_vdbg(hsotg->dev,
1022 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1023 __func__, chan->hc_num);
1024 return;
1025 }
1026
1027 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1028
1029 /* No need to set the bit in DDMA for disabling the channel */
1030 /* TODO check it everywhere channel is disabled */
John Youn95832c02017-01-23 14:57:26 -08001031 if (!hsotg->params.dma_desc_enable) {
John Younb02038fa2016-02-23 19:55:00 -08001032 if (dbg_hc(chan))
1033 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1034 hcchar |= HCCHAR_CHENA;
1035 } else {
1036 if (dbg_hc(chan))
1037 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1038 }
1039 hcchar |= HCCHAR_CHDIS;
1040
John Youn95832c02017-01-23 14:57:26 -08001041 if (!hsotg->params.host_dma) {
John Younb02038fa2016-02-23 19:55:00 -08001042 if (dbg_hc(chan))
1043 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1044 hcchar |= HCCHAR_CHENA;
1045
1046 /* Check for space in the request queue to issue the halt */
1047 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1048 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1049 dev_vdbg(hsotg->dev, "control/bulk\n");
1050 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1051 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1052 dev_vdbg(hsotg->dev, "Disabling channel\n");
1053 hcchar &= ~HCCHAR_CHENA;
1054 }
1055 } else {
1056 if (dbg_perio())
1057 dev_vdbg(hsotg->dev, "isoc/intr\n");
1058 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1059 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1060 hsotg->queuing_high_bandwidth) {
1061 if (dbg_perio())
1062 dev_vdbg(hsotg->dev, "Disabling channel\n");
1063 hcchar &= ~HCCHAR_CHENA;
1064 }
1065 }
1066 } else {
1067 if (dbg_hc(chan))
1068 dev_vdbg(hsotg->dev, "DMA enabled\n");
1069 }
1070
1071 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1072 chan->halt_status = halt_status;
1073
1074 if (hcchar & HCCHAR_CHENA) {
1075 if (dbg_hc(chan))
1076 dev_vdbg(hsotg->dev, "Channel enabled\n");
1077 chan->halt_pending = 1;
1078 chan->halt_on_queue = 0;
1079 } else {
1080 if (dbg_hc(chan))
1081 dev_vdbg(hsotg->dev, "Channel disabled\n");
1082 chan->halt_on_queue = 1;
1083 }
1084
1085 if (dbg_hc(chan)) {
1086 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1087 chan->hc_num);
1088 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1089 hcchar);
1090 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1091 chan->halt_pending);
1092 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1093 chan->halt_on_queue);
1094 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1095 chan->halt_status);
1096 }
1097}
1098
1099/**
1100 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1101 *
1102 * @hsotg: Programming view of DWC_otg controller
1103 * @chan: Identifies the host channel to clean up
1104 *
1105 * This function is normally called after a transfer is done and the host
1106 * channel is being released
1107 */
1108void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1109{
1110 u32 hcintmsk;
1111
1112 chan->xfer_started = 0;
1113
1114 list_del_init(&chan->split_order_list_entry);
1115
1116 /*
1117 * Clear channel interrupt enables and any unhandled channel interrupt
1118 * conditions
1119 */
1120 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1121 hcintmsk = 0xffffffff;
1122 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1123 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1124}
1125
1126/**
1127 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1128 * which frame a periodic transfer should occur
1129 *
1130 * @hsotg: Programming view of DWC_otg controller
1131 * @chan: Identifies the host channel to set up and its properties
1132 * @hcchar: Current value of the HCCHAR register for the specified host channel
1133 *
1134 * This function has no effect on non-periodic transfers
1135 */
1136static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1137 struct dwc2_host_chan *chan, u32 *hcchar)
1138{
1139 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1140 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1141 int host_speed;
1142 int xfer_ns;
1143 int xfer_us;
1144 int bytes_in_fifo;
1145 u16 fifo_space;
1146 u16 frame_number;
1147 u16 wire_frame;
1148
1149 /*
1150 * Try to figure out if we're an even or odd frame. If we set
1151 * even and the current frame number is even the the transfer
1152 * will happen immediately. Similar if both are odd. If one is
1153 * even and the other is odd then the transfer will happen when
1154 * the frame number ticks.
1155 *
1156 * There's a bit of a balancing act to get this right.
1157 * Sometimes we may want to send data in the current frame (AK
1158 * right away). We might want to do this if the frame number
1159 * _just_ ticked, but we might also want to do this in order
1160 * to continue a split transaction that happened late in a
1161 * microframe (so we didn't know to queue the next transfer
1162 * until the frame number had ticked). The problem is that we
1163 * need a lot of knowledge to know if there's actually still
1164 * time to send things or if it would be better to wait until
1165 * the next frame.
1166 *
1167 * We can look at how much time is left in the current frame
1168 * and make a guess about whether we'll have time to transfer.
1169 * We'll do that.
1170 */
1171
1172 /* Get speed host is running at */
1173 host_speed = (chan->speed != USB_SPEED_HIGH &&
1174 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1175
1176 /* See how many bytes are in the periodic FIFO right now */
1177 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1178 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1179 bytes_in_fifo = sizeof(u32) *
John Younbea8e862016-11-03 17:55:53 -07001180 (hsotg->params.host_perio_tx_fifo_size -
John Younb02038fa2016-02-23 19:55:00 -08001181 fifo_space);
1182
1183 /*
1184 * Roughly estimate bus time for everything in the periodic
1185 * queue + our new transfer. This is "rough" because we're
1186 * using a function that makes takes into account IN/OUT
1187 * and INT/ISO and we're just slamming in one value for all
1188 * transfers. This should be an over-estimate and that should
1189 * be OK, but we can probably tighten it.
1190 */
1191 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1192 chan->xfer_len + bytes_in_fifo);
1193 xfer_us = NS_TO_US(xfer_ns);
1194
1195 /* See what frame number we'll be at by the time we finish */
1196 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1197
1198 /* This is when we were scheduled to be on the wire */
1199 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1200
1201 /*
1202 * If we'd finish _after_ the frame we're scheduled in then
1203 * it's hopeless. Just schedule right away and hope for the
1204 * best. Note that it _might_ be wise to call back into the
1205 * scheduler to pick a better frame, but this is better than
1206 * nothing.
1207 */
1208 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1209 dwc2_sch_vdbg(hsotg,
1210 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1211 chan->qh, wire_frame, frame_number,
1212 dwc2_frame_num_dec(frame_number,
1213 wire_frame));
1214 wire_frame = frame_number;
1215
1216 /*
1217 * We picked a different frame number; communicate this
1218 * back to the scheduler so it doesn't try to schedule
1219 * another in the same frame.
1220 *
1221 * Remember that next_active_frame is 1 before the wire
1222 * frame.
1223 */
1224 chan->qh->next_active_frame =
1225 dwc2_frame_num_dec(frame_number, 1);
1226 }
1227
1228 if (wire_frame & 1)
1229 *hcchar |= HCCHAR_ODDFRM;
1230 else
1231 *hcchar &= ~HCCHAR_ODDFRM;
1232 }
1233}
1234
1235static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1236{
1237 /* Set up the initial PID for the transfer */
1238 if (chan->speed == USB_SPEED_HIGH) {
1239 if (chan->ep_is_in) {
1240 if (chan->multi_count == 1)
1241 chan->data_pid_start = DWC2_HC_PID_DATA0;
1242 else if (chan->multi_count == 2)
1243 chan->data_pid_start = DWC2_HC_PID_DATA1;
1244 else
1245 chan->data_pid_start = DWC2_HC_PID_DATA2;
1246 } else {
1247 if (chan->multi_count == 1)
1248 chan->data_pid_start = DWC2_HC_PID_DATA0;
1249 else
1250 chan->data_pid_start = DWC2_HC_PID_MDATA;
1251 }
1252 } else {
1253 chan->data_pid_start = DWC2_HC_PID_DATA0;
1254 }
1255}
1256
1257/**
1258 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1259 * the Host Channel
1260 *
1261 * @hsotg: Programming view of DWC_otg controller
1262 * @chan: Information needed to initialize the host channel
1263 *
1264 * This function should only be called in Slave mode. For a channel associated
1265 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1266 * associated with a periodic EP, the periodic Tx FIFO is written.
1267 *
1268 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1269 * the number of bytes written to the Tx FIFO.
1270 */
1271static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1272 struct dwc2_host_chan *chan)
1273{
1274 u32 i;
1275 u32 remaining_count;
1276 u32 byte_count;
1277 u32 dword_count;
1278 u32 __iomem *data_fifo;
1279 u32 *data_buf = (u32 *)chan->xfer_buf;
1280
1281 if (dbg_hc(chan))
1282 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1283
1284 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1285
1286 remaining_count = chan->xfer_len - chan->xfer_count;
1287 if (remaining_count > chan->max_packet)
1288 byte_count = chan->max_packet;
1289 else
1290 byte_count = remaining_count;
1291
1292 dword_count = (byte_count + 3) / 4;
1293
1294 if (((unsigned long)data_buf & 0x3) == 0) {
1295 /* xfer_buf is DWORD aligned */
1296 for (i = 0; i < dword_count; i++, data_buf++)
1297 dwc2_writel(*data_buf, data_fifo);
1298 } else {
1299 /* xfer_buf is not DWORD aligned */
1300 for (i = 0; i < dword_count; i++, data_buf++) {
1301 u32 data = data_buf[0] | data_buf[1] << 8 |
1302 data_buf[2] << 16 | data_buf[3] << 24;
1303 dwc2_writel(data, data_fifo);
1304 }
1305 }
1306
1307 chan->xfer_count += byte_count;
1308 chan->xfer_buf += byte_count;
1309}
1310
1311/**
1312 * dwc2_hc_do_ping() - Starts a PING transfer
1313 *
1314 * @hsotg: Programming view of DWC_otg controller
1315 * @chan: Information needed to initialize the host channel
1316 *
1317 * This function should only be called in Slave mode. The Do Ping bit is set in
1318 * the HCTSIZ register, then the channel is enabled.
1319 */
1320static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1321 struct dwc2_host_chan *chan)
1322{
1323 u32 hcchar;
1324 u32 hctsiz;
1325
1326 if (dbg_hc(chan))
1327 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1328 chan->hc_num);
1329
1330 hctsiz = TSIZ_DOPNG;
1331 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1332 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1333
1334 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1335 hcchar |= HCCHAR_CHENA;
1336 hcchar &= ~HCCHAR_CHDIS;
1337 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1338}
1339
1340/**
1341 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1342 * channel and starts the transfer
1343 *
1344 * @hsotg: Programming view of DWC_otg controller
1345 * @chan: Information needed to initialize the host channel. The xfer_len value
1346 * may be reduced to accommodate the max widths of the XferSize and
1347 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1348 * changed to reflect the final xfer_len value.
1349 *
1350 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1351 * the caller must ensure that there is sufficient space in the request queue
1352 * and Tx Data FIFO.
1353 *
1354 * For an OUT transfer in Slave mode, it loads a data packet into the
1355 * appropriate FIFO. If necessary, additional data packets are loaded in the
1356 * Host ISR.
1357 *
1358 * For an IN transfer in Slave mode, a data packet is requested. The data
1359 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1360 * additional data packets are requested in the Host ISR.
1361 *
1362 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1363 * register along with a packet count of 1 and the channel is enabled. This
1364 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1365 * simply set to 0 since no data transfer occurs in this case.
1366 *
1367 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1368 * all the information required to perform the subsequent data transfer. In
1369 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1370 * controller performs the entire PING protocol, then starts the data
1371 * transfer.
1372 */
1373static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1374 struct dwc2_host_chan *chan)
1375{
John Younbea8e862016-11-03 17:55:53 -07001376 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1377 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
John Younb02038fa2016-02-23 19:55:00 -08001378 u32 hcchar;
1379 u32 hctsiz = 0;
1380 u16 num_packets;
1381 u32 ec_mc;
1382
1383 if (dbg_hc(chan))
1384 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1385
1386 if (chan->do_ping) {
John Youn95832c02017-01-23 14:57:26 -08001387 if (!hsotg->params.host_dma) {
John Younb02038fa2016-02-23 19:55:00 -08001388 if (dbg_hc(chan))
1389 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1390 dwc2_hc_do_ping(hsotg, chan);
1391 chan->xfer_started = 1;
1392 return;
1393 }
1394
1395 if (dbg_hc(chan))
1396 dev_vdbg(hsotg->dev, "ping, DMA\n");
1397
1398 hctsiz |= TSIZ_DOPNG;
1399 }
1400
1401 if (chan->do_split) {
1402 if (dbg_hc(chan))
1403 dev_vdbg(hsotg->dev, "split\n");
1404 num_packets = 1;
1405
1406 if (chan->complete_split && !chan->ep_is_in)
1407 /*
1408 * For CSPLIT OUT Transfer, set the size to 0 so the
1409 * core doesn't expect any data written to the FIFO
1410 */
1411 chan->xfer_len = 0;
1412 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1413 chan->xfer_len = chan->max_packet;
1414 else if (!chan->ep_is_in && chan->xfer_len > 188)
1415 chan->xfer_len = 188;
1416
1417 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1418 TSIZ_XFERSIZE_MASK;
1419
1420 /* For split set ec_mc for immediate retries */
1421 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1422 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1423 ec_mc = 3;
1424 else
1425 ec_mc = 1;
1426 } else {
1427 if (dbg_hc(chan))
1428 dev_vdbg(hsotg->dev, "no split\n");
1429 /*
1430 * Ensure that the transfer length and packet count will fit
1431 * in the widths allocated for them in the HCTSIZn register
1432 */
1433 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1434 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1435 /*
1436 * Make sure the transfer size is no larger than one
1437 * (micro)frame's worth of data. (A check was done
1438 * when the periodic transfer was accepted to ensure
1439 * that a (micro)frame's worth of data can be
1440 * programmed into a channel.)
1441 */
1442 u32 max_periodic_len =
1443 chan->multi_count * chan->max_packet;
1444
1445 if (chan->xfer_len > max_periodic_len)
1446 chan->xfer_len = max_periodic_len;
1447 } else if (chan->xfer_len > max_hc_xfer_size) {
1448 /*
1449 * Make sure that xfer_len is a multiple of max packet
1450 * size
1451 */
1452 chan->xfer_len =
1453 max_hc_xfer_size - chan->max_packet + 1;
1454 }
1455
1456 if (chan->xfer_len > 0) {
1457 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1458 chan->max_packet;
1459 if (num_packets > max_hc_pkt_count) {
1460 num_packets = max_hc_pkt_count;
1461 chan->xfer_len = num_packets * chan->max_packet;
1462 }
1463 } else {
1464 /* Need 1 packet for transfer length of 0 */
1465 num_packets = 1;
1466 }
1467
1468 if (chan->ep_is_in)
1469 /*
1470 * Always program an integral # of max packets for IN
1471 * transfers
1472 */
1473 chan->xfer_len = num_packets * chan->max_packet;
1474
1475 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1476 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1477 /*
1478 * Make sure that the multi_count field matches the
1479 * actual transfer length
1480 */
1481 chan->multi_count = num_packets;
1482
1483 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1484 dwc2_set_pid_isoc(chan);
1485
1486 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1487 TSIZ_XFERSIZE_MASK;
1488
1489 /* The ec_mc gets the multi_count for non-split */
1490 ec_mc = chan->multi_count;
1491 }
1492
1493 chan->start_pkt_count = num_packets;
1494 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1495 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1496 TSIZ_SC_MC_PID_MASK;
1497 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1498 if (dbg_hc(chan)) {
1499 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1500 hctsiz, chan->hc_num);
1501
1502 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1503 chan->hc_num);
1504 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1505 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1506 TSIZ_XFERSIZE_SHIFT);
1507 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1508 (hctsiz & TSIZ_PKTCNT_MASK) >>
1509 TSIZ_PKTCNT_SHIFT);
1510 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1511 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1512 TSIZ_SC_MC_PID_SHIFT);
1513 }
1514
John Youn95832c02017-01-23 14:57:26 -08001515 if (hsotg->params.host_dma) {
John Younb02038fa2016-02-23 19:55:00 -08001516 dwc2_writel((u32)chan->xfer_dma,
1517 hsotg->regs + HCDMA(chan->hc_num));
1518 if (dbg_hc(chan))
1519 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1520 (unsigned long)chan->xfer_dma, chan->hc_num);
1521 }
1522
1523 /* Start the split */
1524 if (chan->do_split) {
1525 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1526
1527 hcsplt |= HCSPLT_SPLTENA;
1528 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1529 }
1530
1531 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1532 hcchar &= ~HCCHAR_MULTICNT_MASK;
1533 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1534 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1535
1536 if (hcchar & HCCHAR_CHDIS)
1537 dev_warn(hsotg->dev,
1538 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1539 __func__, chan->hc_num, hcchar);
1540
1541 /* Set host channel enable after all other setup is complete */
1542 hcchar |= HCCHAR_CHENA;
1543 hcchar &= ~HCCHAR_CHDIS;
1544
1545 if (dbg_hc(chan))
1546 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1547 (hcchar & HCCHAR_MULTICNT_MASK) >>
1548 HCCHAR_MULTICNT_SHIFT);
1549
1550 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1551 if (dbg_hc(chan))
1552 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1553 chan->hc_num);
1554
1555 chan->xfer_started = 1;
1556 chan->requests++;
1557
John Youn95832c02017-01-23 14:57:26 -08001558 if (!hsotg->params.host_dma &&
John Younb02038fa2016-02-23 19:55:00 -08001559 !chan->ep_is_in && chan->xfer_len > 0)
1560 /* Load OUT packet into the appropriate Tx FIFO */
1561 dwc2_hc_write_packet(hsotg, chan);
1562}
1563
1564/**
1565 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1566 * host channel and starts the transfer in Descriptor DMA mode
1567 *
1568 * @hsotg: Programming view of DWC_otg controller
1569 * @chan: Information needed to initialize the host channel
1570 *
1571 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1572 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1573 * with micro-frame bitmap.
1574 *
1575 * Initializes HCDMA register with descriptor list address and CTD value then
1576 * starts the transfer via enabling the channel.
1577 */
1578void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1579 struct dwc2_host_chan *chan)
1580{
1581 u32 hcchar;
1582 u32 hctsiz = 0;
1583
1584 if (chan->do_ping)
1585 hctsiz |= TSIZ_DOPNG;
1586
1587 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1588 dwc2_set_pid_isoc(chan);
1589
1590 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1591 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1592 TSIZ_SC_MC_PID_MASK;
1593
1594 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1595 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1596
1597 /* Non-zero only for high-speed interrupt endpoints */
1598 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1599
1600 if (dbg_hc(chan)) {
1601 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1602 chan->hc_num);
1603 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1604 chan->data_pid_start);
1605 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1606 }
1607
1608 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1609
1610 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1611 chan->desc_list_sz, DMA_TO_DEVICE);
1612
1613 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1614
1615 if (dbg_hc(chan))
1616 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1617 &chan->desc_list_addr, chan->hc_num);
1618
1619 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1620 hcchar &= ~HCCHAR_MULTICNT_MASK;
1621 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1622 HCCHAR_MULTICNT_MASK;
1623
1624 if (hcchar & HCCHAR_CHDIS)
1625 dev_warn(hsotg->dev,
1626 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1627 __func__, chan->hc_num, hcchar);
1628
1629 /* Set host channel enable after all other setup is complete */
1630 hcchar |= HCCHAR_CHENA;
1631 hcchar &= ~HCCHAR_CHDIS;
1632
1633 if (dbg_hc(chan))
1634 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1635 (hcchar & HCCHAR_MULTICNT_MASK) >>
1636 HCCHAR_MULTICNT_SHIFT);
1637
1638 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1639 if (dbg_hc(chan))
1640 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1641 chan->hc_num);
1642
1643 chan->xfer_started = 1;
1644 chan->requests++;
1645}
1646
1647/**
1648 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1649 * a previous call to dwc2_hc_start_transfer()
1650 *
1651 * @hsotg: Programming view of DWC_otg controller
1652 * @chan: Information needed to initialize the host channel
1653 *
1654 * The caller must ensure there is sufficient space in the request queue and Tx
1655 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1656 * the controller acts autonomously to complete transfers programmed to a host
1657 * channel.
1658 *
1659 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1660 * if there is any data remaining to be queued. For an IN transfer, another
1661 * data packet is always requested. For the SETUP phase of a control transfer,
1662 * this function does nothing.
1663 *
1664 * Return: 1 if a new request is queued, 0 if no more requests are required
1665 * for this transfer
1666 */
1667static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1668 struct dwc2_host_chan *chan)
1669{
1670 if (dbg_hc(chan))
1671 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1672 chan->hc_num);
1673
1674 if (chan->do_split)
1675 /* SPLITs always queue just once per channel */
1676 return 0;
1677
1678 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1679 /* SETUPs are queued only once since they can't be NAK'd */
1680 return 0;
1681
1682 if (chan->ep_is_in) {
1683 /*
1684 * Always queue another request for other IN transfers. If
1685 * back-to-back INs are issued and NAKs are received for both,
1686 * the driver may still be processing the first NAK when the
1687 * second NAK is received. When the interrupt handler clears
1688 * the NAK interrupt for the first NAK, the second NAK will
1689 * not be seen. So we can't depend on the NAK interrupt
1690 * handler to requeue a NAK'd request. Instead, IN requests
1691 * are issued each time this function is called. When the
1692 * transfer completes, the extra requests for the channel will
1693 * be flushed.
1694 */
1695 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1696
1697 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1698 hcchar |= HCCHAR_CHENA;
1699 hcchar &= ~HCCHAR_CHDIS;
1700 if (dbg_hc(chan))
1701 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1702 hcchar);
1703 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1704 chan->requests++;
1705 return 1;
1706 }
1707
1708 /* OUT transfers */
1709
1710 if (chan->xfer_count < chan->xfer_len) {
1711 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1712 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1713 u32 hcchar = dwc2_readl(hsotg->regs +
1714 HCCHAR(chan->hc_num));
1715
1716 dwc2_hc_set_even_odd_frame(hsotg, chan,
1717 &hcchar);
1718 }
1719
1720 /* Load OUT packet into the appropriate Tx FIFO */
1721 dwc2_hc_write_packet(hsotg, chan);
1722 chan->requests++;
1723 return 1;
1724 }
1725
1726 return 0;
1727}
1728
1729/*
1730 * =========================================================================
1731 * HCD
1732 * =========================================================================
1733 */
1734
1735/*
Paul Zimmerman7359d482013-03-11 17:47:59 -07001736 * Processes all the URBs in a single list of QHs. Completes them with
1737 * -ETIMEDOUT and frees the QTD.
1738 *
1739 * Must be called with interrupt disabled and spinlock held
1740 */
1741static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1742 struct list_head *qh_list)
1743{
1744 struct dwc2_qh *qh, *qh_tmp;
1745 struct dwc2_qtd *qtd, *qtd_tmp;
1746
1747 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1748 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1749 qtd_list_entry) {
Gregory Herrero2e84da62015-09-22 15:16:53 +02001750 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
Paul Zimmerman0d012b92013-07-13 14:53:48 -07001751 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
Paul Zimmerman7359d482013-03-11 17:47:59 -07001752 }
1753 }
1754}
1755
1756static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1757 struct list_head *qh_list)
1758{
1759 struct dwc2_qtd *qtd, *qtd_tmp;
1760 struct dwc2_qh *qh, *qh_tmp;
1761 unsigned long flags;
1762
1763 if (!qh_list->next)
1764 /* The list hasn't been initialized yet */
1765 return;
1766
1767 spin_lock_irqsave(&hsotg->lock, flags);
1768
1769 /* Ensure there are no QTDs or URBs left */
1770 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1771
1772 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1773 dwc2_hcd_qh_unlink(hsotg, qh);
1774
1775 /* Free each QTD in the QH's QTD list */
1776 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1777 qtd_list_entry)
1778 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1779
Douglas Anderson16e80212016-01-28 18:19:55 -08001780 if (qh->channel && qh->channel->qh == qh)
1781 qh->channel->qh = NULL;
1782
Paul Zimmerman7359d482013-03-11 17:47:59 -07001783 spin_unlock_irqrestore(&hsotg->lock, flags);
1784 dwc2_hcd_qh_free(hsotg, qh);
1785 spin_lock_irqsave(&hsotg->lock, flags);
1786 }
1787
1788 spin_unlock_irqrestore(&hsotg->lock, flags);
1789}
1790
1791/*
1792 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1793 * and periodic schedules. The QTD associated with each URB is removed from
1794 * the schedule and freed. This function may be called when a disconnect is
1795 * detected or when the HCD is being stopped.
1796 *
1797 * Must be called with interrupt disabled and spinlock held
1798 */
1799static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1800{
1801 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1802 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1803 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1804 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1805 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1806 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1807}
1808
1809/**
1810 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1811 *
1812 * @hsotg: Pointer to struct dwc2_hsotg
1813 */
1814void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1815{
1816 u32 hprt0;
1817
1818 if (hsotg->op_state == OTG_STATE_B_HOST) {
1819 /*
1820 * Reset the port. During a HNP mode switch the reset
1821 * needs to occur within 1ms and have a duration of at
1822 * least 50ms.
1823 */
1824 hprt0 = dwc2_read_hprt0(hsotg);
1825 hprt0 |= HPRT0_RST;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001826 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07001827 }
1828
1829 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1830 msecs_to_jiffies(50));
1831}
1832
1833/* Must be called with interrupt disabled and spinlock held */
1834static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1835{
John Younbea8e862016-11-03 17:55:53 -07001836 int num_channels = hsotg->params.host_channels;
Paul Zimmerman7359d482013-03-11 17:47:59 -07001837 struct dwc2_host_chan *channel;
1838 u32 hcchar;
1839 int i;
1840
John Youn95832c02017-01-23 14:57:26 -08001841 if (!hsotg->params.host_dma) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07001842 /* Flush out any channel requests in slave mode */
1843 for (i = 0; i < num_channels; i++) {
1844 channel = hsotg->hc_ptr_array[i];
1845 if (!list_empty(&channel->hc_list_entry))
1846 continue;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001847 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
Paul Zimmerman7359d482013-03-11 17:47:59 -07001848 if (hcchar & HCCHAR_CHENA) {
1849 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1850 hcchar |= HCCHAR_CHDIS;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001851 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
Paul Zimmerman7359d482013-03-11 17:47:59 -07001852 }
1853 }
1854 }
1855
1856 for (i = 0; i < num_channels; i++) {
1857 channel = hsotg->hc_ptr_array[i];
1858 if (!list_empty(&channel->hc_list_entry))
1859 continue;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001860 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
Paul Zimmerman7359d482013-03-11 17:47:59 -07001861 if (hcchar & HCCHAR_CHENA) {
1862 /* Halt the channel */
1863 hcchar |= HCCHAR_CHDIS;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001864 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
Paul Zimmerman7359d482013-03-11 17:47:59 -07001865 }
1866
1867 dwc2_hc_cleanup(hsotg, channel);
1868 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1869 /*
1870 * Added for Descriptor DMA to prevent channel double cleanup in
1871 * release_channel_ddma(), which is called from ep_disable when
1872 * device disconnects
1873 */
1874 channel->qh = NULL;
1875 }
Vincent Palatin7252f1b2015-03-15 13:24:32 -07001876 /* All channels have been freed, mark them available */
John Youn95832c02017-01-23 14:57:26 -08001877 if (hsotg->params.uframe_sched) {
Vincent Palatin7252f1b2015-03-15 13:24:32 -07001878 hsotg->available_host_channels =
John Younbea8e862016-11-03 17:55:53 -07001879 hsotg->params.host_channels;
Vincent Palatin7252f1b2015-03-15 13:24:32 -07001880 } else {
1881 hsotg->non_periodic_channels = 0;
1882 hsotg->periodic_channels = 0;
1883 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07001884}
1885
1886/**
Douglas Anderson6a659532015-11-19 13:23:14 -08001887 * dwc2_hcd_connect() - Handles connect of the HCD
Paul Zimmerman7359d482013-03-11 17:47:59 -07001888 *
1889 * @hsotg: Pointer to struct dwc2_hsotg
1890 *
1891 * Must be called with interrupt disabled and spinlock held
1892 */
Douglas Anderson6a659532015-11-19 13:23:14 -08001893void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1894{
1895 if (hsotg->lx_state != DWC2_L0)
1896 usb_hcd_resume_root_hub(hsotg->priv);
1897
1898 hsotg->flags.b.port_connect_status_change = 1;
1899 hsotg->flags.b.port_connect_status = 1;
1900}
1901
1902/**
1903 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1904 *
1905 * @hsotg: Pointer to struct dwc2_hsotg
1906 * @force: If true, we won't try to reconnect even if we see device connected.
1907 *
1908 * Must be called with interrupt disabled and spinlock held
1909 */
1910void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
Paul Zimmerman7359d482013-03-11 17:47:59 -07001911{
1912 u32 intr;
Douglas Anderson6a659532015-11-19 13:23:14 -08001913 u32 hprt0;
Paul Zimmerman7359d482013-03-11 17:47:59 -07001914
1915 /* Set status flags for the hub driver */
1916 hsotg->flags.b.port_connect_status_change = 1;
1917 hsotg->flags.b.port_connect_status = 0;
1918
1919 /*
1920 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1921 * interrupt mask and status bits and disabling subsequent host
1922 * channel interrupts.
1923 */
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001924 intr = dwc2_readl(hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07001925 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001926 dwc2_writel(intr, hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07001927 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001928 dwc2_writel(intr, hsotg->regs + GINTSTS);
Paul Zimmerman7359d482013-03-11 17:47:59 -07001929
1930 /*
1931 * Turn off the vbus power only if the core has transitioned to device
1932 * mode. If still in host mode, need to keep power on to detect a
1933 * reconnection.
1934 */
1935 if (dwc2_is_device_mode(hsotg)) {
1936 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1937 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
Antti Seppälä95c8bc32015-08-20 21:41:07 +03001938 dwc2_writel(0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07001939 }
1940
1941 dwc2_disable_host_interrupts(hsotg);
1942 }
1943
1944 /* Respond with an error status to all URBs in the schedule */
1945 dwc2_kill_all_urbs(hsotg);
1946
1947 if (dwc2_is_host_mode(hsotg))
1948 /* Clean up any host channels that were in use */
1949 dwc2_hcd_cleanup_channels(hsotg);
1950
1951 dwc2_host_disconnect(hsotg);
Douglas Anderson6a659532015-11-19 13:23:14 -08001952
1953 /*
1954 * Add an extra check here to see if we're actually connected but
1955 * we don't have a detection interrupt pending. This can happen if:
1956 * 1. hardware sees connect
1957 * 2. hardware sees disconnect
1958 * 3. hardware sees connect
1959 * 4. dwc2_port_intr() - clears connect interrupt
1960 * 5. dwc2_handle_common_intr() - calls here
1961 *
1962 * Without the extra check here we will end calling disconnect
1963 * and won't get any future interrupts to handle the connect.
1964 */
1965 if (!force) {
1966 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1967 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1968 dwc2_hcd_connect(hsotg);
1969 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07001970}
1971
1972/**
1973 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1974 *
1975 * @hsotg: Pointer to struct dwc2_hsotg
1976 */
1977static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1978{
Douglas Anderson1fb7f122015-10-22 13:05:03 -07001979 if (hsotg->bus_suspended) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07001980 hsotg->flags.b.port_suspend_change = 1;
Gregory Herrerob46146d52015-01-30 09:09:26 +01001981 usb_hcd_resume_root_hub(hsotg->priv);
Gregory Herrerob46146d52015-01-30 09:09:26 +01001982 }
Douglas Anderson1fb7f122015-10-22 13:05:03 -07001983
1984 if (hsotg->lx_state == DWC2_L1)
1985 hsotg->flags.b.port_l1_change = 1;
Paul Zimmerman7359d482013-03-11 17:47:59 -07001986}
1987
1988/**
1989 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1990 *
1991 * @hsotg: Pointer to struct dwc2_hsotg
1992 *
1993 * Must be called with interrupt disabled and spinlock held
1994 */
1995void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1996{
1997 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1998
1999 /*
2000 * The root hub should be disconnected before this function is called.
2001 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2002 * and the QH lists (via ..._hcd_endpoint_disable).
2003 */
2004
2005 /* Turn off all host-specific interrupts */
2006 dwc2_disable_host_interrupts(hsotg);
2007
2008 /* Turn off the vbus power */
2009 dev_dbg(hsotg->dev, "PortPower off\n");
Antti Seppälä95c8bc32015-08-20 21:41:07 +03002010 dwc2_writel(0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002011}
2012
Gregory Herrero33ad2612015-04-29 22:09:15 +02002013/* Caller must hold driver lock */
Paul Zimmerman7359d482013-03-11 17:47:59 -07002014static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
Mian Yousaf Kaukabb58e6ce2015-06-29 11:05:28 +02002015 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02002016 struct dwc2_qtd *qtd)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002017{
Paul Zimmerman7359d482013-03-11 17:47:59 -07002018 u32 intr_mask;
2019 int retval;
Nick Hudson9f8144c2013-12-06 14:01:44 -08002020 int dev_speed;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002021
2022 if (!hsotg->flags.b.port_connect_status) {
2023 /* No longer connected */
2024 dev_err(hsotg->dev, "Not connected\n");
2025 return -ENODEV;
2026 }
2027
Nick Hudson9f8144c2013-12-06 14:01:44 -08002028 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2029
2030 /* Some configurations cannot support LS traffic on a FS root port */
2031 if ((dev_speed == USB_SPEED_LOW) &&
2032 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2033 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
Antti Seppälä95c8bc32015-08-20 21:41:07 +03002034 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
Nick Hudson9f8144c2013-12-06 14:01:44 -08002035 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2036
2037 if (prtspd == HPRT0_SPD_FULL_SPEED)
2038 return -ENODEV;
2039 }
2040
Paul Zimmerman7359d482013-03-11 17:47:59 -07002041 if (!qtd)
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02002042 return -EINVAL;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002043
2044 dwc2_hcd_qtd_init(qtd, urb);
Mian Yousaf Kaukabb58e6ce2015-06-29 11:05:28 +02002045 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
Paul Zimmerman9bda1aa2013-11-22 16:43:45 -08002046 if (retval) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07002047 dev_err(hsotg->dev,
2048 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2049 retval);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002050 return retval;
2051 }
2052
Antti Seppälä95c8bc32015-08-20 21:41:07 +03002053 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
Paul Zimmerman9bda1aa2013-11-22 16:43:45 -08002054 if (!(intr_mask & GINTSTS_SOF)) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07002055 enum dwc2_transaction_type tr_type;
2056
2057 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2058 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2059 /*
2060 * Do not schedule SG transactions until qtd has
2061 * URB_GIVEBACK_ASAP set
2062 */
2063 return 0;
2064
Paul Zimmerman7359d482013-03-11 17:47:59 -07002065 tr_type = dwc2_hcd_select_transactions(hsotg);
2066 if (tr_type != DWC2_TRANSACTION_NONE)
2067 dwc2_hcd_queue_transactions(hsotg, tr_type);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002068 }
2069
Paul Zimmerman9bda1aa2013-11-22 16:43:45 -08002070 return 0;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002071}
2072
2073/* Must be called with interrupt disabled and spinlock held */
2074static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2075 struct dwc2_hcd_urb *urb)
2076{
2077 struct dwc2_qh *qh;
2078 struct dwc2_qtd *urb_qtd;
2079
2080 urb_qtd = urb->qtd;
2081 if (!urb_qtd) {
2082 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2083 return -EINVAL;
2084 }
2085
2086 qh = urb_qtd->qh;
2087 if (!qh) {
2088 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2089 return -EINVAL;
2090 }
2091
Paul Zimmerman0d012b92013-07-13 14:53:48 -07002092 urb->priv = NULL;
2093
Paul Zimmerman7359d482013-03-11 17:47:59 -07002094 if (urb_qtd->in_process && qh->channel) {
2095 dwc2_dump_channel_info(hsotg, qh->channel);
2096
2097 /* The QTD is in process (it has been assigned to a channel) */
2098 if (hsotg->flags.b.port_connect_status)
2099 /*
2100 * If still connected (i.e. in host mode), halt the
2101 * channel so it can be used for other transfers. If
2102 * no longer connected, the host registers can't be
2103 * written to halt the channel since the core is in
2104 * device mode.
2105 */
2106 dwc2_hc_halt(hsotg, qh->channel,
2107 DWC2_HC_XFER_URB_DEQUEUE);
2108 }
2109
2110 /*
2111 * Free the QTD and clean up the associated QH. Leave the QH in the
2112 * schedule if it has any remaining QTDs.
2113 */
John Youn95832c02017-01-23 14:57:26 -08002114 if (!hsotg->params.dma_desc_enable) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07002115 u8 in_process = urb_qtd->in_process;
2116
2117 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2118 if (in_process) {
2119 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2120 qh->channel = NULL;
2121 } else if (list_empty(&qh->qtd_list)) {
2122 dwc2_hcd_qh_unlink(hsotg, qh);
2123 }
2124 } else {
2125 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2126 }
2127
2128 return 0;
2129}
2130
2131/* Must NOT be called with interrupt disabled or spinlock held */
2132static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2133 struct usb_host_endpoint *ep, int retry)
2134{
2135 struct dwc2_qtd *qtd, *qtd_tmp;
2136 struct dwc2_qh *qh;
2137 unsigned long flags;
2138 int rc;
2139
2140 spin_lock_irqsave(&hsotg->lock, flags);
2141
2142 qh = ep->hcpriv;
2143 if (!qh) {
2144 rc = -EINVAL;
2145 goto err;
2146 }
2147
2148 while (!list_empty(&qh->qtd_list) && retry--) {
2149 if (retry == 0) {
2150 dev_err(hsotg->dev,
2151 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2152 rc = -EBUSY;
2153 goto err;
2154 }
2155
2156 spin_unlock_irqrestore(&hsotg->lock, flags);
Nicholas Mc Guire04a9db72017-01-12 16:54:03 +01002157 msleep(20);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002158 spin_lock_irqsave(&hsotg->lock, flags);
2159 qh = ep->hcpriv;
2160 if (!qh) {
2161 rc = -EINVAL;
2162 goto err;
2163 }
2164 }
2165
2166 dwc2_hcd_qh_unlink(hsotg, qh);
2167
2168 /* Free each QTD in the QH's QTD list */
2169 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2170 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2171
2172 ep->hcpriv = NULL;
Douglas Anderson16e80212016-01-28 18:19:55 -08002173
2174 if (qh->channel && qh->channel->qh == qh)
2175 qh->channel->qh = NULL;
2176
Paul Zimmerman7359d482013-03-11 17:47:59 -07002177 spin_unlock_irqrestore(&hsotg->lock, flags);
Douglas Anderson16e80212016-01-28 18:19:55 -08002178
Paul Zimmerman7359d482013-03-11 17:47:59 -07002179 dwc2_hcd_qh_free(hsotg, qh);
2180
2181 return 0;
2182
2183err:
2184 ep->hcpriv = NULL;
2185 spin_unlock_irqrestore(&hsotg->lock, flags);
2186
2187 return rc;
2188}
2189
2190/* Must be called with interrupt disabled and spinlock held */
2191static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2192 struct usb_host_endpoint *ep)
2193{
2194 struct dwc2_qh *qh = ep->hcpriv;
2195
2196 if (!qh)
2197 return -EINVAL;
2198
2199 qh->data_toggle = DWC2_HC_PID_DATA0;
2200
2201 return 0;
2202}
2203
John Younb02038fa2016-02-23 19:55:00 -08002204/**
2205 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2206 * prepares the core for device mode or host mode operation
2207 *
2208 * @hsotg: Programming view of the DWC_otg controller
2209 * @initial_setup: If true then this is the first init for this instance.
2210 */
2211static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2212{
2213 u32 usbcfg, otgctl;
2214 int retval;
2215
2216 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2217
2218 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2219
2220 /* Set ULPI External VBUS bit if needed */
2221 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
John Youn95832c02017-01-23 14:57:26 -08002222 if (hsotg->params.phy_ulpi_ext_vbus)
John Younb02038fa2016-02-23 19:55:00 -08002223 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2224
2225 /* Set external TS Dline pulsing bit if needed */
2226 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
John Youn95832c02017-01-23 14:57:26 -08002227 if (hsotg->params.ts_dline)
John Younb02038fa2016-02-23 19:55:00 -08002228 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2229
2230 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2231
2232 /*
2233 * Reset the Controller
2234 *
2235 * We only need to reset the controller if this is a re-init.
2236 * For the first init we know for sure that earlier code reset us (it
2237 * needed to in order to properly detect various parameters).
2238 */
2239 if (!initial_setup) {
2240 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
2241 if (retval) {
2242 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2243 __func__);
2244 return retval;
2245 }
2246 }
2247
2248 /*
2249 * This needs to happen in FS mode before any other programming occurs
2250 */
2251 retval = dwc2_phy_init(hsotg, initial_setup);
2252 if (retval)
2253 return retval;
2254
2255 /* Program the GAHBCFG Register */
2256 retval = dwc2_gahbcfg_init(hsotg);
2257 if (retval)
2258 return retval;
2259
2260 /* Program the GUSBCFG register */
2261 dwc2_gusbcfg_init(hsotg);
2262
2263 /* Program the GOTGCTL register */
2264 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2265 otgctl &= ~GOTGCTL_OTGVER;
John Younb02038fa2016-02-23 19:55:00 -08002266 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
John Younb02038fa2016-02-23 19:55:00 -08002267
2268 /* Clear the SRP success bit for FS-I2c */
2269 hsotg->srp_success = 0;
2270
2271 /* Enable common interrupts */
2272 dwc2_enable_common_interrupts(hsotg);
2273
2274 /*
2275 * Do device or host initialization based on mode during PCD and
2276 * HCD initialization
2277 */
2278 if (dwc2_is_host_mode(hsotg)) {
2279 dev_dbg(hsotg->dev, "Host Mode\n");
2280 hsotg->op_state = OTG_STATE_A_HOST;
2281 } else {
2282 dev_dbg(hsotg->dev, "Device Mode\n");
2283 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2284 }
2285
2286 return 0;
2287}
2288
2289/**
2290 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2291 * Host mode
2292 *
2293 * @hsotg: Programming view of DWC_otg controller
2294 *
2295 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2296 * request queues. Host channels are reset to ensure that they are ready for
2297 * performing transfers.
2298 */
2299static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2300{
2301 u32 hcfg, hfir, otgctl;
2302
2303 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2304
2305 /* Restart the Phy Clock */
2306 dwc2_writel(0, hsotg->regs + PCGCTL);
2307
2308 /* Initialize Host Configuration Register */
2309 dwc2_init_fs_ls_pclk_sel(hsotg);
Vardan Mikayelyan38e90022016-11-14 19:17:03 -08002310 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2311 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
John Younb02038fa2016-02-23 19:55:00 -08002312 hcfg = dwc2_readl(hsotg->regs + HCFG);
2313 hcfg |= HCFG_FSLSSUPP;
2314 dwc2_writel(hcfg, hsotg->regs + HCFG);
2315 }
2316
2317 /*
2318 * This bit allows dynamic reloading of the HFIR register during
2319 * runtime. This bit needs to be programmed during initial configuration
2320 * and its value must not be changed during runtime.
2321 */
John Youn95832c02017-01-23 14:57:26 -08002322 if (hsotg->params.reload_ctl) {
John Younb02038fa2016-02-23 19:55:00 -08002323 hfir = dwc2_readl(hsotg->regs + HFIR);
2324 hfir |= HFIR_RLDCTRL;
2325 dwc2_writel(hfir, hsotg->regs + HFIR);
2326 }
2327
John Youn95832c02017-01-23 14:57:26 -08002328 if (hsotg->params.dma_desc_enable) {
John Younb02038fa2016-02-23 19:55:00 -08002329 u32 op_mode = hsotg->hw_params.op_mode;
2330
2331 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2332 !hsotg->hw_params.dma_desc_enable ||
2333 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2334 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2335 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2336 dev_err(hsotg->dev,
2337 "Hardware does not support descriptor DMA mode -\n");
2338 dev_err(hsotg->dev,
2339 "falling back to buffer DMA mode.\n");
John Youn95832c02017-01-23 14:57:26 -08002340 hsotg->params.dma_desc_enable = false;
John Younb02038fa2016-02-23 19:55:00 -08002341 } else {
2342 hcfg = dwc2_readl(hsotg->regs + HCFG);
2343 hcfg |= HCFG_DESCDMA;
2344 dwc2_writel(hcfg, hsotg->regs + HCFG);
2345 }
2346 }
2347
2348 /* Configure data FIFO sizes */
2349 dwc2_config_fifos(hsotg);
2350
2351 /* TODO - check this */
2352 /* Clear Host Set HNP Enable in the OTG Control Register */
2353 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2354 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2355 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2356
2357 /* Make sure the FIFOs are flushed */
2358 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2359 dwc2_flush_rx_fifo(hsotg);
2360
2361 /* Clear Host Set HNP Enable in the OTG Control Register */
2362 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2363 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2364 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2365
John Youn95832c02017-01-23 14:57:26 -08002366 if (!hsotg->params.dma_desc_enable) {
John Younb02038fa2016-02-23 19:55:00 -08002367 int num_channels, i;
2368 u32 hcchar;
2369
2370 /* Flush out any leftover queued requests */
John Younbea8e862016-11-03 17:55:53 -07002371 num_channels = hsotg->params.host_channels;
John Younb02038fa2016-02-23 19:55:00 -08002372 for (i = 0; i < num_channels; i++) {
2373 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2374 hcchar &= ~HCCHAR_CHENA;
2375 hcchar |= HCCHAR_CHDIS;
2376 hcchar &= ~HCCHAR_EPDIR;
2377 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2378 }
2379
2380 /* Halt all channels to put them into a known state */
2381 for (i = 0; i < num_channels; i++) {
2382 int count = 0;
2383
2384 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2385 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2386 hcchar &= ~HCCHAR_EPDIR;
2387 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2388 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2389 __func__, i);
2390 do {
2391 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2392 if (++count > 1000) {
2393 dev_err(hsotg->dev,
2394 "Unable to clear enable on channel %d\n",
2395 i);
2396 break;
2397 }
2398 udelay(1);
2399 } while (hcchar & HCCHAR_CHENA);
2400 }
2401 }
2402
2403 /* Turn on the vbus power */
2404 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2405 if (hsotg->op_state == OTG_STATE_A_HOST) {
2406 u32 hprt0 = dwc2_read_hprt0(hsotg);
2407
2408 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2409 !!(hprt0 & HPRT0_PWR));
2410 if (!(hprt0 & HPRT0_PWR)) {
2411 hprt0 |= HPRT0_PWR;
2412 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2413 }
2414 }
2415
2416 dwc2_enable_host_interrupts(hsotg);
2417}
2418
Paul Zimmerman7359d482013-03-11 17:47:59 -07002419/*
2420 * Initializes dynamic portions of the DWC_otg HCD state
2421 *
2422 * Must be called with interrupt disabled and spinlock held
2423 */
2424static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2425{
2426 struct dwc2_host_chan *chan, *chan_tmp;
2427 int num_channels;
2428 int i;
2429
2430 hsotg->flags.d32 = 0;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002431 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
Dom Cobley20f2eb92013-09-23 14:23:34 -07002432
John Youn95832c02017-01-23 14:57:26 -08002433 if (hsotg->params.uframe_sched) {
Dom Cobley20f2eb92013-09-23 14:23:34 -07002434 hsotg->available_host_channels =
John Younbea8e862016-11-03 17:55:53 -07002435 hsotg->params.host_channels;
Dom Cobley20f2eb92013-09-23 14:23:34 -07002436 } else {
2437 hsotg->non_periodic_channels = 0;
2438 hsotg->periodic_channels = 0;
2439 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07002440
2441 /*
2442 * Put all channels in the free channel list and clean up channel
2443 * states
2444 */
2445 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2446 hc_list_entry)
2447 list_del_init(&chan->hc_list_entry);
2448
John Younbea8e862016-11-03 17:55:53 -07002449 num_channels = hsotg->params.host_channels;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002450 for (i = 0; i < num_channels; i++) {
2451 chan = hsotg->hc_ptr_array[i];
2452 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2453 dwc2_hc_cleanup(hsotg, chan);
2454 }
2455
2456 /* Initialize the DWC core for host mode operation */
2457 dwc2_core_host_init(hsotg);
2458}
2459
2460static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2461 struct dwc2_host_chan *chan,
2462 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2463{
2464 int hub_addr, hub_port;
2465
2466 chan->do_split = 1;
2467 chan->xact_pos = qtd->isoc_split_pos;
2468 chan->complete_split = qtd->complete_split;
2469 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2470 chan->hub_addr = (u8)hub_addr;
2471 chan->hub_port = (u8)hub_port;
2472}
2473
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002474static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2475 struct dwc2_host_chan *chan,
2476 struct dwc2_qtd *qtd)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002477{
2478 struct dwc2_hcd_urb *urb = qtd->urb;
2479 struct dwc2_hcd_iso_packet_desc *frame_desc;
2480
2481 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2482 case USB_ENDPOINT_XFER_CONTROL:
2483 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2484
2485 switch (qtd->control_phase) {
2486 case DWC2_CONTROL_SETUP:
2487 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2488 chan->do_ping = 0;
2489 chan->ep_is_in = 0;
2490 chan->data_pid_start = DWC2_HC_PID_SETUP;
John Youn95832c02017-01-23 14:57:26 -08002491 if (hsotg->params.host_dma)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002492 chan->xfer_dma = urb->setup_dma;
2493 else
2494 chan->xfer_buf = urb->setup_packet;
2495 chan->xfer_len = 8;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002496 break;
2497
2498 case DWC2_CONTROL_DATA:
2499 dev_vdbg(hsotg->dev, " Control data transaction\n");
2500 chan->data_pid_start = qtd->data_toggle;
2501 break;
2502
2503 case DWC2_CONTROL_STATUS:
2504 /*
2505 * Direction is opposite of data direction or IN if no
2506 * data
2507 */
2508 dev_vdbg(hsotg->dev, " Control status transaction\n");
2509 if (urb->length == 0)
2510 chan->ep_is_in = 1;
2511 else
2512 chan->ep_is_in =
2513 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2514 if (chan->ep_is_in)
2515 chan->do_ping = 0;
2516 chan->data_pid_start = DWC2_HC_PID_DATA1;
2517 chan->xfer_len = 0;
John Youn95832c02017-01-23 14:57:26 -08002518 if (hsotg->params.host_dma)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002519 chan->xfer_dma = hsotg->status_buf_dma;
2520 else
2521 chan->xfer_buf = hsotg->status_buf;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002522 break;
2523 }
2524 break;
2525
2526 case USB_ENDPOINT_XFER_BULK:
2527 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2528 break;
2529
2530 case USB_ENDPOINT_XFER_INT:
2531 chan->ep_type = USB_ENDPOINT_XFER_INT;
2532 break;
2533
2534 case USB_ENDPOINT_XFER_ISOC:
2535 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
John Youn95832c02017-01-23 14:57:26 -08002536 if (hsotg->params.dma_desc_enable)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002537 break;
2538
2539 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2540 frame_desc->status = 0;
2541
John Youn95832c02017-01-23 14:57:26 -08002542 if (hsotg->params.host_dma) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07002543 chan->xfer_dma = urb->dma;
2544 chan->xfer_dma += frame_desc->offset +
2545 qtd->isoc_split_offset;
2546 } else {
2547 chan->xfer_buf = urb->buf;
2548 chan->xfer_buf += frame_desc->offset +
2549 qtd->isoc_split_offset;
2550 }
2551
2552 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2553
Paul Zimmerman7359d482013-03-11 17:47:59 -07002554 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2555 if (chan->xfer_len <= 188)
2556 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2557 else
2558 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2559 }
2560 break;
2561 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07002562}
2563
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002564#define DWC2_USB_DMA_ALIGN 4
2565
2566struct dma_aligned_buffer {
2567 void *kmalloc_ptr;
2568 void *old_xfer_buffer;
2569 u8 data[0];
2570};
2571
2572static void dwc2_free_dma_aligned_buffer(struct urb *urb)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002573{
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002574 struct dma_aligned_buffer *temp;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002575
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002576 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2577 return;
Paul Zimmerman5dce9552014-09-16 13:47:27 -07002578
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002579 temp = container_of(urb->transfer_buffer,
John Youn9da51972017-01-17 20:30:27 -08002580 struct dma_aligned_buffer, data);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002581
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002582 if (usb_urb_dir_in(urb))
2583 memcpy(temp->old_xfer_buffer, temp->data,
2584 urb->transfer_buffer_length);
2585 urb->transfer_buffer = temp->old_xfer_buffer;
2586 kfree(temp->kmalloc_ptr);
Paul Zimmerman5dce9552014-09-16 13:47:27 -07002587
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002588 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2589}
Paul Zimmerman7359d482013-03-11 17:47:59 -07002590
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002591static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2592{
2593 struct dma_aligned_buffer *temp, *kmalloc_ptr;
2594 size_t kmalloc_size;
Gregory Herrerodb62b9a2015-04-29 22:09:16 +02002595
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002596 if (urb->num_sgs || urb->sg ||
2597 urb->transfer_buffer_length == 0 ||
2598 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2599 return 0;
2600
2601 /* Allocate a buffer with enough padding for alignment */
2602 kmalloc_size = urb->transfer_buffer_length +
2603 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1;
2604
2605 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2606 if (!kmalloc_ptr)
2607 return -ENOMEM;
2608
2609 /* Position our struct dma_aligned_buffer such that data is aligned */
2610 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1;
2611 temp->kmalloc_ptr = kmalloc_ptr;
2612 temp->old_xfer_buffer = urb->transfer_buffer;
2613 if (usb_urb_dir_out(urb))
2614 memcpy(temp->data, urb->transfer_buffer,
2615 urb->transfer_buffer_length);
2616 urb->transfer_buffer = temp->data;
2617
2618 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2619
Paul Zimmerman7359d482013-03-11 17:47:59 -07002620 return 0;
2621}
2622
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002623static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
John Youn9da51972017-01-17 20:30:27 -08002624 gfp_t mem_flags)
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002625{
2626 int ret;
2627
2628 /* We assume setup_dma is always aligned; warn if not */
2629 WARN_ON_ONCE(urb->setup_dma &&
2630 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2631
2632 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2633 if (ret)
2634 return ret;
2635
2636 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2637 if (ret)
2638 dwc2_free_dma_aligned_buffer(urb);
2639
2640 return ret;
2641}
2642
2643static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2644{
2645 usb_hcd_unmap_urb_for_dma(hcd, urb);
2646 dwc2_free_dma_aligned_buffer(urb);
2647}
2648
Paul Zimmerman7359d482013-03-11 17:47:59 -07002649/**
2650 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2651 * channel and initializes the host channel to perform the transactions. The
2652 * host channel is removed from the free list.
2653 *
2654 * @hsotg: The HCD state structure
2655 * @qh: Transactions from the first QTD for this QH are selected and assigned
2656 * to a free host channel
2657 */
Dom Cobley20f2eb92013-09-23 14:23:34 -07002658static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002659{
2660 struct dwc2_host_chan *chan;
2661 struct dwc2_hcd_urb *urb;
2662 struct dwc2_qtd *qtd;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002663
Matthijs Kooijmanb49977a2013-04-10 09:55:50 +02002664 if (dbg_qh(qh))
2665 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002666
2667 if (list_empty(&qh->qtd_list)) {
2668 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
Dom Cobley20f2eb92013-09-23 14:23:34 -07002669 return -ENOMEM;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002670 }
2671
2672 if (list_empty(&hsotg->free_hc_list)) {
2673 dev_dbg(hsotg->dev, "No free channel to assign\n");
Dom Cobley20f2eb92013-09-23 14:23:34 -07002674 return -ENOMEM;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002675 }
2676
2677 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2678 hc_list_entry);
2679
Dom Cobley20f2eb92013-09-23 14:23:34 -07002680 /* Remove host channel from free list */
Paul Zimmerman7359d482013-03-11 17:47:59 -07002681 list_del_init(&chan->hc_list_entry);
2682
2683 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2684 urb = qtd->urb;
2685 qh->channel = chan;
2686 qtd->in_process = 1;
2687
2688 /*
2689 * Use usb_pipedevice to determine device address. This address is
2690 * 0 before the SET_ADDRESS command and the correct address afterward.
2691 */
2692 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2693 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2694 chan->speed = qh->dev_speed;
2695 chan->max_packet = dwc2_max_packet(qh->maxp);
2696
2697 chan->xfer_started = 0;
2698 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2699 chan->error_state = (qtd->error_count > 0);
2700 chan->halt_on_queue = 0;
2701 chan->halt_pending = 0;
2702 chan->requests = 0;
2703
2704 /*
2705 * The following values may be modified in the transfer type section
2706 * below. The xfer_len value may be reduced when the transfer is
2707 * started to accommodate the max widths of the XferSize and PktCnt
2708 * fields in the HCTSIZn register.
2709 */
2710
2711 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2712 if (chan->ep_is_in)
2713 chan->do_ping = 0;
2714 else
2715 chan->do_ping = qh->ping_state;
2716
2717 chan->data_pid_start = qh->data_toggle;
2718 chan->multi_count = 1;
2719
Rashika Kheriabb6c3422013-10-26 23:11:22 +05302720 if (urb->actual_length > urb->length &&
John Youn9da51972017-01-17 20:30:27 -08002721 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
Paul Zimmerman84181082013-09-23 14:23:33 -07002722 urb->actual_length = urb->length;
2723
John Youn95832c02017-01-23 14:57:26 -08002724 if (hsotg->params.host_dma)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002725 chan->xfer_dma = urb->dma + urb->actual_length;
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002726 else
Paul Zimmerman7359d482013-03-11 17:47:59 -07002727 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002728
2729 chan->xfer_len = urb->length - urb->actual_length;
2730 chan->xfer_count = 0;
2731
2732 /* Set the split attributes if required */
2733 if (qh->do_split)
2734 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2735 else
2736 chan->do_split = 0;
2737
2738 /* Set the transfer attributes */
Douglas Anderson3bc04e22016-01-28 18:19:53 -08002739 dwc2_hc_init_xfer(hsotg, chan, qtd);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002740
2741 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2742 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2743 /*
2744 * This value may be modified when the transfer is started
2745 * to reflect the actual transfer length
2746 */
2747 chan->multi_count = dwc2_hb_mult(qh->maxp);
2748
John Youn95832c02017-01-23 14:57:26 -08002749 if (hsotg->params.dma_desc_enable) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07002750 chan->desc_list_addr = qh->desc_list_dma;
Gregory Herrero95105a92015-11-20 11:49:29 +01002751 chan->desc_list_sz = qh->desc_list_sz;
2752 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07002753
2754 dwc2_hc_init(hsotg, chan);
2755 chan->qh = qh;
Dom Cobley20f2eb92013-09-23 14:23:34 -07002756
2757 return 0;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002758}
2759
2760/**
2761 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2762 * schedule and assigns them to available host channels. Called from the HCD
2763 * interrupt handler functions.
2764 *
2765 * @hsotg: The HCD state structure
2766 *
2767 * Return: The types of new transactions that were assigned to host channels
2768 */
2769enum dwc2_transaction_type dwc2_hcd_select_transactions(
2770 struct dwc2_hsotg *hsotg)
2771{
2772 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2773 struct list_head *qh_ptr;
2774 struct dwc2_qh *qh;
2775 int num_channels;
2776
2777#ifdef DWC2_DEBUG_SOF
2778 dev_vdbg(hsotg->dev, " Select Transactions\n");
2779#endif
2780
2781 /* Process entries in the periodic ready list */
2782 qh_ptr = hsotg->periodic_sched_ready.next;
2783 while (qh_ptr != &hsotg->periodic_sched_ready) {
2784 if (list_empty(&hsotg->free_hc_list))
2785 break;
John Youn95832c02017-01-23 14:57:26 -08002786 if (hsotg->params.uframe_sched) {
Dom Cobley20f2eb92013-09-23 14:23:34 -07002787 if (hsotg->available_host_channels <= 1)
2788 break;
2789 hsotg->available_host_channels--;
2790 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07002791 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
Dom Cobley20f2eb92013-09-23 14:23:34 -07002792 if (dwc2_assign_and_init_hc(hsotg, qh))
2793 break;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002794
2795 /*
2796 * Move the QH from the periodic ready schedule to the
2797 * periodic assigned schedule
2798 */
2799 qh_ptr = qh_ptr->next;
Douglas Anderson94ef7ae2016-01-28 18:19:56 -08002800 list_move_tail(&qh->qh_list_entry,
2801 &hsotg->periodic_sched_assigned);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002802 ret_val = DWC2_TRANSACTION_PERIODIC;
2803 }
2804
2805 /*
2806 * Process entries in the inactive portion of the non-periodic
2807 * schedule. Some free host channels may not be used if they are
2808 * reserved for periodic transfers.
2809 */
John Younbea8e862016-11-03 17:55:53 -07002810 num_channels = hsotg->params.host_channels;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002811 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2812 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
John Youn95832c02017-01-23 14:57:26 -08002813 if (!hsotg->params.uframe_sched &&
Dom Cobley20f2eb92013-09-23 14:23:34 -07002814 hsotg->non_periodic_channels >= num_channels -
Paul Zimmerman7359d482013-03-11 17:47:59 -07002815 hsotg->periodic_channels)
2816 break;
2817 if (list_empty(&hsotg->free_hc_list))
2818 break;
2819 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
John Youn95832c02017-01-23 14:57:26 -08002820 if (hsotg->params.uframe_sched) {
Dom Cobley20f2eb92013-09-23 14:23:34 -07002821 if (hsotg->available_host_channels < 1)
2822 break;
2823 hsotg->available_host_channels--;
2824 }
2825
2826 if (dwc2_assign_and_init_hc(hsotg, qh))
2827 break;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002828
2829 /*
2830 * Move the QH from the non-periodic inactive schedule to the
2831 * non-periodic active schedule
2832 */
2833 qh_ptr = qh_ptr->next;
Douglas Anderson94ef7ae2016-01-28 18:19:56 -08002834 list_move_tail(&qh->qh_list_entry,
2835 &hsotg->non_periodic_sched_active);
Paul Zimmerman7359d482013-03-11 17:47:59 -07002836
2837 if (ret_val == DWC2_TRANSACTION_NONE)
2838 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2839 else
2840 ret_val = DWC2_TRANSACTION_ALL;
2841
John Youn95832c02017-01-23 14:57:26 -08002842 if (!hsotg->params.uframe_sched)
Dom Cobley20f2eb92013-09-23 14:23:34 -07002843 hsotg->non_periodic_channels++;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002844 }
2845
2846 return ret_val;
2847}
2848
2849/**
2850 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2851 * a host channel associated with either a periodic or non-periodic transfer
2852 *
2853 * @hsotg: The HCD state structure
2854 * @chan: Host channel descriptor associated with either a periodic or
2855 * non-periodic transfer
2856 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2857 * for periodic transfers or the non-periodic Tx FIFO
2858 * for non-periodic transfers
2859 *
2860 * Return: 1 if a request is queued and more requests may be needed to
2861 * complete the transfer, 0 if no more requests are required for this
2862 * transfer, -1 if there is insufficient space in the Tx FIFO
2863 *
2864 * This function assumes that there is space available in the appropriate
2865 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2866 * it checks whether space is available in the appropriate Tx FIFO.
2867 *
2868 * Must be called with interrupt disabled and spinlock held
2869 */
2870static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2871 struct dwc2_host_chan *chan,
2872 u16 fifo_dwords_avail)
2873{
2874 int retval = 0;
2875
Douglas Andersonc9c8ac02016-01-28 18:19:57 -08002876 if (chan->do_split)
2877 /* Put ourselves on the list to keep order straight */
2878 list_move_tail(&chan->split_order_list_entry,
2879 &hsotg->split_order);
2880
John Youn95832c02017-01-23 14:57:26 -08002881 if (hsotg->params.host_dma) {
2882 if (hsotg->params.dma_desc_enable) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07002883 if (!chan->xfer_started ||
2884 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2885 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2886 chan->qh->ping_state = 0;
2887 }
2888 } else if (!chan->xfer_started) {
2889 dwc2_hc_start_transfer(hsotg, chan);
2890 chan->qh->ping_state = 0;
2891 }
2892 } else if (chan->halt_pending) {
2893 /* Don't queue a request if the channel has been halted */
2894 } else if (chan->halt_on_queue) {
2895 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2896 } else if (chan->do_ping) {
2897 if (!chan->xfer_started)
2898 dwc2_hc_start_transfer(hsotg, chan);
2899 } else if (!chan->ep_is_in ||
2900 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2901 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2902 if (!chan->xfer_started) {
2903 dwc2_hc_start_transfer(hsotg, chan);
2904 retval = 1;
2905 } else {
2906 retval = dwc2_hc_continue_transfer(hsotg, chan);
2907 }
2908 } else {
2909 retval = -1;
2910 }
2911 } else {
2912 if (!chan->xfer_started) {
2913 dwc2_hc_start_transfer(hsotg, chan);
2914 retval = 1;
2915 } else {
2916 retval = dwc2_hc_continue_transfer(hsotg, chan);
2917 }
2918 }
2919
2920 return retval;
2921}
2922
2923/*
2924 * Processes periodic channels for the next frame and queues transactions for
2925 * these channels to the DWC_otg controller. After queueing transactions, the
2926 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2927 * to queue as Periodic Tx FIFO or request queue space becomes available.
2928 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2929 *
2930 * Must be called with interrupt disabled and spinlock held
2931 */
2932static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2933{
2934 struct list_head *qh_ptr;
2935 struct dwc2_qh *qh;
2936 u32 tx_status;
2937 u32 fspcavail;
2938 u32 gintmsk;
2939 int status;
Douglas Anderson4e50e012016-01-28 18:20:03 -08002940 bool no_queue_space = false;
2941 bool no_fifo_space = false;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002942 u32 qspcavail;
2943
Douglas Anderson4e50e012016-01-28 18:20:03 -08002944 /* If empty list then just adjust interrupt enables */
2945 if (list_empty(&hsotg->periodic_sched_assigned))
2946 goto exit;
2947
Matthijs Kooijmanb49977a2013-04-10 09:55:50 +02002948 if (dbg_perio())
2949 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
Paul Zimmerman7359d482013-03-11 17:47:59 -07002950
Antti Seppälä95c8bc32015-08-20 21:41:07 +03002951 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02002952 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2953 TXSTS_QSPCAVAIL_SHIFT;
2954 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2955 TXSTS_FSPCAVAIL_SHIFT;
Matthijs Kooijmanb49977a2013-04-10 09:55:50 +02002956
2957 if (dbg_perio()) {
2958 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2959 qspcavail);
2960 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2961 fspcavail);
2962 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07002963
2964 qh_ptr = hsotg->periodic_sched_assigned.next;
2965 while (qh_ptr != &hsotg->periodic_sched_assigned) {
Antti Seppälä95c8bc32015-08-20 21:41:07 +03002966 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
Matthijs Kooijmanacdb9042013-08-30 18:45:16 +02002967 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2968 TXSTS_QSPCAVAIL_SHIFT;
2969 if (qspcavail == 0) {
Nicholas Mc Guirefdb09b32017-01-12 16:55:02 +01002970 no_queue_space = true;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002971 break;
2972 }
2973
2974 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2975 if (!qh->channel) {
2976 qh_ptr = qh_ptr->next;
2977 continue;
2978 }
2979
2980 /* Make sure EP's TT buffer is clean before queueing qtds */
2981 if (qh->tt_buffer_dirty) {
2982 qh_ptr = qh_ptr->next;
2983 continue;
2984 }
2985
2986 /*
2987 * Set a flag if we're queuing high-bandwidth in slave mode.
2988 * The flag prevents any halts to get into the request queue in
2989 * the middle of multiple high-bandwidth packets getting queued.
2990 */
John Youn95832c02017-01-23 14:57:26 -08002991 if (!hsotg->params.host_dma &&
John Youn9da51972017-01-17 20:30:27 -08002992 qh->channel->multi_count > 1)
Paul Zimmerman7359d482013-03-11 17:47:59 -07002993 hsotg->queuing_high_bandwidth = 1;
2994
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02002995 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2996 TXSTS_FSPCAVAIL_SHIFT;
Paul Zimmerman7359d482013-03-11 17:47:59 -07002997 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2998 if (status < 0) {
Nicholas Mc Guirefdb09b32017-01-12 16:55:02 +01002999 no_fifo_space = true;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003000 break;
3001 }
3002
3003 /*
3004 * In Slave mode, stay on the current transfer until there is
3005 * nothing more to do or the high-bandwidth request count is
3006 * reached. In DMA mode, only need to queue one request. The
3007 * controller automatically handles multiple packets for
3008 * high-bandwidth transfers.
3009 */
John Youn95832c02017-01-23 14:57:26 -08003010 if (hsotg->params.host_dma || status == 0 ||
Paul Zimmerman7359d482013-03-11 17:47:59 -07003011 qh->channel->requests == qh->channel->multi_count) {
3012 qh_ptr = qh_ptr->next;
3013 /*
3014 * Move the QH from the periodic assigned schedule to
3015 * the periodic queued schedule
3016 */
Douglas Anderson94ef7ae2016-01-28 18:19:56 -08003017 list_move_tail(&qh->qh_list_entry,
3018 &hsotg->periodic_sched_queued);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003019
3020 /* done queuing high bandwidth */
3021 hsotg->queuing_high_bandwidth = 0;
3022 }
3023 }
3024
Douglas Anderson4e50e012016-01-28 18:20:03 -08003025exit:
3026 if (no_queue_space || no_fifo_space ||
John Youn95832c02017-01-23 14:57:26 -08003027 (!hsotg->params.host_dma &&
Douglas Anderson4e50e012016-01-28 18:20:03 -08003028 !list_empty(&hsotg->periodic_sched_assigned))) {
3029 /*
3030 * May need to queue more transactions as the request
3031 * queue or Tx FIFO empties. Enable the periodic Tx
3032 * FIFO empty interrupt. (Always use the half-empty
3033 * level to ensure that new requests are loaded as
3034 * soon as possible.)
3035 */
3036 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3037 if (!(gintmsk & GINTSTS_PTXFEMP)) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07003038 gintmsk |= GINTSTS_PTXFEMP;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003039 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
Douglas Anderson4e50e012016-01-28 18:20:03 -08003040 }
3041 } else {
3042 /*
3043 * Disable the Tx FIFO empty interrupt since there are
3044 * no more transactions that need to be queued right
3045 * now. This function is called from interrupt
3046 * handlers to queue more transactions as transfer
3047 * states change.
John Youn38beaec2017-01-17 20:31:13 -08003048 */
Douglas Anderson4e50e012016-01-28 18:20:03 -08003049 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3050 if (gintmsk & GINTSTS_PTXFEMP) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07003051 gintmsk &= ~GINTSTS_PTXFEMP;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003052 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003053 }
3054 }
3055}
3056
3057/*
3058 * Processes active non-periodic channels and queues transactions for these
3059 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3060 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3061 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3062 * FIFO Empty interrupt is disabled.
3063 *
3064 * Must be called with interrupt disabled and spinlock held
3065 */
3066static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3067{
3068 struct list_head *orig_qh_ptr;
3069 struct dwc2_qh *qh;
3070 u32 tx_status;
3071 u32 qspcavail;
3072 u32 fspcavail;
3073 u32 gintmsk;
3074 int status;
3075 int no_queue_space = 0;
3076 int no_fifo_space = 0;
3077 int more_to_do = 0;
3078
3079 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3080
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003081 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003082 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3083 TXSTS_QSPCAVAIL_SHIFT;
3084 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3085 TXSTS_FSPCAVAIL_SHIFT;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003086 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3087 qspcavail);
3088 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3089 fspcavail);
3090
3091 /*
3092 * Keep track of the starting point. Skip over the start-of-list
3093 * entry.
3094 */
3095 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3096 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3097 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3098
3099 /*
3100 * Process once through the active list or until no more space is
3101 * available in the request queue or the Tx FIFO
3102 */
3103 do {
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003104 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003105 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3106 TXSTS_QSPCAVAIL_SHIFT;
John Youn95832c02017-01-23 14:57:26 -08003107 if (!hsotg->params.host_dma && qspcavail == 0) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07003108 no_queue_space = 1;
3109 break;
3110 }
3111
3112 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3113 qh_list_entry);
3114 if (!qh->channel)
3115 goto next;
3116
3117 /* Make sure EP's TT buffer is clean before queueing qtds */
3118 if (qh->tt_buffer_dirty)
3119 goto next;
3120
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3122 TXSTS_FSPCAVAIL_SHIFT;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3124
3125 if (status > 0) {
3126 more_to_do = 1;
3127 } else if (status < 0) {
3128 no_fifo_space = 1;
3129 break;
3130 }
3131next:
3132 /* Advance to next QH, skipping start-of-list entry */
3133 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3134 if (hsotg->non_periodic_qh_ptr ==
3135 &hsotg->non_periodic_sched_active)
3136 hsotg->non_periodic_qh_ptr =
3137 hsotg->non_periodic_qh_ptr->next;
3138 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3139
John Youn95832c02017-01-23 14:57:26 -08003140 if (!hsotg->params.host_dma) {
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003141 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003142 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3143 TXSTS_QSPCAVAIL_SHIFT;
3144 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3145 TXSTS_FSPCAVAIL_SHIFT;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003146 dev_vdbg(hsotg->dev,
3147 " NP Tx Req Queue Space Avail (after queue): %d\n",
3148 qspcavail);
3149 dev_vdbg(hsotg->dev,
3150 " NP Tx FIFO Space Avail (after queue): %d\n",
3151 fspcavail);
3152
3153 if (more_to_do || no_queue_space || no_fifo_space) {
3154 /*
3155 * May need to queue more transactions as the request
3156 * queue or Tx FIFO empties. Enable the non-periodic
3157 * Tx FIFO empty interrupt. (Always use the half-empty
3158 * level to ensure that new requests are loaded as
3159 * soon as possible.)
3160 */
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003161 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003162 gintmsk |= GINTSTS_NPTXFEMP;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003163 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003164 } else {
3165 /*
3166 * Disable the Tx FIFO empty interrupt since there are
3167 * no more transactions that need to be queued right
3168 * now. This function is called from interrupt
3169 * handlers to queue more transactions as transfer
3170 * states change.
3171 */
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003172 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003173 gintmsk &= ~GINTSTS_NPTXFEMP;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003174 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003175 }
3176 }
3177}
3178
3179/**
3180 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3181 * and queues transactions for these channels to the DWC_otg controller. Called
3182 * from the HCD interrupt handler functions.
3183 *
3184 * @hsotg: The HCD state structure
3185 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3186 * or both)
3187 *
3188 * Must be called with interrupt disabled and spinlock held
3189 */
3190void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3191 enum dwc2_transaction_type tr_type)
3192{
3193#ifdef DWC2_DEBUG_SOF
3194 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3195#endif
3196 /* Process host channels associated with periodic transfers */
Douglas Anderson4e50e012016-01-28 18:20:03 -08003197 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3198 tr_type == DWC2_TRANSACTION_ALL)
Paul Zimmerman7359d482013-03-11 17:47:59 -07003199 dwc2_process_periodic_channels(hsotg);
3200
3201 /* Process host channels associated with non-periodic transfers */
3202 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3203 tr_type == DWC2_TRANSACTION_ALL) {
3204 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3205 dwc2_process_non_periodic_channels(hsotg);
3206 } else {
3207 /*
3208 * Ensure NP Tx FIFO empty interrupt is disabled when
3209 * there are no non-periodic transfers to process
3210 */
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003211 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003212
3213 gintmsk &= ~GINTSTS_NPTXFEMP;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003214 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003215 }
3216 }
3217}
3218
3219static void dwc2_conn_id_status_change(struct work_struct *work)
3220{
3221 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3222 wf_otg);
3223 u32 count = 0;
3224 u32 gotgctl;
Mian Yousaf Kaukab5390d432015-09-29 12:08:25 +02003225 unsigned long flags;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003226
3227 dev_dbg(hsotg->dev, "%s()\n", __func__);
3228
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003229 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003230 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3231 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3232 !!(gotgctl & GOTGCTL_CONID_B));
3233
3234 /* B-Device connector (Device Mode) */
3235 if (gotgctl & GOTGCTL_CONID_B) {
3236 /* Wait for switch to device mode */
3237 dev_dbg(hsotg->dev, "connId B\n");
Chen Yu9156a7e2017-01-23 14:59:57 -08003238 if (hsotg->bus_suspended) {
3239 dev_info(hsotg->dev,
3240 "Do port resume before switching to device mode\n");
3241 dwc2_port_resume(hsotg);
3242 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07003243 while (!dwc2_is_device_mode(hsotg)) {
3244 dev_info(hsotg->dev,
3245 "Waiting for Peripheral Mode, Mode=%s\n",
3246 dwc2_is_host_mode(hsotg) ? "Host" :
3247 "Peripheral");
Nicholas Mc Guire04a9db72017-01-12 16:54:03 +01003248 msleep(20);
John Stultzfc30c4b2017-01-23 14:59:35 -08003249 /*
3250 * Sometimes the initial GOTGCTRL read is wrong, so
3251 * check it again and jump to host mode if that was
3252 * the case.
3253 */
3254 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3255 if (!(gotgctl & GOTGCTL_CONID_B))
3256 goto host;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003257 if (++count > 250)
3258 break;
3259 }
3260 if (count > 250)
3261 dev_err(hsotg->dev,
Paul Zimmermande9169a2013-04-22 14:00:17 -07003262 "Connection id status change timed out\n");
Paul Zimmerman7359d482013-03-11 17:47:59 -07003263 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
Douglas Anderson0fe239b2015-12-17 11:14:40 -08003264 dwc2_core_init(hsotg, false);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003265 dwc2_enable_global_interrupts(hsotg);
Mian Yousaf Kaukab5390d432015-09-29 12:08:25 +02003266 spin_lock_irqsave(&hsotg->lock, flags);
John Stultzdad3f792017-02-13 20:08:08 -08003267 dwc2_hsotg_disconnect(hsotg);
Felipe Balbi1f91b4c2015-08-06 18:11:54 -05003268 dwc2_hsotg_core_init_disconnected(hsotg, false);
Mian Yousaf Kaukab5390d432015-09-29 12:08:25 +02003269 spin_unlock_irqrestore(&hsotg->lock, flags);
Felipe Balbi1f91b4c2015-08-06 18:11:54 -05003270 dwc2_hsotg_core_connect(hsotg);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003271 } else {
John Stultzfc30c4b2017-01-23 14:59:35 -08003272host:
Paul Zimmerman7359d482013-03-11 17:47:59 -07003273 /* A-Device connector (Host Mode) */
3274 dev_dbg(hsotg->dev, "connId A\n");
3275 while (!dwc2_is_host_mode(hsotg)) {
3276 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3277 dwc2_is_host_mode(hsotg) ?
3278 "Host" : "Peripheral");
Nicholas Mc Guire04a9db72017-01-12 16:54:03 +01003279 msleep(20);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003280 if (++count > 250)
3281 break;
3282 }
3283 if (count > 250)
3284 dev_err(hsotg->dev,
Paul Zimmermande9169a2013-04-22 14:00:17 -07003285 "Connection id status change timed out\n");
Paul Zimmerman7359d482013-03-11 17:47:59 -07003286 hsotg->op_state = OTG_STATE_A_HOST;
3287
3288 /* Initialize the Core for Host mode */
Douglas Anderson0fe239b2015-12-17 11:14:40 -08003289 dwc2_core_init(hsotg, false);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003290 dwc2_enable_global_interrupts(hsotg);
3291 dwc2_hcd_start(hsotg);
3292 }
3293}
3294
3295static void dwc2_wakeup_detected(unsigned long data)
3296{
3297 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
3298 u32 hprt0;
3299
3300 dev_dbg(hsotg->dev, "%s()\n", __func__);
3301
3302 /*
3303 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3304 * so that OPT tests pass with all PHYs.)
3305 */
3306 hprt0 = dwc2_read_hprt0(hsotg);
3307 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3308 hprt0 &= ~HPRT0_RES;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003309 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003310 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003311 dwc2_readl(hsotg->regs + HPRT0));
Paul Zimmerman7359d482013-03-11 17:47:59 -07003312
3313 dwc2_hcd_rem_wakeup(hsotg);
Nicholas Mc Guirefdb09b32017-01-12 16:55:02 +01003314 hsotg->bus_suspended = false;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003315
3316 /* Change to L0 state */
3317 hsotg->lx_state = DWC2_L0;
3318}
3319
3320static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3321{
3322 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3323
3324 return hcd->self.b_hnp_enable;
3325}
3326
3327/* Must NOT be called with interrupt disabled or spinlock held */
3328static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3329{
3330 unsigned long flags;
3331 u32 hprt0;
3332 u32 pcgctl;
3333 u32 gotgctl;
3334
3335 dev_dbg(hsotg->dev, "%s()\n", __func__);
3336
3337 spin_lock_irqsave(&hsotg->lock, flags);
3338
3339 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003340 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003341 gotgctl |= GOTGCTL_HSTSETHNPEN;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003342 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003343 hsotg->op_state = OTG_STATE_A_SUSPEND;
3344 }
3345
3346 hprt0 = dwc2_read_hprt0(hsotg);
3347 hprt0 |= HPRT0_SUSP;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003348 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003349
Nicholas Mc Guirefdb09b32017-01-12 16:55:02 +01003350 hsotg->bus_suspended = true;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003351
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02003352 /*
3353 * If hibernation is supported, Phy clock will be suspended
3354 * after registers are backuped.
3355 */
John Younbea8e862016-11-03 17:55:53 -07003356 if (!hsotg->params.hibernation) {
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02003357 /* Suspend the Phy Clock */
3358 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3359 pcgctl |= PCGCTL_STOPPCLK;
3360 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3361 udelay(10);
3362 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07003363
3364 /* For HNP the bus must be suspended for at least 200ms */
3365 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003366 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003367 pcgctl &= ~PCGCTL_STOPPCLK;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003368 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003369
3370 spin_unlock_irqrestore(&hsotg->lock, flags);
3371
Nicholas Mc Guire04a9db72017-01-12 16:54:03 +01003372 msleep(200);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003373 } else {
3374 spin_unlock_irqrestore(&hsotg->lock, flags);
3375 }
3376}
3377
Gregory Herrero30db1032015-09-22 15:16:38 +02003378/* Must NOT be called with interrupt disabled or spinlock held */
3379static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3380{
3381 unsigned long flags;
3382 u32 hprt0;
3383 u32 pcgctl;
3384
Douglas Anderson4d273c22015-10-14 15:58:27 -07003385 spin_lock_irqsave(&hsotg->lock, flags);
3386
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02003387 /*
3388 * If hibernation is supported, Phy clock is already resumed
3389 * after registers restore.
3390 */
John Younbea8e862016-11-03 17:55:53 -07003391 if (!hsotg->params.hibernation) {
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02003392 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3393 pcgctl &= ~PCGCTL_STOPPCLK;
3394 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
Douglas Anderson4d273c22015-10-14 15:58:27 -07003395 spin_unlock_irqrestore(&hsotg->lock, flags);
Nicholas Mc Guire04a9db72017-01-12 16:54:03 +01003396 msleep(20);
Douglas Anderson4d273c22015-10-14 15:58:27 -07003397 spin_lock_irqsave(&hsotg->lock, flags);
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02003398 }
Gregory Herrero30db1032015-09-22 15:16:38 +02003399
Gregory Herrero30db1032015-09-22 15:16:38 +02003400 hprt0 = dwc2_read_hprt0(hsotg);
3401 hprt0 |= HPRT0_RES;
3402 hprt0 &= ~HPRT0_SUSP;
3403 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3404 spin_unlock_irqrestore(&hsotg->lock, flags);
3405
3406 msleep(USB_RESUME_TIMEOUT);
3407
3408 spin_lock_irqsave(&hsotg->lock, flags);
3409 hprt0 = dwc2_read_hprt0(hsotg);
3410 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3411 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Nicholas Mc Guirefdb09b32017-01-12 16:55:02 +01003412 hsotg->bus_suspended = false;
Gregory Herrero30db1032015-09-22 15:16:38 +02003413 spin_unlock_irqrestore(&hsotg->lock, flags);
3414}
3415
Paul Zimmerman7359d482013-03-11 17:47:59 -07003416/* Handles hub class-specific requests */
3417static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3418 u16 wvalue, u16 windex, char *buf, u16 wlength)
3419{
3420 struct usb_hub_descriptor *hub_desc;
3421 int retval = 0;
3422 u32 hprt0;
3423 u32 port_status;
3424 u32 speed;
3425 u32 pcgctl;
3426
3427 switch (typereq) {
3428 case ClearHubFeature:
3429 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3430
3431 switch (wvalue) {
3432 case C_HUB_LOCAL_POWER:
3433 case C_HUB_OVER_CURRENT:
3434 /* Nothing required here */
3435 break;
3436
3437 default:
3438 retval = -EINVAL;
3439 dev_err(hsotg->dev,
3440 "ClearHubFeature request %1xh unknown\n",
3441 wvalue);
3442 }
3443 break;
3444
3445 case ClearPortFeature:
3446 if (wvalue != USB_PORT_FEAT_L1)
3447 if (!windex || windex > 1)
3448 goto error;
3449 switch (wvalue) {
3450 case USB_PORT_FEAT_ENABLE:
3451 dev_dbg(hsotg->dev,
3452 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3453 hprt0 = dwc2_read_hprt0(hsotg);
3454 hprt0 |= HPRT0_ENA;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003455 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003456 break;
3457
3458 case USB_PORT_FEAT_SUSPEND:
3459 dev_dbg(hsotg->dev,
3460 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
Paul Zimmermanb0bb9bb2015-01-15 19:21:46 +00003461
Gregory Herrerobea78552015-09-22 15:16:44 +02003462 if (hsotg->bus_suspended)
3463 dwc2_port_resume(hsotg);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003464 break;
3465
3466 case USB_PORT_FEAT_POWER:
3467 dev_dbg(hsotg->dev,
3468 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3469 hprt0 = dwc2_read_hprt0(hsotg);
3470 hprt0 &= ~HPRT0_PWR;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003471 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003472 break;
3473
3474 case USB_PORT_FEAT_INDICATOR:
3475 dev_dbg(hsotg->dev,
3476 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3477 /* Port indicator not supported */
3478 break;
3479
3480 case USB_PORT_FEAT_C_CONNECTION:
3481 /*
3482 * Clears driver's internal Connect Status Change flag
3483 */
3484 dev_dbg(hsotg->dev,
3485 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3486 hsotg->flags.b.port_connect_status_change = 0;
3487 break;
3488
3489 case USB_PORT_FEAT_C_RESET:
3490 /* Clears driver's internal Port Reset Change flag */
3491 dev_dbg(hsotg->dev,
3492 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3493 hsotg->flags.b.port_reset_change = 0;
3494 break;
3495
3496 case USB_PORT_FEAT_C_ENABLE:
3497 /*
3498 * Clears the driver's internal Port Enable/Disable
3499 * Change flag
3500 */
3501 dev_dbg(hsotg->dev,
3502 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3503 hsotg->flags.b.port_enable_change = 0;
3504 break;
3505
3506 case USB_PORT_FEAT_C_SUSPEND:
3507 /*
3508 * Clears the driver's internal Port Suspend Change
3509 * flag, which is set when resume signaling on the host
3510 * port is complete
3511 */
3512 dev_dbg(hsotg->dev,
3513 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3514 hsotg->flags.b.port_suspend_change = 0;
3515 break;
3516
3517 case USB_PORT_FEAT_C_PORT_L1:
3518 dev_dbg(hsotg->dev,
3519 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3520 hsotg->flags.b.port_l1_change = 0;
3521 break;
3522
3523 case USB_PORT_FEAT_C_OVER_CURRENT:
3524 dev_dbg(hsotg->dev,
3525 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3526 hsotg->flags.b.port_over_current_change = 0;
3527 break;
3528
3529 default:
3530 retval = -EINVAL;
3531 dev_err(hsotg->dev,
3532 "ClearPortFeature request %1xh unknown or unsupported\n",
3533 wvalue);
3534 }
3535 break;
3536
3537 case GetHubDescriptor:
3538 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3539 hub_desc = (struct usb_hub_descriptor *)buf;
3540 hub_desc->bDescLength = 9;
Sergei Shtylyova5dd0392015-03-29 01:36:28 +03003541 hub_desc->bDescriptorType = USB_DT_HUB;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003542 hub_desc->bNbrPorts = 1;
Sergei Shtylyov3d040de2015-01-19 01:54:15 +03003543 hub_desc->wHubCharacteristics =
3544 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3545 HUB_CHAR_INDV_PORT_OCPM);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003546 hub_desc->bPwrOn2PwrGood = 1;
3547 hub_desc->bHubContrCurrent = 0;
3548 hub_desc->u.hs.DeviceRemovable[0] = 0;
3549 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3550 break;
3551
3552 case GetHubStatus:
3553 dev_dbg(hsotg->dev, "GetHubStatus\n");
3554 memset(buf, 0, 4);
3555 break;
3556
3557 case GetPortStatus:
Paul Zimmermanb8313412013-05-24 16:32:12 -07003558 dev_vdbg(hsotg->dev,
3559 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3560 hsotg->flags.d32);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003561 if (!windex || windex > 1)
3562 goto error;
3563
3564 port_status = 0;
3565 if (hsotg->flags.b.port_connect_status_change)
3566 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3567 if (hsotg->flags.b.port_enable_change)
3568 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3569 if (hsotg->flags.b.port_suspend_change)
3570 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3571 if (hsotg->flags.b.port_l1_change)
3572 port_status |= USB_PORT_STAT_C_L1 << 16;
3573 if (hsotg->flags.b.port_reset_change)
3574 port_status |= USB_PORT_STAT_C_RESET << 16;
3575 if (hsotg->flags.b.port_over_current_change) {
3576 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3577 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3578 }
3579
3580 if (!hsotg->flags.b.port_connect_status) {
3581 /*
3582 * The port is disconnected, which means the core is
3583 * either in device mode or it soon will be. Just
3584 * return 0's for the remainder of the port status
3585 * since the port register can't be read if the core
3586 * is in device mode.
3587 */
3588 *(__le32 *)buf = cpu_to_le32(port_status);
3589 break;
3590 }
3591
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003592 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
Paul Zimmermanb8313412013-05-24 16:32:12 -07003593 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003594
3595 if (hprt0 & HPRT0_CONNSTS)
3596 port_status |= USB_PORT_STAT_CONNECTION;
3597 if (hprt0 & HPRT0_ENA)
3598 port_status |= USB_PORT_STAT_ENABLE;
3599 if (hprt0 & HPRT0_SUSP)
3600 port_status |= USB_PORT_STAT_SUSPEND;
3601 if (hprt0 & HPRT0_OVRCURRACT)
3602 port_status |= USB_PORT_STAT_OVERCURRENT;
3603 if (hprt0 & HPRT0_RST)
3604 port_status |= USB_PORT_STAT_RESET;
3605 if (hprt0 & HPRT0_PWR)
3606 port_status |= USB_PORT_STAT_POWER;
3607
Matthijs Kooijmanf9234632013-08-30 18:45:13 +02003608 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003609 if (speed == HPRT0_SPD_HIGH_SPEED)
3610 port_status |= USB_PORT_STAT_HIGH_SPEED;
3611 else if (speed == HPRT0_SPD_LOW_SPEED)
3612 port_status |= USB_PORT_STAT_LOW_SPEED;
3613
3614 if (hprt0 & HPRT0_TSTCTL_MASK)
3615 port_status |= USB_PORT_STAT_TEST;
3616 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3617
John Younbea8e862016-11-03 17:55:53 -07003618 if (hsotg->params.dma_desc_fs_enable) {
Mian Yousaf Kaukabfbb9e222015-11-20 11:49:28 +01003619 /*
3620 * Enable descriptor DMA only if a full speed
3621 * device is connected.
3622 */
3623 if (hsotg->new_connection &&
3624 ((port_status &
3625 (USB_PORT_STAT_CONNECTION |
3626 USB_PORT_STAT_HIGH_SPEED |
3627 USB_PORT_STAT_LOW_SPEED)) ==
3628 USB_PORT_STAT_CONNECTION)) {
3629 u32 hcfg;
3630
3631 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
John Youn95832c02017-01-23 14:57:26 -08003632 hsotg->params.dma_desc_enable = true;
Mian Yousaf Kaukabfbb9e222015-11-20 11:49:28 +01003633 hcfg = dwc2_readl(hsotg->regs + HCFG);
3634 hcfg |= HCFG_DESCDMA;
3635 dwc2_writel(hcfg, hsotg->regs + HCFG);
3636 hsotg->new_connection = false;
3637 }
3638 }
3639
Paul Zimmermanb8313412013-05-24 16:32:12 -07003640 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003641 *(__le32 *)buf = cpu_to_le32(port_status);
3642 break;
3643
3644 case SetHubFeature:
3645 dev_dbg(hsotg->dev, "SetHubFeature\n");
3646 /* No HUB features supported */
3647 break;
3648
3649 case SetPortFeature:
3650 dev_dbg(hsotg->dev, "SetPortFeature\n");
3651 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3652 goto error;
3653
3654 if (!hsotg->flags.b.port_connect_status) {
3655 /*
3656 * The port is disconnected, which means the core is
3657 * either in device mode or it soon will be. Just
3658 * return without doing anything since the port
3659 * register can't be written if the core is in device
3660 * mode.
3661 */
3662 break;
3663 }
3664
3665 switch (wvalue) {
3666 case USB_PORT_FEAT_SUSPEND:
3667 dev_dbg(hsotg->dev,
3668 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3669 if (windex != hsotg->otg_port)
3670 goto error;
3671 dwc2_port_suspend(hsotg, windex);
3672 break;
3673
3674 case USB_PORT_FEAT_POWER:
3675 dev_dbg(hsotg->dev,
3676 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3677 hprt0 = dwc2_read_hprt0(hsotg);
3678 hprt0 |= HPRT0_PWR;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003679 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003680 break;
3681
3682 case USB_PORT_FEAT_RESET:
3683 hprt0 = dwc2_read_hprt0(hsotg);
3684 dev_dbg(hsotg->dev,
3685 "SetPortFeature - USB_PORT_FEAT_RESET\n");
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003686 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003687 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003688 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003689 /* ??? Original driver does this */
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003690 dwc2_writel(0, hsotg->regs + PCGCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003691
3692 hprt0 = dwc2_read_hprt0(hsotg);
3693 /* Clear suspend bit if resetting from suspend state */
3694 hprt0 &= ~HPRT0_SUSP;
3695
3696 /*
3697 * When B-Host the Port reset bit is set in the Start
3698 * HCD Callback function, so that the reset is started
3699 * within 1ms of the HNP success interrupt
3700 */
3701 if (!dwc2_hcd_is_b_host(hsotg)) {
3702 hprt0 |= HPRT0_PWR | HPRT0_RST;
3703 dev_dbg(hsotg->dev,
3704 "In host mode, hprt0=%08x\n", hprt0);
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003705 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003706 }
3707
3708 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
Nicholas Mc Guire04a9db72017-01-12 16:54:03 +01003709 msleep(50);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003710 hprt0 &= ~HPRT0_RST;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003711 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003712 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3713 break;
3714
3715 case USB_PORT_FEAT_INDICATOR:
3716 dev_dbg(hsotg->dev,
3717 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3718 /* Not supported */
3719 break;
3720
Jingwu Lin96d480e2015-04-29 22:09:17 +02003721 case USB_PORT_FEAT_TEST:
3722 hprt0 = dwc2_read_hprt0(hsotg);
3723 dev_dbg(hsotg->dev,
3724 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3725 hprt0 &= ~HPRT0_TSTCTL_MASK;
3726 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003727 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Jingwu Lin96d480e2015-04-29 22:09:17 +02003728 break;
3729
Paul Zimmerman7359d482013-03-11 17:47:59 -07003730 default:
3731 retval = -EINVAL;
3732 dev_err(hsotg->dev,
3733 "SetPortFeature %1xh unknown or unsupported\n",
3734 wvalue);
3735 break;
3736 }
3737 break;
3738
3739 default:
3740error:
3741 retval = -EINVAL;
3742 dev_dbg(hsotg->dev,
3743 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3744 typereq, windex, wvalue);
3745 break;
3746 }
3747
3748 return retval;
3749}
3750
3751static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3752{
3753 int retval;
3754
Paul Zimmerman7359d482013-03-11 17:47:59 -07003755 if (port != 1)
3756 return -EINVAL;
3757
3758 retval = (hsotg->flags.b.port_connect_status_change ||
3759 hsotg->flags.b.port_reset_change ||
3760 hsotg->flags.b.port_enable_change ||
3761 hsotg->flags.b.port_suspend_change ||
3762 hsotg->flags.b.port_over_current_change);
3763
3764 if (retval) {
3765 dev_dbg(hsotg->dev,
3766 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3767 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3768 hsotg->flags.b.port_connect_status_change);
3769 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3770 hsotg->flags.b.port_reset_change);
3771 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3772 hsotg->flags.b.port_enable_change);
3773 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3774 hsotg->flags.b.port_suspend_change);
3775 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3776 hsotg->flags.b.port_over_current_change);
3777 }
3778
3779 return retval;
3780}
3781
3782int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3783{
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003784 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003785
3786#ifdef DWC2_DEBUG_SOF
3787 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003788 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003789#endif
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003790 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003791}
3792
Douglas Andersonfae4e822016-01-28 18:20:10 -08003793int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3794{
3795 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3796 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3797 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3798 unsigned int us_per_frame;
3799 unsigned int frame_number;
3800 unsigned int remaining;
3801 unsigned int interval;
3802 unsigned int phy_clks;
3803
3804 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3805 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3806
3807 /* Extract fields */
3808 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3809 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3810 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3811
3812 /*
3813 * Number of phy clocks since the last tick of the frame number after
3814 * "us" has passed.
3815 */
3816 phy_clks = (interval - remaining) +
3817 DIV_ROUND_UP(interval * us, us_per_frame);
3818
3819 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3820}
3821
Paul Zimmerman7359d482013-03-11 17:47:59 -07003822int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3823{
Aldo Iljazi6bf2e2a2013-11-30 19:33:57 +02003824 return hsotg->op_state == OTG_STATE_B_HOST;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003825}
3826
3827static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3828 int iso_desc_count,
3829 gfp_t mem_flags)
3830{
3831 struct dwc2_hcd_urb *urb;
3832 u32 size = sizeof(*urb) + iso_desc_count *
3833 sizeof(struct dwc2_hcd_iso_packet_desc);
3834
3835 urb = kzalloc(size, mem_flags);
3836 if (urb)
3837 urb->packet_count = iso_desc_count;
3838 return urb;
3839}
3840
3841static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3842 struct dwc2_hcd_urb *urb, u8 dev_addr,
3843 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3844{
Matthijs Kooijmanb49977a2013-04-10 09:55:50 +02003845 if (dbg_perio() ||
3846 ep_type == USB_ENDPOINT_XFER_BULK ||
3847 ep_type == USB_ENDPOINT_XFER_CONTROL)
3848 dev_vdbg(hsotg->dev,
3849 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3850 dev_addr, ep_num, ep_dir, ep_type, mps);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003851 urb->pipe_info.dev_addr = dev_addr;
3852 urb->pipe_info.ep_num = ep_num;
3853 urb->pipe_info.pipe_type = ep_type;
3854 urb->pipe_info.pipe_dir = ep_dir;
3855 urb->pipe_info.mps = mps;
3856}
3857
3858/*
3859 * NOTE: This function will be removed once the peripheral controller code
3860 * is integrated and the driver is stable
3861 */
3862void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3863{
3864#ifdef DEBUG
3865 struct dwc2_host_chan *chan;
3866 struct dwc2_hcd_urb *urb;
3867 struct dwc2_qtd *qtd;
3868 int num_channels;
3869 u32 np_tx_status;
3870 u32 p_tx_status;
3871 int i;
3872
John Younbea8e862016-11-03 17:55:53 -07003873 num_channels = hsotg->params.host_channels;
Paul Zimmerman7359d482013-03-11 17:47:59 -07003874 dev_dbg(hsotg->dev, "\n");
3875 dev_dbg(hsotg->dev,
3876 "************************************************************\n");
3877 dev_dbg(hsotg->dev, "HCD State:\n");
3878 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3879
3880 for (i = 0; i < num_channels; i++) {
3881 chan = hsotg->hc_ptr_array[i];
3882 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3883 dev_dbg(hsotg->dev,
3884 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3885 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3886 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3887 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3888 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3889 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3890 chan->data_pid_start);
3891 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3892 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3893 chan->xfer_started);
3894 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3895 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3896 (unsigned long)chan->xfer_dma);
3897 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3898 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3899 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3900 chan->halt_on_queue);
3901 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3902 chan->halt_pending);
3903 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3904 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3905 dev_dbg(hsotg->dev, " complete_split: %d\n",
3906 chan->complete_split);
3907 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3908 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3909 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3910 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3911 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3912
3913 if (chan->xfer_started) {
3914 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3915
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003916 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3917 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
3918 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
3919 hcint = dwc2_readl(hsotg->regs + HCINT(i));
3920 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
Paul Zimmerman7359d482013-03-11 17:47:59 -07003921 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3922 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3923 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3924 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3925 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3926 }
3927
3928 if (!(chan->xfer_started && chan->qh))
3929 continue;
3930
3931 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3932 if (!qtd->in_process)
3933 break;
3934 urb = qtd->urb;
3935 dev_dbg(hsotg->dev, " URB Info:\n");
3936 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3937 qtd, urb);
3938 if (urb) {
3939 dev_dbg(hsotg->dev,
3940 " Dev: %d, EP: %d %s\n",
3941 dwc2_hcd_get_dev_addr(&urb->pipe_info),
3942 dwc2_hcd_get_ep_num(&urb->pipe_info),
3943 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3944 "IN" : "OUT");
3945 dev_dbg(hsotg->dev,
3946 " Max packet size: %d\n",
3947 dwc2_hcd_get_mps(&urb->pipe_info));
3948 dev_dbg(hsotg->dev,
3949 " transfer_buffer: %p\n",
3950 urb->buf);
Paul Zimmerman157dfaa2013-03-14 13:12:00 -07003951 dev_dbg(hsotg->dev,
3952 " transfer_dma: %08lx\n",
3953 (unsigned long)urb->dma);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003954 dev_dbg(hsotg->dev,
3955 " transfer_buffer_length: %d\n",
3956 urb->length);
3957 dev_dbg(hsotg->dev, " actual_length: %d\n",
3958 urb->actual_length);
3959 }
3960 }
3961 }
3962
3963 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3964 hsotg->non_periodic_channels);
3965 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3966 hsotg->periodic_channels);
3967 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003968 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003969 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003970 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003971 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003972 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
Antti Seppälä95c8bc32015-08-20 21:41:07 +03003973 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003974 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003975 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003976 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
Matthijs Kooijmand6ec53e2013-08-30 18:45:15 +02003977 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
Paul Zimmerman7359d482013-03-11 17:47:59 -07003978 dwc2_hcd_dump_frrem(hsotg);
3979 dwc2_dump_global_registers(hsotg);
3980 dwc2_dump_host_registers(hsotg);
3981 dev_dbg(hsotg->dev,
3982 "************************************************************\n");
3983 dev_dbg(hsotg->dev, "\n");
3984#endif
3985}
3986
3987/*
3988 * NOTE: This function will be removed once the peripheral controller code
3989 * is integrated and the driver is stable
3990 */
3991void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
3992{
3993#ifdef DWC2_DUMP_FRREM
3994 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
3995 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3996 hsotg->frrem_samples, hsotg->frrem_accum,
3997 hsotg->frrem_samples > 0 ?
3998 hsotg->frrem_accum / hsotg->frrem_samples : 0);
3999 dev_dbg(hsotg->dev, "\n");
4000 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
4001 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4002 hsotg->hfnum_7_samples,
4003 hsotg->hfnum_7_frrem_accum,
4004 hsotg->hfnum_7_samples > 0 ?
4005 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
4006 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
4007 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4008 hsotg->hfnum_0_samples,
4009 hsotg->hfnum_0_frrem_accum,
4010 hsotg->hfnum_0_samples > 0 ?
4011 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
4012 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
4013 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4014 hsotg->hfnum_other_samples,
4015 hsotg->hfnum_other_frrem_accum,
4016 hsotg->hfnum_other_samples > 0 ?
4017 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
4018 0);
4019 dev_dbg(hsotg->dev, "\n");
4020 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
4021 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4022 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
4023 hsotg->hfnum_7_samples_a > 0 ?
4024 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
4025 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
4026 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4027 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
4028 hsotg->hfnum_0_samples_a > 0 ?
4029 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
4030 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
4031 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4032 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
4033 hsotg->hfnum_other_samples_a > 0 ?
4034 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
4035 : 0);
4036 dev_dbg(hsotg->dev, "\n");
4037 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
4038 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4039 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
4040 hsotg->hfnum_7_samples_b > 0 ?
4041 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
4042 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
4043 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4044 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
4045 (hsotg->hfnum_0_samples_b > 0) ?
4046 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
4047 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
4048 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4049 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
4050 (hsotg->hfnum_other_samples_b > 0) ?
4051 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
4052 : 0);
4053#endif
4054}
4055
4056struct wrapper_priv_data {
4057 struct dwc2_hsotg *hsotg;
4058};
4059
4060/* Gets the dwc2_hsotg from a usb_hcd */
4061static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4062{
4063 struct wrapper_priv_data *p;
4064
John Youn9da51972017-01-17 20:30:27 -08004065 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004066 return p->hsotg;
4067}
4068
Douglas Anderson9f9f09b2016-01-28 18:20:12 -08004069/**
4070 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4071 *
4072 * This will get the dwc2_tt structure (and ttport) associated with the given
4073 * context (which is really just a struct urb pointer).
4074 *
4075 * The first time this is called for a given TT we allocate memory for our
4076 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4077 * then the refcount for the structure will go to 0 and we'll free it.
4078 *
4079 * @hsotg: The HCD state structure for the DWC OTG controller.
4080 * @qh: The QH structure.
4081 * @context: The priv pointer from a struct dwc2_hcd_urb.
4082 * @mem_flags: Flags for allocating memory.
4083 * @ttport: We'll return this device's port number here. That's used to
4084 * reference into the bitmap if we're on a multi_tt hub.
4085 *
4086 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4087 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4088 */
4089
4090struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4091 gfp_t mem_flags, int *ttport)
4092{
4093 struct urb *urb = context;
4094 struct dwc2_tt *dwc_tt = NULL;
4095
4096 if (urb->dev->tt) {
4097 *ttport = urb->dev->ttport;
4098
4099 dwc_tt = urb->dev->tt->hcpriv;
John Youn9da51972017-01-17 20:30:27 -08004100 if (!dwc_tt) {
Douglas Anderson9f9f09b2016-01-28 18:20:12 -08004101 size_t bitmap_size;
4102
4103 /*
4104 * For single_tt we need one schedule. For multi_tt
4105 * we need one per port.
4106 */
4107 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4108 sizeof(dwc_tt->periodic_bitmaps[0]);
4109 if (urb->dev->tt->multi)
4110 bitmap_size *= urb->dev->tt->hub->maxchild;
4111
4112 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4113 mem_flags);
John Youn9da51972017-01-17 20:30:27 -08004114 if (!dwc_tt)
Douglas Anderson9f9f09b2016-01-28 18:20:12 -08004115 return NULL;
4116
4117 dwc_tt->usb_tt = urb->dev->tt;
4118 dwc_tt->usb_tt->hcpriv = dwc_tt;
4119 }
4120
4121 dwc_tt->refcount++;
4122 }
4123
4124 return dwc_tt;
4125}
4126
4127/**
4128 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4129 *
4130 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4131 * of the structure are done.
4132 *
4133 * It's OK to call this with NULL.
4134 *
4135 * @hsotg: The HCD state structure for the DWC OTG controller.
4136 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4137 */
4138void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4139{
4140 /* Model kfree and make put of NULL a no-op */
John Youn9da51972017-01-17 20:30:27 -08004141 if (!dwc_tt)
Douglas Anderson9f9f09b2016-01-28 18:20:12 -08004142 return;
4143
4144 WARN_ON(dwc_tt->refcount < 1);
4145
4146 dwc_tt->refcount--;
4147 if (!dwc_tt->refcount) {
4148 dwc_tt->usb_tt->hcpriv = NULL;
4149 kfree(dwc_tt);
4150 }
4151}
4152
Paul Zimmerman7359d482013-03-11 17:47:59 -07004153int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4154{
4155 struct urb *urb = context;
4156
4157 return urb->dev->speed;
4158}
4159
4160static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4161 struct urb *urb)
4162{
4163 struct usb_bus *bus = hcd_to_bus(hcd);
4164
4165 if (urb->interval)
4166 bus->bandwidth_allocated += bw / urb->interval;
4167 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4168 bus->bandwidth_isoc_reqs++;
4169 else
4170 bus->bandwidth_int_reqs++;
4171}
4172
4173static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4174 struct urb *urb)
4175{
4176 struct usb_bus *bus = hcd_to_bus(hcd);
4177
4178 if (urb->interval)
4179 bus->bandwidth_allocated -= bw / urb->interval;
4180 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4181 bus->bandwidth_isoc_reqs--;
4182 else
4183 bus->bandwidth_int_reqs--;
4184}
4185
4186/*
4187 * Sets the final status of an URB and returns it to the upper layer. Any
4188 * required cleanup of the URB is performed.
4189 *
4190 * Must be called with interrupt disabled and spinlock held
4191 */
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004192void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4193 int status)
Paul Zimmerman7359d482013-03-11 17:47:59 -07004194{
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004195 struct urb *urb;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004196 int i;
4197
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004198 if (!qtd) {
4199 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4200 return;
4201 }
4202
4203 if (!qtd->urb) {
4204 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4205 return;
4206 }
4207
4208 urb = qtd->urb->priv;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004209 if (!urb) {
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004210 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004211 return;
4212 }
4213
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004214 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004215
Matthijs Kooijmanb49977a2013-04-10 09:55:50 +02004216 if (dbg_urb(urb))
4217 dev_vdbg(hsotg->dev,
4218 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4219 __func__, urb, usb_pipedevice(urb->pipe),
4220 usb_pipeendpoint(urb->pipe),
4221 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4222 urb->actual_length);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004223
Paul Zimmerman7359d482013-03-11 17:47:59 -07004224 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004225 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004226 for (i = 0; i < urb->number_of_packets; ++i) {
4227 urb->iso_frame_desc[i].actual_length =
4228 dwc2_hcd_urb_get_iso_desc_actual_length(
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004229 qtd->urb, i);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004230 urb->iso_frame_desc[i].status =
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004231 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004232 }
4233 }
4234
Gregory Herrerofe9b1772015-09-22 15:16:51 +02004235 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4236 for (i = 0; i < urb->number_of_packets; i++)
4237 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4238 i, urb->iso_frame_desc[i].status);
4239 }
4240
Paul Zimmerman7359d482013-03-11 17:47:59 -07004241 urb->status = status;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004242 if (!status) {
4243 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4244 urb->actual_length < urb->transfer_buffer_length)
4245 urb->status = -EREMOTEIO;
4246 }
4247
4248 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4249 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4250 struct usb_host_endpoint *ep = urb->ep;
4251
4252 if (ep)
4253 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4254 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4255 urb);
4256 }
4257
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004258 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
Paul Zimmerman0d012b92013-07-13 14:53:48 -07004259 urb->hcpriv = NULL;
4260 kfree(qtd->urb);
4261 qtd->urb = NULL;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004262
Paul Zimmerman7359d482013-03-11 17:47:59 -07004263 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004264}
4265
4266/*
4267 * Work queue function for starting the HCD when A-Cable is connected
4268 */
4269static void dwc2_hcd_start_func(struct work_struct *work)
4270{
4271 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4272 start_work.work);
4273
4274 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4275 dwc2_host_start(hsotg);
4276}
4277
4278/*
4279 * Reset work queue function
4280 */
4281static void dwc2_hcd_reset_func(struct work_struct *work)
4282{
4283 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4284 reset_work.work);
Douglas Anderson4a065c72015-11-20 09:06:27 -08004285 unsigned long flags;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004286 u32 hprt0;
4287
4288 dev_dbg(hsotg->dev, "USB RESET function called\n");
Douglas Anderson4a065c72015-11-20 09:06:27 -08004289
4290 spin_lock_irqsave(&hsotg->lock, flags);
4291
Paul Zimmerman7359d482013-03-11 17:47:59 -07004292 hprt0 = dwc2_read_hprt0(hsotg);
4293 hprt0 &= ~HPRT0_RST;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03004294 dwc2_writel(hprt0, hsotg->regs + HPRT0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004295 hsotg->flags.b.port_reset_change = 1;
Douglas Anderson4a065c72015-11-20 09:06:27 -08004296
4297 spin_unlock_irqrestore(&hsotg->lock, flags);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004298}
4299
4300/*
4301 * =========================================================================
4302 * Linux HC Driver Functions
4303 * =========================================================================
4304 */
4305
4306/*
4307 * Initializes the DWC_otg controller and its root hub and prepares it for host
4308 * mode operation. Activates the root port. Returns 0 on success and a negative
4309 * error code on failure.
4310 */
4311static int _dwc2_hcd_start(struct usb_hcd *hcd)
4312{
4313 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4314 struct usb_bus *bus = hcd_to_bus(hcd);
4315 unsigned long flags;
4316
4317 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4318
4319 spin_lock_irqsave(&hsotg->lock, flags);
Gregory Herrero31927b62015-09-22 15:16:41 +02004320 hsotg->lx_state = DWC2_L0;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004321 hcd->state = HC_STATE_RUNNING;
Gregory Herrero31927b62015-09-22 15:16:41 +02004322 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004323
4324 if (dwc2_is_device_mode(hsotg)) {
4325 spin_unlock_irqrestore(&hsotg->lock, flags);
4326 return 0; /* why 0 ?? */
4327 }
4328
4329 dwc2_hcd_reinit(hsotg);
4330
4331 /* Initialize and connect root hub if one is not already attached */
4332 if (bus->root_hub) {
4333 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4334 /* Inform the HUB driver to resume */
4335 usb_hcd_resume_root_hub(hcd);
4336 }
4337
4338 spin_unlock_irqrestore(&hsotg->lock, flags);
4339 return 0;
4340}
4341
4342/*
4343 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4344 * stopped.
4345 */
4346static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4347{
4348 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4349 unsigned long flags;
4350
Gregory Herrero5bbf6ce2015-09-22 15:16:48 +02004351 /* Turn off all host-specific interrupts */
4352 dwc2_disable_host_interrupts(hsotg);
4353
Gregory Herrero091473a2015-09-22 15:16:46 +02004354 /* Wait for interrupt processing to finish */
4355 synchronize_irq(hcd->irq);
4356
Paul Zimmerman7359d482013-03-11 17:47:59 -07004357 spin_lock_irqsave(&hsotg->lock, flags);
Gregory Herrero091473a2015-09-22 15:16:46 +02004358 /* Ensure hcd is disconnected */
Douglas Anderson6a659532015-11-19 13:23:14 -08004359 dwc2_hcd_disconnect(hsotg, true);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004360 dwc2_hcd_stop(hsotg);
Gregory Herrero31927b62015-09-22 15:16:41 +02004361 hsotg->lx_state = DWC2_L3;
4362 hcd->state = HC_STATE_HALT;
4363 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004364 spin_unlock_irqrestore(&hsotg->lock, flags);
4365
4366 usleep_range(1000, 3000);
4367}
4368
Gregory Herrero99a65792015-04-29 22:09:13 +02004369static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4370{
4371 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004372 unsigned long flags;
4373 int ret = 0;
4374 u32 hprt0;
Gregory Herrero99a65792015-04-29 22:09:13 +02004375
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004376 spin_lock_irqsave(&hsotg->lock, flags);
4377
4378 if (hsotg->lx_state != DWC2_L0)
4379 goto unlock;
4380
4381 if (!HCD_HW_ACCESSIBLE(hcd))
4382 goto unlock;
4383
John Stultz866932e2017-01-09 13:10:24 -08004384 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4385 goto unlock;
4386
John Younbea8e862016-11-03 17:55:53 -07004387 if (!hsotg->params.hibernation)
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004388 goto skip_power_saving;
4389
4390 /*
4391 * Drive USB suspend and disable port Power
4392 * if usb bus is not suspended.
4393 */
4394 if (!hsotg->bus_suspended) {
4395 hprt0 = dwc2_read_hprt0(hsotg);
4396 hprt0 |= HPRT0_SUSP;
4397 hprt0 &= ~HPRT0_PWR;
4398 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4399 }
4400
4401 /* Enter hibernation */
4402 ret = dwc2_enter_hibernation(hsotg);
4403 if (ret) {
4404 if (ret != -ENOTSUPP)
4405 dev_err(hsotg->dev,
4406 "enter hibernation failed\n");
4407 goto skip_power_saving;
4408 }
4409
4410 /* Ask phy to be suspended */
4411 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4412 spin_unlock_irqrestore(&hsotg->lock, flags);
4413 usb_phy_set_suspend(hsotg->uphy, true);
4414 spin_lock_irqsave(&hsotg->lock, flags);
4415 }
4416
4417 /* After entering hibernation, hardware is no more accessible */
4418 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4419
4420skip_power_saving:
Gregory Herrero99a65792015-04-29 22:09:13 +02004421 hsotg->lx_state = DWC2_L2;
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004422unlock:
4423 spin_unlock_irqrestore(&hsotg->lock, flags);
4424
4425 return ret;
Gregory Herrero99a65792015-04-29 22:09:13 +02004426}
4427
4428static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4429{
4430 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004431 unsigned long flags;
4432 int ret = 0;
4433
4434 spin_lock_irqsave(&hsotg->lock, flags);
4435
4436 if (hsotg->lx_state != DWC2_L2)
4437 goto unlock;
4438
John Younbea8e862016-11-03 17:55:53 -07004439 if (!hsotg->params.hibernation) {
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004440 hsotg->lx_state = DWC2_L0;
4441 goto unlock;
4442 }
4443
4444 /*
4445 * Set HW accessible bit before powering on the controller
4446 * since an interrupt may rise.
4447 */
4448 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4449
4450 /*
4451 * Enable power if not already done.
4452 * This must not be spinlocked since duration
4453 * of this call is unknown.
4454 */
4455 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4456 spin_unlock_irqrestore(&hsotg->lock, flags);
4457 usb_phy_set_suspend(hsotg->uphy, false);
4458 spin_lock_irqsave(&hsotg->lock, flags);
4459 }
4460
4461 /* Exit hibernation */
4462 ret = dwc2_exit_hibernation(hsotg, true);
4463 if (ret && (ret != -ENOTSUPP))
4464 dev_err(hsotg->dev, "exit hibernation failed\n");
Gregory Herrero99a65792015-04-29 22:09:13 +02004465
4466 hsotg->lx_state = DWC2_L0;
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004467
4468 spin_unlock_irqrestore(&hsotg->lock, flags);
4469
4470 if (hsotg->bus_suspended) {
4471 spin_lock_irqsave(&hsotg->lock, flags);
4472 hsotg->flags.b.port_suspend_change = 1;
4473 spin_unlock_irqrestore(&hsotg->lock, flags);
4474 dwc2_port_resume(hsotg);
4475 } else {
Gregory Herrero5634e012015-09-22 15:16:50 +02004476 /* Wait for controller to correctly update D+/D- level */
4477 usleep_range(3000, 5000);
4478
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004479 /*
4480 * Clear Port Enable and Port Status changes.
4481 * Enable Port Power.
4482 */
4483 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4484 HPRT0_ENACHG, hsotg->regs + HPRT0);
4485 /* Wait for controller to detect Port Connect */
Gregory Herrero5634e012015-09-22 15:16:50 +02004486 usleep_range(5000, 7000);
Gregory Herreroa2a23d3f2015-09-22 15:16:40 +02004487 }
4488
4489 return ret;
4490unlock:
4491 spin_unlock_irqrestore(&hsotg->lock, flags);
4492
4493 return ret;
Gregory Herrero99a65792015-04-29 22:09:13 +02004494}
4495
Paul Zimmerman7359d482013-03-11 17:47:59 -07004496/* Returns the current frame number */
4497static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4498{
4499 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4500
4501 return dwc2_hcd_get_frame_number(hsotg);
4502}
4503
4504static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4505 char *fn_name)
4506{
4507#ifdef VERBOSE_DEBUG
4508 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
Nicholas Mc Guireefe357f2017-01-12 17:33:26 +01004509 char *pipetype = NULL;
4510 char *speed = NULL;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004511
4512 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4513 dev_vdbg(hsotg->dev, " Device address: %d\n",
4514 usb_pipedevice(urb->pipe));
4515 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4516 usb_pipeendpoint(urb->pipe),
4517 usb_pipein(urb->pipe) ? "IN" : "OUT");
4518
4519 switch (usb_pipetype(urb->pipe)) {
4520 case PIPE_CONTROL:
4521 pipetype = "CONTROL";
4522 break;
4523 case PIPE_BULK:
4524 pipetype = "BULK";
4525 break;
4526 case PIPE_INTERRUPT:
4527 pipetype = "INTERRUPT";
4528 break;
4529 case PIPE_ISOCHRONOUS:
4530 pipetype = "ISOCHRONOUS";
4531 break;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004532 }
4533
4534 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4535 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4536 "IN" : "OUT");
4537
4538 switch (urb->dev->speed) {
4539 case USB_SPEED_HIGH:
4540 speed = "HIGH";
4541 break;
4542 case USB_SPEED_FULL:
4543 speed = "FULL";
4544 break;
4545 case USB_SPEED_LOW:
4546 speed = "LOW";
4547 break;
4548 default:
4549 speed = "UNKNOWN";
4550 break;
4551 }
4552
4553 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4554 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4555 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4556 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4557 urb->transfer_buffer_length);
Paul Zimmerman157dfaa2013-03-14 13:12:00 -07004558 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4559 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4560 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4561 urb->setup_packet, (unsigned long)urb->setup_dma);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004562 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4563
4564 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4565 int i;
4566
4567 for (i = 0; i < urb->number_of_packets; i++) {
4568 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4569 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4570 urb->iso_frame_desc[i].offset,
4571 urb->iso_frame_desc[i].length);
4572 }
4573 }
4574#endif
4575}
4576
4577/*
4578 * Starts processing a USB transfer request specified by a USB Request Block
4579 * (URB). mem_flags indicates the type of memory allocation to use while
4580 * processing this URB.
4581 */
4582static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4583 gfp_t mem_flags)
4584{
4585 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4586 struct usb_host_endpoint *ep = urb->ep;
4587 struct dwc2_hcd_urb *dwc2_urb;
4588 int i;
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004589 int retval;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004590 int alloc_bandwidth = 0;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004591 u8 ep_type = 0;
4592 u32 tflags = 0;
4593 void *buf;
4594 unsigned long flags;
Mian Yousaf Kaukabb58e6ce2015-06-29 11:05:28 +02004595 struct dwc2_qh *qh;
4596 bool qh_allocated = false;
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02004597 struct dwc2_qtd *qtd;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004598
Matthijs Kooijmanb49977a2013-04-10 09:55:50 +02004599 if (dbg_urb(urb)) {
4600 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4601 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4602 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07004603
John Youn9da51972017-01-17 20:30:27 -08004604 if (!ep)
Paul Zimmerman7359d482013-03-11 17:47:59 -07004605 return -EINVAL;
4606
4607 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4608 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4609 spin_lock_irqsave(&hsotg->lock, flags);
4610 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4611 alloc_bandwidth = 1;
4612 spin_unlock_irqrestore(&hsotg->lock, flags);
4613 }
4614
4615 switch (usb_pipetype(urb->pipe)) {
4616 case PIPE_CONTROL:
4617 ep_type = USB_ENDPOINT_XFER_CONTROL;
4618 break;
4619 case PIPE_ISOCHRONOUS:
4620 ep_type = USB_ENDPOINT_XFER_ISOC;
4621 break;
4622 case PIPE_BULK:
4623 ep_type = USB_ENDPOINT_XFER_BULK;
4624 break;
4625 case PIPE_INTERRUPT:
4626 ep_type = USB_ENDPOINT_XFER_INT;
4627 break;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004628 }
4629
4630 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4631 mem_flags);
4632 if (!dwc2_urb)
4633 return -ENOMEM;
4634
4635 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4636 usb_pipeendpoint(urb->pipe), ep_type,
4637 usb_pipein(urb->pipe),
4638 usb_maxpacket(urb->dev, urb->pipe,
4639 !(usb_pipein(urb->pipe))));
4640
4641 buf = urb->transfer_buffer;
Paul Zimmerman25a49442013-07-13 14:53:53 -07004642
Paul Zimmerman7359d482013-03-11 17:47:59 -07004643 if (hcd->self.uses_dma) {
Paul Zimmerman25a49442013-07-13 14:53:53 -07004644 if (!buf && (urb->transfer_dma & 3)) {
4645 dev_err(hsotg->dev,
4646 "%s: unaligned transfer with no transfer_buffer",
4647 __func__);
4648 retval = -EINVAL;
Gregory Herrero33ad2612015-04-29 22:09:15 +02004649 goto fail0;
Paul Zimmerman25a49442013-07-13 14:53:53 -07004650 }
Paul Zimmerman7359d482013-03-11 17:47:59 -07004651 }
4652
4653 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4654 tflags |= URB_GIVEBACK_ASAP;
4655 if (urb->transfer_flags & URB_ZERO_PACKET)
4656 tflags |= URB_SEND_ZERO_PACKET;
4657
4658 dwc2_urb->priv = urb;
4659 dwc2_urb->buf = buf;
4660 dwc2_urb->dma = urb->transfer_dma;
4661 dwc2_urb->length = urb->transfer_buffer_length;
4662 dwc2_urb->setup_packet = urb->setup_packet;
4663 dwc2_urb->setup_dma = urb->setup_dma;
4664 dwc2_urb->flags = tflags;
4665 dwc2_urb->interval = urb->interval;
4666 dwc2_urb->status = -EINPROGRESS;
4667
4668 for (i = 0; i < urb->number_of_packets; ++i)
4669 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4670 urb->iso_frame_desc[i].offset,
4671 urb->iso_frame_desc[i].length);
4672
4673 urb->hcpriv = dwc2_urb;
John Youn9da51972017-01-17 20:30:27 -08004674 qh = (struct dwc2_qh *)ep->hcpriv;
Mian Yousaf Kaukabb58e6ce2015-06-29 11:05:28 +02004675 /* Create QH for the endpoint if it doesn't exist */
4676 if (!qh) {
4677 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4678 if (!qh) {
4679 retval = -ENOMEM;
4680 goto fail0;
4681 }
4682 ep->hcpriv = qh;
4683 qh_allocated = true;
4684 }
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004685
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02004686 qtd = kzalloc(sizeof(*qtd), mem_flags);
4687 if (!qtd) {
4688 retval = -ENOMEM;
4689 goto fail1;
4690 }
4691
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004692 spin_lock_irqsave(&hsotg->lock, flags);
4693 retval = usb_hcd_link_urb_to_ep(hcd, urb);
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004694 if (retval)
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004695 goto fail2;
4696
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02004697 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4698 if (retval)
4699 goto fail3;
4700
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004701 if (alloc_bandwidth) {
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004702 dwc2_allocate_bus_bandwidth(hcd,
4703 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4704 urb);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004705 }
4706
Gregory Herrero33ad2612015-04-29 22:09:15 +02004707 spin_unlock_irqrestore(&hsotg->lock, flags);
4708
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004709 return 0;
4710
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02004711fail3:
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004712 dwc2_urb->priv = NULL;
4713 usb_hcd_unlink_urb_from_ep(hcd, urb);
Douglas Anderson16e80212016-01-28 18:19:55 -08004714 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4715 qh->channel->qh = NULL;
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02004716fail2:
Gregory Herrero33ad2612015-04-29 22:09:15 +02004717 spin_unlock_irqrestore(&hsotg->lock, flags);
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004718 urb->hcpriv = NULL;
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02004719 kfree(qtd);
Vardan Mikayelyanb0d659022016-04-27 20:20:51 -07004720 qtd = NULL;
Mian Yousaf Kaukabb5a468a2015-06-29 11:05:29 +02004721fail1:
Mian Yousaf Kaukabb58e6ce2015-06-29 11:05:28 +02004722 if (qh_allocated) {
4723 struct dwc2_qtd *qtd2, *qtd2_tmp;
4724
4725 ep->hcpriv = NULL;
4726 dwc2_hcd_qh_unlink(hsotg, qh);
4727 /* Free each QTD in the QH's QTD list */
4728 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
John Youn9da51972017-01-17 20:30:27 -08004729 qtd_list_entry)
Mian Yousaf Kaukabb58e6ce2015-06-29 11:05:28 +02004730 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4731 dwc2_hcd_qh_free(hsotg, qh);
4732 }
Gregory Herrero33ad2612015-04-29 22:09:15 +02004733fail0:
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004734 kfree(dwc2_urb);
4735
Paul Zimmerman7359d482013-03-11 17:47:59 -07004736 return retval;
4737}
4738
4739/*
4740 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4741 */
4742static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4743 int status)
4744{
4745 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004746 int rc;
Paul Zimmerman7359d482013-03-11 17:47:59 -07004747 unsigned long flags;
4748
4749 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4750 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4751
4752 spin_lock_irqsave(&hsotg->lock, flags);
4753
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004754 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4755 if (rc)
4756 goto out;
4757
Paul Zimmerman7359d482013-03-11 17:47:59 -07004758 if (!urb->hcpriv) {
4759 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4760 goto out;
4761 }
4762
4763 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4764
Paul Zimmermanc9e1c902013-07-13 14:53:49 -07004765 usb_hcd_unlink_urb_from_ep(hcd, urb);
4766
Paul Zimmerman7359d482013-03-11 17:47:59 -07004767 kfree(urb->hcpriv);
4768 urb->hcpriv = NULL;
4769
4770 /* Higher layer software sets URB status */
4771 spin_unlock(&hsotg->lock);
4772 usb_hcd_giveback_urb(hcd, urb, status);
4773 spin_lock(&hsotg->lock);
4774
4775 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4776 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4777out:
4778 spin_unlock_irqrestore(&hsotg->lock, flags);
4779
4780 return rc;
4781}
4782
4783/*
4784 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4785 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4786 * must already be dequeued.
4787 */
4788static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4789 struct usb_host_endpoint *ep)
4790{
4791 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4792
4793 dev_dbg(hsotg->dev,
4794 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4795 ep->desc.bEndpointAddress, ep->hcpriv);
4796 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4797}
4798
4799/*
4800 * Resets endpoint specific parameter values, in current version used to reset
4801 * the data toggle (as a WA). This function can be called from usb_clear_halt
4802 * routine.
4803 */
4804static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4805 struct usb_host_endpoint *ep)
4806{
4807 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004808 unsigned long flags;
4809
4810 dev_dbg(hsotg->dev,
4811 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4812 ep->desc.bEndpointAddress);
4813
Paul Zimmerman7359d482013-03-11 17:47:59 -07004814 spin_lock_irqsave(&hsotg->lock, flags);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004815 dwc2_hcd_endpoint_reset(hsotg, ep);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004816 spin_unlock_irqrestore(&hsotg->lock, flags);
4817}
4818
4819/*
4820 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4821 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4822 * interrupt.
4823 *
4824 * This function is called by the USB core when an interrupt occurs
4825 */
4826static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4827{
4828 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004829
Matthijs Kooijmanca18f4a2013-04-25 23:39:15 +02004830 return dwc2_handle_hcd_intr(hsotg);
Paul Zimmerman7359d482013-03-11 17:47:59 -07004831}
4832
4833/*
4834 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4835 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4836 * is the status change indicator for the single root port. Returns 1 if either
4837 * change indicator is 1, otherwise returns 0.
4838 */
4839static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4840{
4841 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4842
4843 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4844 return buf[0] != 0;
4845}
4846
4847/* Handles hub class-specific requests */
4848static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4849 u16 windex, char *buf, u16 wlength)
4850{
4851 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4852 wvalue, windex, buf, wlength);
4853 return retval;
4854}
4855
4856/* Handles hub TT buffer clear completions */
4857static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4858 struct usb_host_endpoint *ep)
4859{
4860 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4861 struct dwc2_qh *qh;
4862 unsigned long flags;
4863
4864 qh = ep->hcpriv;
4865 if (!qh)
4866 return;
4867
4868 spin_lock_irqsave(&hsotg->lock, flags);
4869 qh->tt_buffer_dirty = 0;
4870
4871 if (hsotg->flags.b.port_connect_status)
4872 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4873
4874 spin_unlock_irqrestore(&hsotg->lock, flags);
4875}
4876
Chen Yuca8b0332017-01-23 15:00:18 -08004877/*
4878 * HPRT0_SPD_HIGH_SPEED: high speed
4879 * HPRT0_SPD_FULL_SPEED: full speed
4880 */
4881static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4882{
4883 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4884
4885 if (hsotg->params.speed == speed)
4886 return;
4887
4888 hsotg->params.speed = speed;
4889 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4890}
4891
4892static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4893{
4894 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4895
4896 if (!hsotg->params.change_speed_quirk)
4897 return;
4898
4899 /*
4900 * On removal, set speed to default high-speed.
4901 */
4902 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4903 udev->parent->speed < USB_SPEED_HIGH) {
4904 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4905 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4906 }
4907}
4908
4909static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4910{
4911 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4912
4913 if (!hsotg->params.change_speed_quirk)
4914 return 0;
4915
4916 if (udev->speed == USB_SPEED_HIGH) {
4917 dev_info(hsotg->dev, "Set speed to high-speed\n");
4918 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4919 } else if ((udev->speed == USB_SPEED_FULL ||
4920 udev->speed == USB_SPEED_LOW)) {
4921 /*
4922 * Change speed setting to full-speed if there's
4923 * a full-speed or low-speed device plugged in.
4924 */
4925 dev_info(hsotg->dev, "Set speed to full-speed\n");
4926 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4927 }
4928
4929 return 0;
4930}
4931
Paul Zimmerman7359d482013-03-11 17:47:59 -07004932static struct hc_driver dwc2_hc_driver = {
4933 .description = "dwc2_hsotg",
4934 .product_desc = "DWC OTG Controller",
4935 .hcd_priv_size = sizeof(struct wrapper_priv_data),
4936
4937 .irq = _dwc2_hcd_irq,
Douglas Anderson8add17c2016-01-28 18:20:00 -08004938 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
Paul Zimmerman7359d482013-03-11 17:47:59 -07004939
4940 .start = _dwc2_hcd_start,
4941 .stop = _dwc2_hcd_stop,
4942 .urb_enqueue = _dwc2_hcd_urb_enqueue,
4943 .urb_dequeue = _dwc2_hcd_urb_dequeue,
4944 .endpoint_disable = _dwc2_hcd_endpoint_disable,
4945 .endpoint_reset = _dwc2_hcd_endpoint_reset,
4946 .get_frame_number = _dwc2_hcd_get_frame_number,
4947
4948 .hub_status_data = _dwc2_hcd_hub_status_data,
4949 .hub_control = _dwc2_hcd_hub_control,
4950 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
Gregory Herrero99a65792015-04-29 22:09:13 +02004951
4952 .bus_suspend = _dwc2_hcd_suspend,
4953 .bus_resume = _dwc2_hcd_resume,
Douglas Anderson3bc04e22016-01-28 18:19:53 -08004954
4955 .map_urb_for_dma = dwc2_map_urb_for_dma,
4956 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
Paul Zimmerman7359d482013-03-11 17:47:59 -07004957};
4958
4959/*
4960 * Frees secondary storage associated with the dwc2_hsotg structure contained
4961 * in the struct usb_hcd field
4962 */
4963static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4964{
4965 u32 ahbcfg;
4966 u32 dctl;
4967 int i;
4968
4969 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4970
4971 /* Free memory for QH/QTD lists */
4972 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4973 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4974 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4975 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4976 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4977 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4978
4979 /* Free memory for the host channels */
4980 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4981 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4982
John Youn9da51972017-01-17 20:30:27 -08004983 if (chan) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07004984 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4985 i, chan);
4986 hsotg->hc_ptr_array[i] = NULL;
4987 kfree(chan);
4988 }
4989 }
4990
John Youn95832c02017-01-23 14:57:26 -08004991 if (hsotg->params.host_dma) {
Paul Zimmerman7359d482013-03-11 17:47:59 -07004992 if (hsotg->status_buf) {
4993 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4994 hsotg->status_buf,
4995 hsotg->status_buf_dma);
4996 hsotg->status_buf = NULL;
4997 }
4998 } else {
4999 kfree(hsotg->status_buf);
5000 hsotg->status_buf = NULL;
5001 }
5002
Antti Seppälä95c8bc32015-08-20 21:41:07 +03005003 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005004
5005 /* Disable all interrupts */
5006 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03005007 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5008 dwc2_writel(0, hsotg->regs + GINTMSK);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005009
Matthijs Kooijman9badec22013-08-30 18:45:21 +02005010 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
Antti Seppälä95c8bc32015-08-20 21:41:07 +03005011 dctl = dwc2_readl(hsotg->regs + DCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005012 dctl |= DCTL_SFTDISCON;
Antti Seppälä95c8bc32015-08-20 21:41:07 +03005013 dwc2_writel(dctl, hsotg->regs + DCTL);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005014 }
5015
5016 if (hsotg->wq_otg) {
5017 if (!cancel_work_sync(&hsotg->wf_otg))
5018 flush_workqueue(hsotg->wq_otg);
5019 destroy_workqueue(hsotg->wq_otg);
5020 }
5021
Paul Zimmerman7359d482013-03-11 17:47:59 -07005022 del_timer(&hsotg->wkp_timer);
5023}
5024
5025static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5026{
5027 /* Turn off all host-specific interrupts */
5028 dwc2_disable_host_interrupts(hsotg);
5029
5030 dwc2_hcd_free(hsotg);
5031}
5032
Matthijs Kooijman8284f932013-04-11 18:43:47 +02005033/*
Paul Zimmerman7359d482013-03-11 17:47:59 -07005034 * Initializes the HCD. This function allocates memory for and initializes the
5035 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5036 * USB bus with the core and calls the hc_driver->start() function. It returns
5037 * a negative error on failure.
5038 */
Heiner Kallweit4fe160d2017-01-25 23:13:37 +01005039int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
Paul Zimmerman7359d482013-03-11 17:47:59 -07005040{
Heiner Kallweit348becd2017-01-25 23:10:51 +01005041 struct platform_device *pdev = to_platform_device(hsotg->dev);
5042 struct resource *res;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005043 struct usb_hcd *hcd;
5044 struct dwc2_host_chan *channel;
Matthijs Kooijman9badec22013-08-30 18:45:21 +02005045 u32 hcfg;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005046 int i, num_channels;
Matthijs Kooijman9badec22013-08-30 18:45:21 +02005047 int retval;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005048
Dinh Nguyenf5500ec2014-11-11 11:13:39 -06005049 if (usb_disabled())
5050 return -ENODEV;
5051
Paul Zimmermane62662c2013-03-25 17:03:35 -07005052 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
Paul Zimmerman7359d482013-03-11 17:47:59 -07005053
Matthijs Kooijman9badec22013-08-30 18:45:21 +02005054 retval = -ENOMEM;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005055
Antti Seppälä95c8bc32015-08-20 21:41:07 +03005056 hcfg = dwc2_readl(hsotg->regs + HCFG);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005057 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005058
5059#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5060 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5061 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5062 if (!hsotg->frame_num_array)
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005063 goto error1;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005064 hsotg->last_frame_num_array = kzalloc(
5065 sizeof(*hsotg->last_frame_num_array) *
5066 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5067 if (!hsotg->last_frame_num_array)
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005068 goto error1;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005069#endif
Douglas Anderson483bb252016-01-28 18:20:07 -08005070 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005071
Matthijs Kooijmana0112f42013-07-19 11:34:22 +02005072 /* Check if the bus driver or platform code has setup a dma_mask */
John Youn95832c02017-01-23 14:57:26 -08005073 if (hsotg->params.host_dma &&
John Youn9da51972017-01-17 20:30:27 -08005074 !hsotg->dev->dma_mask) {
Matthijs Kooijmana0112f42013-07-19 11:34:22 +02005075 dev_warn(hsotg->dev,
5076 "dma_mask not set, disabling DMA\n");
Nicholas Mc Guirefdb09b32017-01-12 16:55:02 +01005077 hsotg->params.host_dma = false;
John Youn95832c02017-01-23 14:57:26 -08005078 hsotg->params.dma_desc_enable = false;
Matthijs Kooijmana0112f42013-07-19 11:34:22 +02005079 }
5080
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005081 /* Set device flags indicating whether the HCD supports DMA */
John Youn95832c02017-01-23 14:57:26 -08005082 if (hsotg->params.host_dma) {
Paul Zimmerman30885312013-05-24 16:27:56 -07005083 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5084 dev_warn(hsotg->dev, "can't set DMA mask\n");
Paul Zimmerman25a49442013-07-13 14:53:53 -07005085 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5086 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005087 }
5088
Chen Yuca8b0332017-01-23 15:00:18 -08005089 if (hsotg->params.change_speed_quirk) {
5090 dwc2_hc_driver.free_dev = dwc2_free_dev;
5091 dwc2_hc_driver.reset_device = dwc2_reset_device;
5092 }
5093
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005094 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5095 if (!hcd)
5096 goto error1;
5097
John Youn95832c02017-01-23 14:57:26 -08005098 if (!hsotg->params.host_dma)
Matthijs Kooijman7de76ee2013-07-19 11:34:23 +02005099 hcd->self.uses_dma = 0;
5100
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005101 hcd->has_tt = 1;
5102
Heiner Kallweit348becd2017-01-25 23:10:51 +01005103 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5104 hcd->rsrc_start = res->start;
5105 hcd->rsrc_len = resource_size(res);
5106
John Youn9da51972017-01-17 20:30:27 -08005107 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005108 hsotg->priv = hcd;
5109
Paul Zimmerman7359d482013-03-11 17:47:59 -07005110 /*
5111 * Disable the global interrupt until all the interrupt handlers are
5112 * installed
5113 */
5114 dwc2_disable_global_interrupts(hsotg);
5115
Matthijs Kooijman6706c722013-04-11 17:52:41 +02005116 /* Initialize the DWC_otg core, and select the Phy type */
Douglas Anderson0fe239b2015-12-17 11:14:40 -08005117 retval = dwc2_core_init(hsotg, true);
Matthijs Kooijman6706c722013-04-11 17:52:41 +02005118 if (retval)
5119 goto error2;
5120
Paul Zimmerman7359d482013-03-11 17:47:59 -07005121 /* Create new workqueue and init work */
Wei Yongjun53510352013-04-12 22:41:48 +08005122 retval = -ENOMEM;
Bhaktipriya Shridharec7b1262016-07-28 13:57:29 +05305123 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005124 if (!hsotg->wq_otg) {
5125 dev_err(hsotg->dev, "Failed to create workqueue\n");
5126 goto error2;
5127 }
5128 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5129
Paul Zimmerman7359d482013-03-11 17:47:59 -07005130 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
5131 (unsigned long)hsotg);
5132
5133 /* Initialize the non-periodic schedule */
5134 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5135 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5136
5137 /* Initialize the periodic schedule */
5138 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5139 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5140 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5141 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5142
Douglas Andersonc9c8ac02016-01-28 18:19:57 -08005143 INIT_LIST_HEAD(&hsotg->split_order);
5144
Paul Zimmerman7359d482013-03-11 17:47:59 -07005145 /*
5146 * Create a host channel descriptor for each host channel implemented
5147 * in the controller. Initialize the channel descriptor array.
5148 */
5149 INIT_LIST_HEAD(&hsotg->free_hc_list);
John Younbea8e862016-11-03 17:55:53 -07005150 num_channels = hsotg->params.host_channels;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005151 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5152
5153 for (i = 0; i < num_channels; i++) {
5154 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
John Youn9da51972017-01-17 20:30:27 -08005155 if (!channel)
Paul Zimmerman7359d482013-03-11 17:47:59 -07005156 goto error3;
5157 channel->hc_num = i;
Douglas Andersonc9c8ac02016-01-28 18:19:57 -08005158 INIT_LIST_HEAD(&channel->split_order_list_entry);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005159 hsotg->hc_ptr_array[i] = channel;
5160 }
5161
5162 /* Initialize hsotg start work */
5163 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5164
5165 /* Initialize port reset work */
5166 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5167
5168 /*
5169 * Allocate space for storing data on status transactions. Normally no
5170 * data is sent, but this space acts as a bit bucket. This must be
5171 * done after usb_add_hcd since that function allocates the DMA buffer
5172 * pool.
5173 */
John Youn95832c02017-01-23 14:57:26 -08005174 if (hsotg->params.host_dma)
Paul Zimmerman7359d482013-03-11 17:47:59 -07005175 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5176 DWC2_HCD_STATUS_BUF_SIZE,
5177 &hsotg->status_buf_dma, GFP_KERNEL);
5178 else
5179 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5180 GFP_KERNEL);
5181
5182 if (!hsotg->status_buf)
5183 goto error3;
5184
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005185 /*
5186 * Create kmem caches to handle descriptor buffers in descriptor
5187 * DMA mode.
5188 * Alignment must be set to 512 bytes.
5189 */
John Younbea8e862016-11-03 17:55:53 -07005190 if (hsotg->params.dma_desc_enable ||
5191 hsotg->params.dma_desc_fs_enable) {
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005192 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
Vahram Aharonyanec703252016-11-09 19:27:43 -08005193 sizeof(struct dwc2_dma_desc) *
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005194 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5195 NULL);
5196 if (!hsotg->desc_gen_cache) {
5197 dev_err(hsotg->dev,
5198 "unable to create dwc2 generic desc cache\n");
5199
5200 /*
5201 * Disable descriptor dma mode since it will not be
5202 * usable.
5203 */
John Youn95832c02017-01-23 14:57:26 -08005204 hsotg->params.dma_desc_enable = false;
5205 hsotg->params.dma_desc_fs_enable = false;
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005206 }
5207
5208 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
Vahram Aharonyanec703252016-11-09 19:27:43 -08005209 sizeof(struct dwc2_dma_desc) *
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005210 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5211 if (!hsotg->desc_hsisoc_cache) {
5212 dev_err(hsotg->dev,
5213 "unable to create dwc2 hs isoc desc cache\n");
5214
5215 kmem_cache_destroy(hsotg->desc_gen_cache);
5216
5217 /*
5218 * Disable descriptor dma mode since it will not be
5219 * usable.
5220 */
John Youn95832c02017-01-23 14:57:26 -08005221 hsotg->params.dma_desc_enable = false;
5222 hsotg->params.dma_desc_fs_enable = false;
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005223 }
5224 }
5225
Paul Zimmerman7359d482013-03-11 17:47:59 -07005226 hsotg->otg_port = 1;
5227 hsotg->frame_list = NULL;
5228 hsotg->frame_list_dma = 0;
5229 hsotg->periodic_qh_count = 0;
5230
5231 /* Initiate lx_state to L3 disconnected state */
5232 hsotg->lx_state = DWC2_L3;
5233
5234 hcd->self.otg_port = hsotg->otg_port;
5235
5236 /* Don't support SG list at this point */
5237 hcd->self.sg_tablesize = 0;
5238
Mian Yousaf Kaukab9df4cea2015-04-29 22:09:12 +02005239 if (!IS_ERR_OR_NULL(hsotg->uphy))
5240 otg_set_host(hsotg->uphy->otg, &hcd->self);
5241
Paul Zimmerman7359d482013-03-11 17:47:59 -07005242 /*
5243 * Finish generic HCD initialization and start the HCD. This function
5244 * allocates the DMA buffer pool, registers the USB bus, requests the
5245 * IRQ line, and calls hcd_start method.
5246 */
Heiner Kallweit4fe160d2017-01-25 23:13:37 +01005247 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005248 if (retval < 0)
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005249 goto error4;
Paul Zimmerman7359d482013-03-11 17:47:59 -07005250
Peter Chen3c9740a2013-11-05 10:46:02 +08005251 device_wakeup_enable(hcd->self.controller);
5252
Paul Zimmerman7359d482013-03-11 17:47:59 -07005253 dwc2_hcd_dump_state(hsotg);
5254
5255 dwc2_enable_global_interrupts(hsotg);
5256
5257 return 0;
5258
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005259error4:
5260 kmem_cache_destroy(hsotg->desc_gen_cache);
5261 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005262error3:
5263 dwc2_hcd_release(hsotg);
5264error2:
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005265 usb_put_hcd(hcd);
5266error1:
Paul Zimmerman7359d482013-03-11 17:47:59 -07005267
5268#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5269 kfree(hsotg->last_frame_num_array);
5270 kfree(hsotg->frame_num_array);
5271#endif
5272
Paul Zimmermane62662c2013-03-25 17:03:35 -07005273 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005274 return retval;
5275}
Paul Zimmerman7359d482013-03-11 17:47:59 -07005276
5277/*
5278 * Removes the HCD.
5279 * Frees memory and resources associated with the HCD and deregisters the bus.
5280 */
Paul Zimmermane62662c2013-03-25 17:03:35 -07005281void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
Paul Zimmerman7359d482013-03-11 17:47:59 -07005282{
5283 struct usb_hcd *hcd;
5284
Paul Zimmermane62662c2013-03-25 17:03:35 -07005285 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
Paul Zimmerman7359d482013-03-11 17:47:59 -07005286
5287 hcd = dwc2_hsotg_to_hcd(hsotg);
Paul Zimmermane62662c2013-03-25 17:03:35 -07005288 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005289
5290 if (!hcd) {
Paul Zimmermane62662c2013-03-25 17:03:35 -07005291 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
Paul Zimmerman7359d482013-03-11 17:47:59 -07005292 __func__);
5293 return;
5294 }
5295
Mian Yousaf Kaukab9df4cea2015-04-29 22:09:12 +02005296 if (!IS_ERR_OR_NULL(hsotg->uphy))
5297 otg_set_host(hsotg->uphy->otg, NULL);
5298
Paul Zimmerman7359d482013-03-11 17:47:59 -07005299 usb_remove_hcd(hcd);
5300 hsotg->priv = NULL;
Gregory Herrero3b5fcc92015-11-20 11:49:31 +01005301
5302 kmem_cache_destroy(hsotg->desc_gen_cache);
5303 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5304
Paul Zimmerman7359d482013-03-11 17:47:59 -07005305 dwc2_hcd_release(hsotg);
Paul Zimmermanba0e60d2013-03-25 17:03:36 -07005306 usb_put_hcd(hcd);
Paul Zimmerman7359d482013-03-11 17:47:59 -07005307
5308#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5309 kfree(hsotg->last_frame_num_array);
5310 kfree(hsotg->frame_num_array);
5311#endif
Paul Zimmerman7359d482013-03-11 17:47:59 -07005312}
John Youn58e52ff6a2016-02-23 19:54:57 -08005313
5314/**
5315 * dwc2_backup_host_registers() - Backup controller host registers.
5316 * When suspending usb bus, registers needs to be backuped
5317 * if controller power is disabled once suspended.
5318 *
5319 * @hsotg: Programming view of the DWC_otg controller
5320 */
5321int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5322{
5323 struct dwc2_hregs_backup *hr;
5324 int i;
5325
5326 dev_dbg(hsotg->dev, "%s\n", __func__);
5327
5328 /* Backup Host regs */
5329 hr = &hsotg->hr_backup;
5330 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5331 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
John Younbea8e862016-11-03 17:55:53 -07005332 for (i = 0; i < hsotg->params.host_channels; ++i)
John Youn58e52ff6a2016-02-23 19:54:57 -08005333 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5334
5335 hr->hprt0 = dwc2_read_hprt0(hsotg);
5336 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5337 hr->valid = true;
5338
5339 return 0;
5340}
5341
5342/**
5343 * dwc2_restore_host_registers() - Restore controller host registers.
5344 * When resuming usb bus, device registers needs to be restored
5345 * if controller power were disabled.
5346 *
5347 * @hsotg: Programming view of the DWC_otg controller
5348 */
5349int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5350{
5351 struct dwc2_hregs_backup *hr;
5352 int i;
5353
5354 dev_dbg(hsotg->dev, "%s\n", __func__);
5355
5356 /* Restore host regs */
5357 hr = &hsotg->hr_backup;
5358 if (!hr->valid) {
5359 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5360 __func__);
5361 return -EINVAL;
5362 }
5363 hr->valid = false;
5364
5365 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5366 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5367
John Younbea8e862016-11-03 17:55:53 -07005368 for (i = 0; i < hsotg->params.host_channels; ++i)
John Youn58e52ff6a2016-02-23 19:54:57 -08005369 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5370
5371 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5372 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5373 hsotg->frame_number = 0;
5374
5375 return 0;
5376}