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Greg Kroah-Hartmane3b3d0f2017-11-06 18:11:51 +01001// SPDX-License-Identifier: GPL-2.0
Maxime Coquelin48a60922015-06-10 21:19:36 +02002/*
3 * Copyright (C) Maxime Coquelin 2015
Bich HEMON3e5fcba2017-07-13 15:08:26 +00004 * Copyright (C) STMicroelectronics SA 2017
Alexandre TORGUEada86182016-09-15 18:42:33 +02005 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
Maxime Coquelin48a60922015-06-10 21:19:36 +02007 * License terms: GNU General Public License (GPL), version 2
8 *
9 * Inspired by st-asc.c from STMicroelectronics (c)
10 */
11
Maxime Coquelin6b596a82015-06-16 11:12:19 +020012#if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
Maxime Coquelin48a60922015-06-10 21:19:36 +020013#define SUPPORT_SYSRQ
14#endif
15
Alexandre TORGUE34891872016-09-15 18:42:40 +020016#include <linux/clk.h>
Maxime Coquelin48a60922015-06-10 21:19:36 +020017#include <linux/console.h>
Maxime Coquelin48a60922015-06-10 21:19:36 +020018#include <linux/delay.h>
Alexandre TORGUE34891872016-09-15 18:42:40 +020019#include <linux/dma-direction.h>
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/io.h>
23#include <linux/iopoll.h>
24#include <linux/irq.h>
25#include <linux/module.h>
Maxime Coquelin48a60922015-06-10 21:19:36 +020026#include <linux/of.h>
27#include <linux/of_platform.h>
Alexandre TORGUE34891872016-09-15 18:42:40 +020028#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
Fabrice Gasnier270e5a72017-07-13 15:08:30 +000030#include <linux/pm_wakeirq.h>
Maxime Coquelin48a60922015-06-10 21:19:36 +020031#include <linux/serial_core.h>
Alexandre TORGUE34891872016-09-15 18:42:40 +020032#include <linux/serial.h>
33#include <linux/spinlock.h>
34#include <linux/sysrq.h>
35#include <linux/tty_flip.h>
36#include <linux/tty.h>
Maxime Coquelin48a60922015-06-10 21:19:36 +020037
Alexandre TORGUEbc5a0b52016-09-15 18:42:35 +020038#include "stm32-usart.h"
Maxime Coquelin48a60922015-06-10 21:19:36 +020039
40static void stm32_stop_tx(struct uart_port *port);
Alexandre TORGUE34891872016-09-15 18:42:40 +020041static void stm32_transmit_chars(struct uart_port *port);
Maxime Coquelin48a60922015-06-10 21:19:36 +020042
43static inline struct stm32_port *to_stm32_port(struct uart_port *port)
44{
45 return container_of(port, struct stm32_port, port);
46}
47
48static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
49{
50 u32 val;
51
52 val = readl_relaxed(port->membase + reg);
53 val |= bits;
54 writel_relaxed(val, port->membase + reg);
55}
56
57static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
58{
59 u32 val;
60
61 val = readl_relaxed(port->membase + reg);
62 val &= ~bits;
63 writel_relaxed(val, port->membase + reg);
64}
65
Baoyou Xieb97055b2016-09-26 19:58:56 +080066static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
67 bool threaded)
Alexandre TORGUE34891872016-09-15 18:42:40 +020068{
69 struct stm32_port *stm32_port = to_stm32_port(port);
70 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
71 enum dma_status status;
72 struct dma_tx_state state;
73
74 *sr = readl_relaxed(port->membase + ofs->isr);
75
76 if (threaded && stm32_port->rx_ch) {
77 status = dmaengine_tx_status(stm32_port->rx_ch,
78 stm32_port->rx_ch->cookie,
79 &state);
80 if ((status == DMA_IN_PROGRESS) &&
81 (*last_res != state.residue))
82 return 1;
83 else
84 return 0;
85 } else if (*sr & USART_SR_RXNE) {
86 return 1;
87 }
88 return 0;
89}
90
Baoyou Xieb97055b2016-09-26 19:58:56 +080091static unsigned long
92stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
Alexandre TORGUE34891872016-09-15 18:42:40 +020093{
94 struct stm32_port *stm32_port = to_stm32_port(port);
95 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
96 unsigned long c;
97
98 if (stm32_port->rx_ch) {
99 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
100 if ((*last_res) == 0)
101 *last_res = RX_BUF_L;
102 return c;
103 } else {
104 return readl_relaxed(port->membase + ofs->rdr);
105 }
106}
107
108static void stm32_receive_chars(struct uart_port *port, bool threaded)
Maxime Coquelin48a60922015-06-10 21:19:36 +0200109{
110 struct tty_port *tport = &port->state->port;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200111 struct stm32_port *stm32_port = to_stm32_port(port);
112 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200113 unsigned long c;
114 u32 sr;
115 char flag;
116
Andy Shevchenko29d60982017-08-13 17:47:41 +0300117 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
Maxime Coquelin48a60922015-06-10 21:19:36 +0200118 pm_wakeup_event(tport->tty->dev, 0);
119
Gerald Baezae5707912017-07-13 15:08:27 +0000120 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
Maxime Coquelin48a60922015-06-10 21:19:36 +0200121 sr |= USART_SR_DUMMY_RX;
Gerald Baezae5707912017-07-13 15:08:27 +0000122 c = stm32_get_char(port, &sr, &stm32_port->last_res);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200123 flag = TTY_NORMAL;
124 port->icount.rx++;
125
126 if (sr & USART_SR_ERR_MASK) {
127 if (sr & USART_SR_LBD) {
128 port->icount.brk++;
129 if (uart_handle_break(port))
130 continue;
131 } else if (sr & USART_SR_ORE) {
Alexandre TORGUEada86182016-09-15 18:42:33 +0200132 if (ofs->icr != UNDEF_REG)
133 writel_relaxed(USART_ICR_ORECF,
134 port->membase +
135 ofs->icr);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200136 port->icount.overrun++;
137 } else if (sr & USART_SR_PE) {
138 port->icount.parity++;
139 } else if (sr & USART_SR_FE) {
140 port->icount.frame++;
141 }
142
143 sr &= port->read_status_mask;
144
145 if (sr & USART_SR_LBD)
146 flag = TTY_BREAK;
147 else if (sr & USART_SR_PE)
148 flag = TTY_PARITY;
149 else if (sr & USART_SR_FE)
150 flag = TTY_FRAME;
151 }
152
153 if (uart_handle_sysrq_char(port, c))
154 continue;
155 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
156 }
157
158 spin_unlock(&port->lock);
159 tty_flip_buffer_push(tport);
160 spin_lock(&port->lock);
161}
162
Alexandre TORGUE34891872016-09-15 18:42:40 +0200163static void stm32_tx_dma_complete(void *arg)
164{
165 struct uart_port *port = arg;
166 struct stm32_port *stm32port = to_stm32_port(port);
167 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
168 unsigned int isr;
169 int ret;
170
171 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
172 isr,
173 (isr & USART_SR_TC),
174 10, 100000);
175
176 if (ret)
177 dev_err(port->dev, "terminal count not set\n");
178
179 if (ofs->icr == UNDEF_REG)
180 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
181 else
182 stm32_set_bits(port, ofs->icr, USART_CR_TC);
183
184 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
185 stm32port->tx_dma_busy = false;
186
187 /* Let's see if we have pending data to send */
188 stm32_transmit_chars(port);
189}
190
191static void stm32_transmit_chars_pio(struct uart_port *port)
192{
193 struct stm32_port *stm32_port = to_stm32_port(port);
194 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
195 struct circ_buf *xmit = &port->state->xmit;
196 unsigned int isr;
197 int ret;
198
199 if (stm32_port->tx_dma_busy) {
200 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
201 stm32_port->tx_dma_busy = false;
202 }
203
204 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
205 isr,
206 (isr & USART_SR_TXE),
Gerald Baezaa61d9e62017-07-31 09:31:52 +0000207 10, 100000);
Alexandre TORGUE34891872016-09-15 18:42:40 +0200208
209 if (ret)
210 dev_err(port->dev, "tx empty not set\n");
211
212 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
213
214 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
215 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
216 port->icount.tx++;
217}
218
219static void stm32_transmit_chars_dma(struct uart_port *port)
220{
221 struct stm32_port *stm32port = to_stm32_port(port);
222 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
223 struct circ_buf *xmit = &port->state->xmit;
224 struct dma_async_tx_descriptor *desc = NULL;
225 dma_cookie_t cookie;
226 unsigned int count, i;
227
228 if (stm32port->tx_dma_busy)
229 return;
230
231 stm32port->tx_dma_busy = true;
232
233 count = uart_circ_chars_pending(xmit);
234
235 if (count > TX_BUF_L)
236 count = TX_BUF_L;
237
238 if (xmit->tail < xmit->head) {
239 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
240 } else {
241 size_t one = UART_XMIT_SIZE - xmit->tail;
242 size_t two;
243
244 if (one > count)
245 one = count;
246 two = count - one;
247
248 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
249 if (two)
250 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
251 }
252
253 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
254 stm32port->tx_dma_buf,
255 count,
256 DMA_MEM_TO_DEV,
257 DMA_PREP_INTERRUPT);
258
259 if (!desc) {
260 for (i = count; i > 0; i--)
261 stm32_transmit_chars_pio(port);
262 return;
263 }
264
265 desc->callback = stm32_tx_dma_complete;
266 desc->callback_param = port;
267
268 /* Push current DMA TX transaction in the pending queue */
269 cookie = dmaengine_submit(desc);
270
271 /* Issue pending DMA TX requests */
272 dma_async_issue_pending(stm32port->tx_ch);
273
274 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
275 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
276
277 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
278 port->icount.tx += count;
279}
280
Maxime Coquelin48a60922015-06-10 21:19:36 +0200281static void stm32_transmit_chars(struct uart_port *port)
282{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200283 struct stm32_port *stm32_port = to_stm32_port(port);
284 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200285 struct circ_buf *xmit = &port->state->xmit;
286
287 if (port->x_char) {
Alexandre TORGUE34891872016-09-15 18:42:40 +0200288 if (stm32_port->tx_dma_busy)
289 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
Alexandre TORGUEada86182016-09-15 18:42:33 +0200290 writel_relaxed(port->x_char, port->membase + ofs->tdr);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200291 port->x_char = 0;
292 port->icount.tx++;
Alexandre TORGUE34891872016-09-15 18:42:40 +0200293 if (stm32_port->tx_dma_busy)
294 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200295 return;
296 }
297
298 if (uart_tx_stopped(port)) {
299 stm32_stop_tx(port);
300 return;
301 }
302
303 if (uart_circ_empty(xmit)) {
304 stm32_stop_tx(port);
305 return;
306 }
307
Alexandre TORGUE34891872016-09-15 18:42:40 +0200308 if (stm32_port->tx_ch)
309 stm32_transmit_chars_dma(port);
310 else
311 stm32_transmit_chars_pio(port);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200312
313 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
314 uart_write_wakeup(port);
315
316 if (uart_circ_empty(xmit))
317 stm32_stop_tx(port);
318}
319
320static irqreturn_t stm32_interrupt(int irq, void *ptr)
321{
322 struct uart_port *port = ptr;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200323 struct stm32_port *stm32_port = to_stm32_port(port);
324 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200325 u32 sr;
326
Alexandre TORGUE01d32d72016-09-15 18:42:41 +0200327 spin_lock(&port->lock);
328
Alexandre TORGUEada86182016-09-15 18:42:33 +0200329 sr = readl_relaxed(port->membase + ofs->isr);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200330
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000331 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
332 writel_relaxed(USART_ICR_WUCF,
333 port->membase + ofs->icr);
334
Alexandre TORGUE34891872016-09-15 18:42:40 +0200335 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
336 stm32_receive_chars(port, false);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200337
Alexandre TORGUE34891872016-09-15 18:42:40 +0200338 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
Maxime Coquelin48a60922015-06-10 21:19:36 +0200339 stm32_transmit_chars(port);
340
Alexandre TORGUE01d32d72016-09-15 18:42:41 +0200341 spin_unlock(&port->lock);
342
Alexandre TORGUE34891872016-09-15 18:42:40 +0200343 if (stm32_port->rx_ch)
344 return IRQ_WAKE_THREAD;
345 else
346 return IRQ_HANDLED;
347}
348
349static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
350{
351 struct uart_port *port = ptr;
352 struct stm32_port *stm32_port = to_stm32_port(port);
353
354 spin_lock(&port->lock);
355
356 if (stm32_port->rx_ch)
357 stm32_receive_chars(port, true);
358
Maxime Coquelin48a60922015-06-10 21:19:36 +0200359 spin_unlock(&port->lock);
360
361 return IRQ_HANDLED;
362}
363
364static unsigned int stm32_tx_empty(struct uart_port *port)
365{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200366 struct stm32_port *stm32_port = to_stm32_port(port);
367 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
368
369 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200370}
371
372static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
373{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200374 struct stm32_port *stm32_port = to_stm32_port(port);
375 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
376
Maxime Coquelin48a60922015-06-10 21:19:36 +0200377 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
Alexandre TORGUEada86182016-09-15 18:42:33 +0200378 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200379 else
Alexandre TORGUEada86182016-09-15 18:42:33 +0200380 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200381}
382
383static unsigned int stm32_get_mctrl(struct uart_port *port)
384{
385 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
386 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
387}
388
389/* Transmit stop */
390static void stm32_stop_tx(struct uart_port *port)
391{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200392 struct stm32_port *stm32_port = to_stm32_port(port);
393 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
394
395 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200396}
397
398/* There are probably characters waiting to be transmitted. */
399static void stm32_start_tx(struct uart_port *port)
400{
401 struct circ_buf *xmit = &port->state->xmit;
402
403 if (uart_circ_empty(xmit))
404 return;
405
Alexandre TORGUE34891872016-09-15 18:42:40 +0200406 stm32_transmit_chars(port);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200407}
408
409/* Throttle the remote when input buffer is about to overflow. */
410static void stm32_throttle(struct uart_port *port)
411{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200412 struct stm32_port *stm32_port = to_stm32_port(port);
413 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200414 unsigned long flags;
415
416 spin_lock_irqsave(&port->lock, flags);
Alexandre TORGUEada86182016-09-15 18:42:33 +0200417 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200418 spin_unlock_irqrestore(&port->lock, flags);
419}
420
421/* Unthrottle the remote, the input buffer can now accept data. */
422static void stm32_unthrottle(struct uart_port *port)
423{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200424 struct stm32_port *stm32_port = to_stm32_port(port);
425 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200426 unsigned long flags;
427
428 spin_lock_irqsave(&port->lock, flags);
Alexandre TORGUEada86182016-09-15 18:42:33 +0200429 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200430 spin_unlock_irqrestore(&port->lock, flags);
431}
432
433/* Receive stop */
434static void stm32_stop_rx(struct uart_port *port)
435{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200436 struct stm32_port *stm32_port = to_stm32_port(port);
437 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
438
439 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200440}
441
442/* Handle breaks - ignored by us */
443static void stm32_break_ctl(struct uart_port *port, int break_state)
444{
445}
446
447static int stm32_startup(struct uart_port *port)
448{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200449 struct stm32_port *stm32_port = to_stm32_port(port);
450 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000451 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200452 const char *name = to_platform_device(port->dev)->name;
453 u32 val;
454 int ret;
455
Alexandre TORGUE34891872016-09-15 18:42:40 +0200456 ret = request_threaded_irq(port->irq, stm32_interrupt,
457 stm32_threaded_interrupt,
458 IRQF_NO_SUSPEND, name, port);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200459 if (ret)
460 return ret;
461
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000462 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
463 ret = dev_pm_set_dedicated_wake_irq(port->dev,
464 stm32_port->wakeirq);
465 if (ret) {
466 free_irq(port->irq, port);
467 return ret;
468 }
469 }
470
Maxime Coquelin48a60922015-06-10 21:19:36 +0200471 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
Gerald Baeza351a7622017-07-13 15:08:30 +0000472 if (stm32_port->fifoen)
473 val |= USART_CR1_FIFOEN;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200474 stm32_set_bits(port, ofs->cr1, val);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200475
476 return 0;
477}
478
479static void stm32_shutdown(struct uart_port *port)
480{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200481 struct stm32_port *stm32_port = to_stm32_port(port);
482 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Alexandre TORGUE87f1f802016-09-15 18:42:42 +0200483 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200484 u32 val;
485
486 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
Alexandre TORGUE87f1f802016-09-15 18:42:42 +0200487 val |= BIT(cfg->uart_enable_bit);
Gerald Baeza351a7622017-07-13 15:08:30 +0000488 if (stm32_port->fifoen)
489 val |= USART_CR1_FIFOEN;
Alexandre TORGUEa14f66a2016-09-15 18:42:36 +0200490 stm32_clr_bits(port, ofs->cr1, val);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200491
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000492 dev_pm_clear_wake_irq(port->dev);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200493 free_irq(port->irq, port);
494}
495
496static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
497 struct ktermios *old)
498{
499 struct stm32_port *stm32_port = to_stm32_port(port);
Alexandre TORGUEada86182016-09-15 18:42:33 +0200500 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
501 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200502 unsigned int baud;
503 u32 usartdiv, mantissa, fraction, oversampling;
504 tcflag_t cflag = termios->c_cflag;
505 u32 cr1, cr2, cr3;
506 unsigned long flags;
507
508 if (!stm32_port->hw_flow_control)
509 cflag &= ~CRTSCTS;
510
511 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
512
513 spin_lock_irqsave(&port->lock, flags);
514
515 /* Stop serial port and reset value */
Alexandre TORGUEada86182016-09-15 18:42:33 +0200516 writel_relaxed(0, port->membase + ofs->cr1);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200517
Alexandre TORGUEada86182016-09-15 18:42:33 +0200518 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
519 cr1 |= BIT(cfg->uart_enable_bit);
Gerald Baeza351a7622017-07-13 15:08:30 +0000520 if (stm32_port->fifoen)
521 cr1 |= USART_CR1_FIFOEN;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200522 cr2 = 0;
523 cr3 = 0;
524
525 if (cflag & CSTOPB)
526 cr2 |= USART_CR2_STOP_2B;
527
528 if (cflag & PARENB) {
529 cr1 |= USART_CR1_PCE;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200530 if ((cflag & CSIZE) == CS8) {
531 if (cfg->has_7bits_data)
532 cr1 |= USART_CR1_M0;
533 else
534 cr1 |= USART_CR1_M;
535 }
Maxime Coquelin48a60922015-06-10 21:19:36 +0200536 }
537
538 if (cflag & PARODD)
539 cr1 |= USART_CR1_PS;
540
541 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
542 if (cflag & CRTSCTS) {
543 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
Bich HEMON35abe982017-07-13 15:08:28 +0000544 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200545 }
546
547 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
548
549 /*
550 * The USART supports 16 or 8 times oversampling.
551 * By default we prefer 16 times oversampling, so that the receiver
552 * has a better tolerance to clock deviations.
553 * 8 times oversampling is only used to achieve higher speeds.
554 */
555 if (usartdiv < 16) {
556 oversampling = 8;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200557 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200558 } else {
559 oversampling = 16;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200560 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200561 }
562
563 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
564 fraction = usartdiv % oversampling;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200565 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200566
567 uart_update_timeout(port, cflag, baud);
568
569 port->read_status_mask = USART_SR_ORE;
570 if (termios->c_iflag & INPCK)
571 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
572 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
573 port->read_status_mask |= USART_SR_LBD;
574
575 /* Characters to ignore */
576 port->ignore_status_mask = 0;
577 if (termios->c_iflag & IGNPAR)
578 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
579 if (termios->c_iflag & IGNBRK) {
580 port->ignore_status_mask |= USART_SR_LBD;
581 /*
582 * If we're ignoring parity and break indicators,
583 * ignore overruns too (for real raw support).
584 */
585 if (termios->c_iflag & IGNPAR)
586 port->ignore_status_mask |= USART_SR_ORE;
587 }
588
589 /* Ignore all characters if CREAD is not set */
590 if ((termios->c_cflag & CREAD) == 0)
591 port->ignore_status_mask |= USART_SR_DUMMY_RX;
592
Alexandre TORGUE34891872016-09-15 18:42:40 +0200593 if (stm32_port->rx_ch)
594 cr3 |= USART_CR3_DMAR;
595
Alexandre TORGUEada86182016-09-15 18:42:33 +0200596 writel_relaxed(cr3, port->membase + ofs->cr3);
597 writel_relaxed(cr2, port->membase + ofs->cr2);
598 writel_relaxed(cr1, port->membase + ofs->cr1);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200599
600 spin_unlock_irqrestore(&port->lock, flags);
601}
602
603static const char *stm32_type(struct uart_port *port)
604{
605 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
606}
607
608static void stm32_release_port(struct uart_port *port)
609{
610}
611
612static int stm32_request_port(struct uart_port *port)
613{
614 return 0;
615}
616
617static void stm32_config_port(struct uart_port *port, int flags)
618{
619 if (flags & UART_CONFIG_TYPE)
620 port->type = PORT_STM32;
621}
622
623static int
624stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
625{
626 /* No user changeable parameters */
627 return -EINVAL;
628}
629
630static void stm32_pm(struct uart_port *port, unsigned int state,
631 unsigned int oldstate)
632{
633 struct stm32_port *stm32port = container_of(port,
634 struct stm32_port, port);
Alexandre TORGUEada86182016-09-15 18:42:33 +0200635 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
636 struct stm32_usart_config *cfg = &stm32port->info->cfg;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200637 unsigned long flags = 0;
638
639 switch (state) {
640 case UART_PM_STATE_ON:
641 clk_prepare_enable(stm32port->clk);
642 break;
643 case UART_PM_STATE_OFF:
644 spin_lock_irqsave(&port->lock, flags);
Alexandre TORGUEada86182016-09-15 18:42:33 +0200645 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
Maxime Coquelin48a60922015-06-10 21:19:36 +0200646 spin_unlock_irqrestore(&port->lock, flags);
647 clk_disable_unprepare(stm32port->clk);
648 break;
649 }
650}
651
652static const struct uart_ops stm32_uart_ops = {
653 .tx_empty = stm32_tx_empty,
654 .set_mctrl = stm32_set_mctrl,
655 .get_mctrl = stm32_get_mctrl,
656 .stop_tx = stm32_stop_tx,
657 .start_tx = stm32_start_tx,
658 .throttle = stm32_throttle,
659 .unthrottle = stm32_unthrottle,
660 .stop_rx = stm32_stop_rx,
661 .break_ctl = stm32_break_ctl,
662 .startup = stm32_startup,
663 .shutdown = stm32_shutdown,
664 .set_termios = stm32_set_termios,
665 .pm = stm32_pm,
666 .type = stm32_type,
667 .release_port = stm32_release_port,
668 .request_port = stm32_request_port,
669 .config_port = stm32_config_port,
670 .verify_port = stm32_verify_port,
671};
672
673static int stm32_init_port(struct stm32_port *stm32port,
674 struct platform_device *pdev)
675{
676 struct uart_port *port = &stm32port->port;
677 struct resource *res;
678 int ret;
679
680 port->iotype = UPIO_MEM;
681 port->flags = UPF_BOOT_AUTOCONF;
682 port->ops = &stm32_uart_ops;
683 port->dev = &pdev->dev;
684 port->irq = platform_get_irq(pdev, 0);
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000685 stm32port->wakeirq = platform_get_irq(pdev, 1);
Gerald Baeza351a7622017-07-13 15:08:30 +0000686 stm32port->fifoen = stm32port->info->cfg.has_fifo;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200687
688 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689 port->membase = devm_ioremap_resource(&pdev->dev, res);
690 if (IS_ERR(port->membase))
691 return PTR_ERR(port->membase);
692 port->mapbase = res->start;
693
694 spin_lock_init(&port->lock);
695
696 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
697 if (IS_ERR(stm32port->clk))
698 return PTR_ERR(stm32port->clk);
699
700 /* Ensure that clk rate is correct by enabling the clk */
701 ret = clk_prepare_enable(stm32port->clk);
702 if (ret)
703 return ret;
704
705 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
Fabrice Gasnierada80042017-07-13 15:08:29 +0000706 if (!stm32port->port.uartclk) {
707 clk_disable_unprepare(stm32port->clk);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200708 ret = -EINVAL;
Fabrice Gasnierada80042017-07-13 15:08:29 +0000709 }
Maxime Coquelin48a60922015-06-10 21:19:36 +0200710
Maxime Coquelin48a60922015-06-10 21:19:36 +0200711 return ret;
712}
713
714static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
715{
716 struct device_node *np = pdev->dev.of_node;
717 int id;
718
719 if (!np)
720 return NULL;
721
722 id = of_alias_get_id(np, "serial");
Gerald Baezae5707912017-07-13 15:08:27 +0000723 if (id < 0) {
724 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
725 return NULL;
726 }
Maxime Coquelin48a60922015-06-10 21:19:36 +0200727
728 if (WARN_ON(id >= STM32_MAX_PORTS))
729 return NULL;
730
731 stm32_ports[id].hw_flow_control = of_property_read_bool(np,
Alexandre TORGUE59bed2d2016-09-15 18:42:37 +0200732 "st,hw-flow-ctrl");
Maxime Coquelin48a60922015-06-10 21:19:36 +0200733 stm32_ports[id].port.line = id;
Gerald Baezae5707912017-07-13 15:08:27 +0000734 stm32_ports[id].last_res = RX_BUF_L;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200735 return &stm32_ports[id];
736}
737
738#ifdef CONFIG_OF
739static const struct of_device_id stm32_match[] = {
Alexandre TORGUEada86182016-09-15 18:42:33 +0200740 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
Alexandre TORGUEada86182016-09-15 18:42:33 +0200741 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000742 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
Maxime Coquelin48a60922015-06-10 21:19:36 +0200743 {},
744};
745
746MODULE_DEVICE_TABLE(of, stm32_match);
747#endif
748
Alexandre TORGUE34891872016-09-15 18:42:40 +0200749static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
750 struct platform_device *pdev)
751{
752 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
753 struct uart_port *port = &stm32port->port;
754 struct device *dev = &pdev->dev;
755 struct dma_slave_config config;
756 struct dma_async_tx_descriptor *desc = NULL;
757 dma_cookie_t cookie;
758 int ret;
759
760 /* Request DMA RX channel */
761 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
762 if (!stm32port->rx_ch) {
763 dev_info(dev, "rx dma alloc failed\n");
764 return -ENODEV;
765 }
766 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
767 &stm32port->rx_dma_buf,
768 GFP_KERNEL);
769 if (!stm32port->rx_buf) {
770 ret = -ENOMEM;
771 goto alloc_err;
772 }
773
774 /* Configure DMA channel */
775 memset(&config, 0, sizeof(config));
Arnd Bergmann8e5481d2016-09-23 21:38:51 +0200776 config.src_addr = port->mapbase + ofs->rdr;
Alexandre TORGUE34891872016-09-15 18:42:40 +0200777 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
778
779 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
780 if (ret < 0) {
781 dev_err(dev, "rx dma channel config failed\n");
782 ret = -ENODEV;
783 goto config_err;
784 }
785
786 /* Prepare a DMA cyclic transaction */
787 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
788 stm32port->rx_dma_buf,
789 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
790 DMA_PREP_INTERRUPT);
791 if (!desc) {
792 dev_err(dev, "rx dma prep cyclic failed\n");
793 ret = -ENODEV;
794 goto config_err;
795 }
796
797 /* No callback as dma buffer is drained on usart interrupt */
798 desc->callback = NULL;
799 desc->callback_param = NULL;
800
801 /* Push current DMA transaction in the pending queue */
802 cookie = dmaengine_submit(desc);
803
804 /* Issue pending DMA requests */
805 dma_async_issue_pending(stm32port->rx_ch);
806
807 return 0;
808
809config_err:
810 dma_free_coherent(&pdev->dev,
811 RX_BUF_L, stm32port->rx_buf,
812 stm32port->rx_dma_buf);
813
814alloc_err:
815 dma_release_channel(stm32port->rx_ch);
816 stm32port->rx_ch = NULL;
817
818 return ret;
819}
820
821static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
822 struct platform_device *pdev)
823{
824 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
825 struct uart_port *port = &stm32port->port;
826 struct device *dev = &pdev->dev;
827 struct dma_slave_config config;
828 int ret;
829
830 stm32port->tx_dma_busy = false;
831
832 /* Request DMA TX channel */
833 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
834 if (!stm32port->tx_ch) {
835 dev_info(dev, "tx dma alloc failed\n");
836 return -ENODEV;
837 }
838 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
839 &stm32port->tx_dma_buf,
840 GFP_KERNEL);
841 if (!stm32port->tx_buf) {
842 ret = -ENOMEM;
843 goto alloc_err;
844 }
845
846 /* Configure DMA channel */
847 memset(&config, 0, sizeof(config));
Arnd Bergmann8e5481d2016-09-23 21:38:51 +0200848 config.dst_addr = port->mapbase + ofs->tdr;
Alexandre TORGUE34891872016-09-15 18:42:40 +0200849 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
850
851 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
852 if (ret < 0) {
853 dev_err(dev, "tx dma channel config failed\n");
854 ret = -ENODEV;
855 goto config_err;
856 }
857
858 return 0;
859
860config_err:
861 dma_free_coherent(&pdev->dev,
862 TX_BUF_L, stm32port->tx_buf,
863 stm32port->tx_dma_buf);
864
865alloc_err:
866 dma_release_channel(stm32port->tx_ch);
867 stm32port->tx_ch = NULL;
868
869 return ret;
870}
871
Maxime Coquelin48a60922015-06-10 21:19:36 +0200872static int stm32_serial_probe(struct platform_device *pdev)
873{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200874 const struct of_device_id *match;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200875 struct stm32_port *stm32port;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200876 int ret;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200877
878 stm32port = stm32_of_get_stm32_port(pdev);
879 if (!stm32port)
880 return -ENODEV;
881
Alexandre TORGUEada86182016-09-15 18:42:33 +0200882 match = of_match_device(stm32_match, &pdev->dev);
883 if (match && match->data)
884 stm32port->info = (struct stm32_usart_info *)match->data;
885 else
886 return -EINVAL;
887
Maxime Coquelin48a60922015-06-10 21:19:36 +0200888 ret = stm32_init_port(stm32port, pdev);
889 if (ret)
890 return ret;
891
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000892 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
893 ret = device_init_wakeup(&pdev->dev, true);
894 if (ret)
895 goto err_uninit;
896 }
897
Maxime Coquelin48a60922015-06-10 21:19:36 +0200898 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
899 if (ret)
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000900 goto err_nowup;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200901
Alexandre TORGUE34891872016-09-15 18:42:40 +0200902 ret = stm32_of_dma_rx_probe(stm32port, pdev);
903 if (ret)
904 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
905
906 ret = stm32_of_dma_tx_probe(stm32port, pdev);
907 if (ret)
908 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
909
Maxime Coquelin48a60922015-06-10 21:19:36 +0200910 platform_set_drvdata(pdev, &stm32port->port);
911
912 return 0;
Fabrice Gasnierada80042017-07-13 15:08:29 +0000913
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000914err_nowup:
915 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
916 device_init_wakeup(&pdev->dev, false);
917
Fabrice Gasnierada80042017-07-13 15:08:29 +0000918err_uninit:
919 clk_disable_unprepare(stm32port->clk);
920
921 return ret;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200922}
923
924static int stm32_serial_remove(struct platform_device *pdev)
925{
926 struct uart_port *port = platform_get_drvdata(pdev);
Alexandre TORGUE511c7b12016-09-15 18:42:38 +0200927 struct stm32_port *stm32_port = to_stm32_port(port);
Alexandre TORGUE34891872016-09-15 18:42:40 +0200928 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000929 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
Alexandre TORGUE34891872016-09-15 18:42:40 +0200930
931 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
932
933 if (stm32_port->rx_ch)
934 dma_release_channel(stm32_port->rx_ch);
935
936 if (stm32_port->rx_dma_buf)
937 dma_free_coherent(&pdev->dev,
938 RX_BUF_L, stm32_port->rx_buf,
939 stm32_port->rx_dma_buf);
940
941 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
942
943 if (stm32_port->tx_ch)
944 dma_release_channel(stm32_port->tx_ch);
945
946 if (stm32_port->tx_dma_buf)
947 dma_free_coherent(&pdev->dev,
948 TX_BUF_L, stm32_port->tx_buf,
949 stm32_port->tx_dma_buf);
Alexandre TORGUE511c7b12016-09-15 18:42:38 +0200950
Fabrice Gasnier270e5a72017-07-13 15:08:30 +0000951 if (cfg->has_wakeup && stm32_port->wakeirq >= 0)
952 device_init_wakeup(&pdev->dev, false);
953
Alexandre TORGUE511c7b12016-09-15 18:42:38 +0200954 clk_disable_unprepare(stm32_port->clk);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200955
956 return uart_remove_one_port(&stm32_usart_driver, port);
957}
958
959
960#ifdef CONFIG_SERIAL_STM32_CONSOLE
961static void stm32_console_putchar(struct uart_port *port, int ch)
962{
Alexandre TORGUEada86182016-09-15 18:42:33 +0200963 struct stm32_port *stm32_port = to_stm32_port(port);
964 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
965
966 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
Maxime Coquelin48a60922015-06-10 21:19:36 +0200967 cpu_relax();
968
Alexandre TORGUEada86182016-09-15 18:42:33 +0200969 writel_relaxed(ch, port->membase + ofs->tdr);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200970}
971
972static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
973{
974 struct uart_port *port = &stm32_ports[co->index].port;
Alexandre TORGUEada86182016-09-15 18:42:33 +0200975 struct stm32_port *stm32_port = to_stm32_port(port);
976 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
Alexandre TORGUE87f1f802016-09-15 18:42:42 +0200977 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
Maxime Coquelin48a60922015-06-10 21:19:36 +0200978 unsigned long flags;
979 u32 old_cr1, new_cr1;
980 int locked = 1;
981
982 local_irq_save(flags);
983 if (port->sysrq)
984 locked = 0;
985 else if (oops_in_progress)
986 locked = spin_trylock(&port->lock);
987 else
988 spin_lock(&port->lock);
989
Alexandre TORGUE87f1f802016-09-15 18:42:42 +0200990 /* Save and disable interrupts, enable the transmitter */
Alexandre TORGUEada86182016-09-15 18:42:33 +0200991 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200992 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
Alexandre TORGUE87f1f802016-09-15 18:42:42 +0200993 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
Alexandre TORGUEada86182016-09-15 18:42:33 +0200994 writel_relaxed(new_cr1, port->membase + ofs->cr1);
Maxime Coquelin48a60922015-06-10 21:19:36 +0200995
996 uart_console_write(port, s, cnt, stm32_console_putchar);
997
998 /* Restore interrupt state */
Alexandre TORGUEada86182016-09-15 18:42:33 +0200999 writel_relaxed(old_cr1, port->membase + ofs->cr1);
Maxime Coquelin48a60922015-06-10 21:19:36 +02001000
1001 if (locked)
1002 spin_unlock(&port->lock);
1003 local_irq_restore(flags);
1004}
1005
1006static int stm32_console_setup(struct console *co, char *options)
1007{
1008 struct stm32_port *stm32port;
1009 int baud = 9600;
1010 int bits = 8;
1011 int parity = 'n';
1012 int flow = 'n';
1013
1014 if (co->index >= STM32_MAX_PORTS)
1015 return -ENODEV;
1016
1017 stm32port = &stm32_ports[co->index];
1018
1019 /*
1020 * This driver does not support early console initialization
1021 * (use ARM early printk support instead), so we only expect
1022 * this to be called during the uart port registration when the
1023 * driver gets probed and the port should be mapped at that point.
1024 */
1025 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1026 return -ENXIO;
1027
1028 if (options)
1029 uart_parse_options(options, &baud, &parity, &bits, &flow);
1030
1031 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1032}
1033
1034static struct console stm32_console = {
1035 .name = STM32_SERIAL_NAME,
1036 .device = uart_console_device,
1037 .write = stm32_console_write,
1038 .setup = stm32_console_setup,
1039 .flags = CON_PRINTBUFFER,
1040 .index = -1,
1041 .data = &stm32_usart_driver,
1042};
1043
1044#define STM32_SERIAL_CONSOLE (&stm32_console)
1045
1046#else
1047#define STM32_SERIAL_CONSOLE NULL
1048#endif /* CONFIG_SERIAL_STM32_CONSOLE */
1049
1050static struct uart_driver stm32_usart_driver = {
1051 .driver_name = DRIVER_NAME,
1052 .dev_name = STM32_SERIAL_NAME,
1053 .major = 0,
1054 .minor = 0,
1055 .nr = STM32_MAX_PORTS,
1056 .cons = STM32_SERIAL_CONSOLE,
1057};
1058
Fabrice Gasnier270e5a72017-07-13 15:08:30 +00001059#ifdef CONFIG_PM_SLEEP
1060static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1061{
1062 struct stm32_port *stm32_port = to_stm32_port(port);
1063 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1064 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1065 u32 val;
1066
1067 if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1068 return;
1069
1070 if (enable) {
1071 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1072 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1073 val = readl_relaxed(port->membase + ofs->cr3);
1074 val &= ~USART_CR3_WUS_MASK;
1075 /* Enable Wake up interrupt from low power on start bit */
1076 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1077 writel_relaxed(val, port->membase + ofs->cr3);
1078 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1079 } else {
1080 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1081 }
1082}
1083
1084static int stm32_serial_suspend(struct device *dev)
1085{
1086 struct uart_port *port = dev_get_drvdata(dev);
1087
1088 uart_suspend_port(&stm32_usart_driver, port);
1089
1090 if (device_may_wakeup(dev))
1091 stm32_serial_enable_wakeup(port, true);
1092 else
1093 stm32_serial_enable_wakeup(port, false);
1094
1095 return 0;
1096}
1097
1098static int stm32_serial_resume(struct device *dev)
1099{
1100 struct uart_port *port = dev_get_drvdata(dev);
1101
1102 if (device_may_wakeup(dev))
1103 stm32_serial_enable_wakeup(port, false);
1104
1105 return uart_resume_port(&stm32_usart_driver, port);
1106}
1107#endif /* CONFIG_PM_SLEEP */
1108
1109static const struct dev_pm_ops stm32_serial_pm_ops = {
1110 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1111};
1112
Maxime Coquelin48a60922015-06-10 21:19:36 +02001113static struct platform_driver stm32_serial_driver = {
1114 .probe = stm32_serial_probe,
1115 .remove = stm32_serial_remove,
1116 .driver = {
1117 .name = DRIVER_NAME,
Fabrice Gasnier270e5a72017-07-13 15:08:30 +00001118 .pm = &stm32_serial_pm_ops,
Maxime Coquelin48a60922015-06-10 21:19:36 +02001119 .of_match_table = of_match_ptr(stm32_match),
1120 },
1121};
1122
1123static int __init usart_init(void)
1124{
1125 static char banner[] __initdata = "STM32 USART driver initialized";
1126 int ret;
1127
1128 pr_info("%s\n", banner);
1129
1130 ret = uart_register_driver(&stm32_usart_driver);
1131 if (ret)
1132 return ret;
1133
1134 ret = platform_driver_register(&stm32_serial_driver);
1135 if (ret)
1136 uart_unregister_driver(&stm32_usart_driver);
1137
1138 return ret;
1139}
1140
1141static void __exit usart_exit(void)
1142{
1143 platform_driver_unregister(&stm32_serial_driver);
1144 uart_unregister_driver(&stm32_usart_driver);
1145}
1146
1147module_init(usart_init);
1148module_exit(usart_exit);
1149
1150MODULE_ALIAS("platform:" DRIVER_NAME);
1151MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1152MODULE_LICENSE("GPL v2");