| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * m532xsim.h -- ColdFire 5329 registers |
| 5 | */ |
| 6 | |
| 7 | /****************************************************************************/ |
| 8 | #ifndef m532xsim_h |
| 9 | #define m532xsim_h |
| 10 | /****************************************************************************/ |
| 11 | |
| Greg Ungerer | 733f31b | 2010-11-02 17:40:37 +1000 | [diff] [blame] | 12 | #define CPU_NAME "COLDFIRE(m532x)" |
| 13 | #define CPU_INSTR_PER_JIFFY 3 |
| Greg Ungerer | ce3de78 | 2011-03-09 14:19:08 +1000 | [diff] [blame] | 14 | #define MCF_BUSCLK (MCF_CLK / 3) |
| Greg Ungerer | 7fc82b6 | 2010-11-02 17:13:27 +1000 | [diff] [blame] | 15 | |
| Greg Ungerer | 278c2cb | 2010-11-09 10:19:45 +1000 | [diff] [blame] | 16 | #include <asm/m53xxacr.h> |
| 17 | |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 18 | #define MCF_REG32(x) (*(volatile unsigned long *)(x)) |
| 19 | #define MCF_REG16(x) (*(volatile unsigned short *)(x)) |
| 20 | #define MCF_REG08(x) (*(volatile unsigned char *)(x)) |
| 21 | |
| 22 | #define MCFINT_VECBASE 64 |
| 23 | #define MCFINT_UART0 26 /* Interrupt number for UART0 */ |
| 24 | #define MCFINT_UART1 27 /* Interrupt number for UART1 */ |
| Greg Ungerer | e2545b6 | 2009-02-12 16:02:05 +1000 | [diff] [blame] | 25 | #define MCFINT_UART2 28 /* Interrupt number for UART2 */ |
| Steven King | 91d6041 | 2010-01-22 12:43:03 -0800 | [diff] [blame] | 26 | #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ |
| Greg Ungerer | 5046954 | 2011-12-24 10:23:01 +1000 | [diff] [blame] | 27 | #define MCFINT_FECRX0 36 /* Interrupt number for FEC */ |
| 28 | #define MCFINT_FECTX0 40 /* Interrupt number for FEC */ |
| 29 | #define MCFINT_FECENTC0 42 /* Interrupt number for FEC */ |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 30 | |
| Greg Ungerer | 35b7cf2 | 2011-12-24 00:41:07 +1000 | [diff] [blame] | 31 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
| 32 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) |
| 33 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) |
| 34 | |
| Greg Ungerer | 5046954 | 2011-12-24 10:23:01 +1000 | [diff] [blame] | 35 | #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
| 36 | #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) |
| 37 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
| 38 | |
| Greg Ungerer | ed8a279 | 2011-12-24 12:44:45 +1000 | [diff] [blame] | 39 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| 40 | |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 41 | #define MCF_WTM_WCR MCF_REG16(0xFC098000) |
| 42 | |
| 43 | /* |
| 44 | * Define the 532x SIM register set addresses. |
| 45 | */ |
| 46 | #define MCFSIM_IPRL 0xFC048004 |
| 47 | #define MCFSIM_IPRH 0xFC048000 |
| 48 | #define MCFSIM_IPR MCFSIM_IPRL |
| 49 | #define MCFSIM_IMRL 0xFC04800C |
| 50 | #define MCFSIM_IMRH 0xFC048008 |
| 51 | #define MCFSIM_IMR MCFSIM_IMRL |
| 52 | #define MCFSIM_ICR0 0xFC048040 |
| 53 | #define MCFSIM_ICR1 0xFC048041 |
| 54 | #define MCFSIM_ICR2 0xFC048042 |
| 55 | #define MCFSIM_ICR3 0xFC048043 |
| 56 | #define MCFSIM_ICR4 0xFC048044 |
| 57 | #define MCFSIM_ICR5 0xFC048045 |
| 58 | #define MCFSIM_ICR6 0xFC048046 |
| 59 | #define MCFSIM_ICR7 0xFC048047 |
| 60 | #define MCFSIM_ICR8 0xFC048048 |
| 61 | #define MCFSIM_ICR9 0xFC048049 |
| 62 | #define MCFSIM_ICR10 0xFC04804A |
| 63 | #define MCFSIM_ICR11 0xFC04804B |
| 64 | |
| 65 | /* |
| 66 | * Some symbol defines for the above... |
| 67 | */ |
| 68 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ |
| 69 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ |
| 70 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ |
| 71 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ |
| 72 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ |
| 73 | #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ |
| 74 | #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ |
| 75 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ |
| 76 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ |
| 77 | |
| 78 | |
| Greg Ungerer | 277c5e3 | 2009-04-29 12:07:13 +1000 | [diff] [blame] | 79 | #define MCFINTC0_SIMR 0xFC04801C |
| 80 | #define MCFINTC0_CIMR 0xFC04801D |
| 81 | #define MCFINTC0_ICR0 0xFC048040 |
| 82 | #define MCFINTC1_SIMR 0xFC04C01C |
| 83 | #define MCFINTC1_CIMR 0xFC04C01D |
| 84 | #define MCFINTC1_ICR0 0xFC04C040 |
| Steven King | 3223432 | 2012-06-08 14:15:29 -0700 | [diff] [blame] | 85 | #define MCFINTC2_SIMR (0) |
| 86 | #define MCFINTC2_CIMR (0) |
| 87 | #define MCFINTC2_ICR0 (0) |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 88 | |
| 89 | #define MCFSIM_ICR_TIMER1 (0xFC048040+32) |
| 90 | #define MCFSIM_ICR_TIMER2 (0xFC048040+33) |
| 91 | |
| Greg Ungerer | f6a6627 | 2009-05-19 15:00:01 +1000 | [diff] [blame] | 92 | /* |
| 93 | * Define system peripheral IRQ usage. |
| 94 | */ |
| 95 | #define MCF_IRQ_TIMER (64 + 32) /* Timer0 */ |
| 96 | #define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */ |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 97 | |
| 98 | /* |
| Greg Ungerer | 5701542 | 2010-11-03 12:50:30 +1000 | [diff] [blame] | 99 | * UART module. |
| 100 | */ |
| Greg Ungerer | 35b7cf2 | 2011-12-24 00:41:07 +1000 | [diff] [blame] | 101 | #define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */ |
| 102 | #define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */ |
| 103 | #define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */ |
| Greg Ungerer | 5701542 | 2010-11-03 12:50:30 +1000 | [diff] [blame] | 104 | |
| Greg Ungerer | 58f0ac9 | 2011-03-09 09:57:14 +1000 | [diff] [blame] | 105 | /* |
| Greg Ungerer | 5046954 | 2011-12-24 10:23:01 +1000 | [diff] [blame] | 106 | * FEC module. |
| 107 | */ |
| 108 | #define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */ |
| 109 | #define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */ |
| 110 | |
| 111 | /* |
| Greg Ungerer | ed8a279 | 2011-12-24 12:44:45 +1000 | [diff] [blame] | 112 | * QSPI module. |
| 113 | */ |
| 114 | #define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */ |
| 115 | #define MCFQSPI_SIZE 0x40 /* Size of QSPI region */ |
| 116 | |
| 117 | #define MCFQSPI_CS0 84 |
| 118 | #define MCFQSPI_CS1 85 |
| 119 | #define MCFQSPI_CS2 86 |
| 120 | |
| 121 | /* |
| Greg Ungerer | 58f0ac9 | 2011-03-09 09:57:14 +1000 | [diff] [blame] | 122 | * Timer module. |
| 123 | */ |
| 124 | #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */ |
| 125 | #define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */ |
| 126 | #define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */ |
| 127 | #define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */ |
| 128 | |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 129 | /********************************************************************* |
| 130 | * |
| Greg Ungerer | 384feb9 | 2009-04-30 22:03:43 +1000 | [diff] [blame] | 131 | * Reset Controller Module |
| 132 | * |
| 133 | *********************************************************************/ |
| 134 | |
| 135 | #define MCF_RCR 0xFC0A0000 |
| 136 | #define MCF_RSR 0xFC0A0001 |
| 137 | |
| 138 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| 139 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| 140 | |
| Steven King | 12ce4c1 | 2012-06-17 00:41:39 -0700 | [diff] [blame] | 141 | |
| 142 | /* |
| 143 | * Power Management |
| 144 | */ |
| 145 | #define MCFPM_WCR 0xfc040013 |
| 146 | #define MCFPM_PPMSR0 0xfc04002c |
| 147 | #define MCFPM_PPMCR0 0xfc04002d |
| 148 | #define MCFPM_PPMSR1 0xfc04002e |
| 149 | #define MCFPM_PPMCR1 0xfc04002f |
| 150 | #define MCFPM_PPMHR0 0xfc040030 |
| 151 | #define MCFPM_PPMLR0 0xfc040034 |
| 152 | #define MCFPM_PPMHR1 0xfc040038 |
| 153 | #define MCFPM_LPCR 0xec090007 |
| 154 | |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 155 | /* |
| 156 | * The M5329EVB board needs a help getting its devices initialized |
| 157 | * at kernel start time if dBUG doesn't set it up (for example |
| 158 | * it is not used), so we need to do it manually. |
| 159 | */ |
| 160 | #ifdef __ASSEMBLER__ |
| 161 | .macro m5329EVB_setup |
| 162 | movel #0xFC098000, %a7 |
| 163 | movel #0x0, (%a7) |
| 164 | #define CORE_SRAM 0x80000000 |
| 165 | #define CORE_SRAM_SIZE 0x8000 |
| 166 | movel #CORE_SRAM, %d0 |
| 167 | addl #0x221, %d0 |
| 168 | movec %d0,%RAMBAR1 |
| 169 | movel #CORE_SRAM, %sp |
| 170 | addl #CORE_SRAM_SIZE, %sp |
| 171 | jsr sysinit |
| 172 | .endm |
| 173 | #define PLATFORM_SETUP m5329EVB_setup |
| 174 | |
| 175 | #endif /* __ASSEMBLER__ */ |
| 176 | |
| 177 | /********************************************************************* |
| 178 | * |
| 179 | * Chip Configuration Module (CCM) |
| 180 | * |
| 181 | *********************************************************************/ |
| 182 | |
| 183 | /* Register read/write macros */ |
| 184 | #define MCF_CCM_CCR MCF_REG16(0xFC0A0004) |
| 185 | #define MCF_CCM_RCON MCF_REG16(0xFC0A0008) |
| 186 | #define MCF_CCM_CIR MCF_REG16(0xFC0A000A) |
| 187 | #define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) |
| 188 | #define MCF_CCM_CDR MCF_REG16(0xFC0A0012) |
| 189 | #define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014) |
| 190 | #define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016) |
| 191 | |
| 192 | /* Bit definitions and macros for MCF_CCM_CCR */ |
| 193 | #define MCF_CCM_CCR_RESERVED (0x0001) |
| 194 | #define MCF_CCM_CCR_PLL_MODE (0x0003) |
| 195 | #define MCF_CCM_CCR_OSC_MODE (0x0005) |
| 196 | #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) |
| 197 | #define MCF_CCM_CCR_LOAD (0x0021) |
| 198 | #define MCF_CCM_CCR_LIMP (0x0041) |
| 199 | #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) |
| 200 | |
| 201 | /* Bit definitions and macros for MCF_CCM_RCON */ |
| 202 | #define MCF_CCM_RCON_RESERVED (0x0001) |
| 203 | #define MCF_CCM_RCON_PLL_MODE (0x0003) |
| 204 | #define MCF_CCM_RCON_OSC_MODE (0x0005) |
| 205 | #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) |
| 206 | #define MCF_CCM_RCON_LOAD (0x0021) |
| 207 | #define MCF_CCM_RCON_LIMP (0x0041) |
| 208 | #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) |
| 209 | |
| 210 | /* Bit definitions and macros for MCF_CCM_CIR */ |
| 211 | #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) |
| 212 | #define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) |
| 213 | |
| 214 | /* Bit definitions and macros for MCF_CCM_MISCCR */ |
| 215 | #define MCF_CCM_MISCCR_USBSRC (0x0001) |
| 216 | #define MCF_CCM_MISCCR_USBDIV (0x0002) |
| 217 | #define MCF_CCM_MISCCR_SSI_SRC (0x0010) |
| 218 | #define MCF_CCM_MISCCR_TIM_DMA (0x0020) |
| 219 | #define MCF_CCM_MISCCR_SSI_PUS (0x0040) |
| 220 | #define MCF_CCM_MISCCR_SSI_PUE (0x0080) |
| 221 | #define MCF_CCM_MISCCR_LCD_CHEN (0x0100) |
| 222 | #define MCF_CCM_MISCCR_LIMP (0x1000) |
| 223 | #define MCF_CCM_MISCCR_PLL_LOCK (0x2000) |
| 224 | |
| 225 | /* Bit definitions and macros for MCF_CCM_CDR */ |
| 226 | #define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0) |
| 227 | #define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) |
| 228 | |
| 229 | /* Bit definitions and macros for MCF_CCM_UHCSR */ |
| 230 | #define MCF_CCM_UHCSR_XPDE (0x0001) |
| 231 | #define MCF_CCM_UHCSR_UHMIE (0x0002) |
| 232 | #define MCF_CCM_UHCSR_WKUP (0x0004) |
| 233 | #define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) |
| 234 | |
| 235 | /* Bit definitions and macros for MCF_CCM_UOCSR */ |
| 236 | #define MCF_CCM_UOCSR_XPDE (0x0001) |
| 237 | #define MCF_CCM_UOCSR_UOMIE (0x0002) |
| 238 | #define MCF_CCM_UOCSR_WKUP (0x0004) |
| 239 | #define MCF_CCM_UOCSR_PWRFLT (0x0008) |
| 240 | #define MCF_CCM_UOCSR_SEND (0x0010) |
| 241 | #define MCF_CCM_UOCSR_VVLD (0x0020) |
| 242 | #define MCF_CCM_UOCSR_BVLD (0x0040) |
| 243 | #define MCF_CCM_UOCSR_AVLD (0x0080) |
| 244 | #define MCF_CCM_UOCSR_DPPU (0x0100) |
| 245 | #define MCF_CCM_UOCSR_DCR_VBUS (0x0200) |
| 246 | #define MCF_CCM_UOCSR_CRG_VBUS (0x0400) |
| 247 | #define MCF_CCM_UOCSR_DRV_VBUS (0x0800) |
| 248 | #define MCF_CCM_UOCSR_DMPD (0x1000) |
| 249 | #define MCF_CCM_UOCSR_DPPD (0x2000) |
| 250 | #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) |
| 251 | |
| 252 | /********************************************************************* |
| 253 | * |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 254 | * FlexBus Chip Selects (FBCS) |
| 255 | * |
| 256 | *********************************************************************/ |
| 257 | |
| 258 | /* Register read/write macros */ |
| 259 | #define MCF_FBCS0_CSAR MCF_REG32(0xFC008000) |
| 260 | #define MCF_FBCS0_CSMR MCF_REG32(0xFC008004) |
| 261 | #define MCF_FBCS0_CSCR MCF_REG32(0xFC008008) |
| 262 | #define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C) |
| 263 | #define MCF_FBCS1_CSMR MCF_REG32(0xFC008010) |
| 264 | #define MCF_FBCS1_CSCR MCF_REG32(0xFC008014) |
| 265 | #define MCF_FBCS2_CSAR MCF_REG32(0xFC008018) |
| 266 | #define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C) |
| 267 | #define MCF_FBCS2_CSCR MCF_REG32(0xFC008020) |
| 268 | #define MCF_FBCS3_CSAR MCF_REG32(0xFC008024) |
| 269 | #define MCF_FBCS3_CSMR MCF_REG32(0xFC008028) |
| 270 | #define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C) |
| 271 | #define MCF_FBCS4_CSAR MCF_REG32(0xFC008030) |
| 272 | #define MCF_FBCS4_CSMR MCF_REG32(0xFC008034) |
| 273 | #define MCF_FBCS4_CSCR MCF_REG32(0xFC008038) |
| 274 | #define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C) |
| 275 | #define MCF_FBCS5_CSMR MCF_REG32(0xFC008040) |
| 276 | #define MCF_FBCS5_CSCR MCF_REG32(0xFC008044) |
| 277 | #define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) |
| 278 | #define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) |
| 279 | #define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) |
| 280 | |
| 281 | /* Bit definitions and macros for MCF_FBCS_CSAR */ |
| 282 | #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) |
| 283 | |
| 284 | /* Bit definitions and macros for MCF_FBCS_CSMR */ |
| 285 | #define MCF_FBCS_CSMR_V (0x00000001) |
| 286 | #define MCF_FBCS_CSMR_WP (0x00000100) |
| 287 | #define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) |
| 288 | #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) |
| 289 | #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) |
| 290 | #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) |
| 291 | #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) |
| 292 | #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) |
| 293 | #define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) |
| 294 | #define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) |
| 295 | #define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) |
| 296 | #define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) |
| 297 | #define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) |
| 298 | #define MCF_FBCS_CSMR_BAM_8M (0x007F0000) |
| 299 | #define MCF_FBCS_CSMR_BAM_4M (0x003F0000) |
| 300 | #define MCF_FBCS_CSMR_BAM_2M (0x001F0000) |
| 301 | #define MCF_FBCS_CSMR_BAM_1M (0x000F0000) |
| 302 | #define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) |
| 303 | #define MCF_FBCS_CSMR_BAM_512K (0x00070000) |
| 304 | #define MCF_FBCS_CSMR_BAM_256K (0x00030000) |
| 305 | #define MCF_FBCS_CSMR_BAM_128K (0x00010000) |
| 306 | #define MCF_FBCS_CSMR_BAM_64K (0x00000000) |
| 307 | |
| 308 | /* Bit definitions and macros for MCF_FBCS_CSCR */ |
| 309 | #define MCF_FBCS_CSCR_BSTW (0x00000008) |
| 310 | #define MCF_FBCS_CSCR_BSTR (0x00000010) |
| 311 | #define MCF_FBCS_CSCR_BEM (0x00000020) |
| 312 | #define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) |
| 313 | #define MCF_FBCS_CSCR_AA (0x00000100) |
| 314 | #define MCF_FBCS_CSCR_SBM (0x00000200) |
| 315 | #define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) |
| 316 | #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) |
| 317 | #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) |
| 318 | #define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) |
| 319 | #define MCF_FBCS_CSCR_SWSEN (0x00800000) |
| 320 | #define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) |
| 321 | #define MCF_FBCS_CSCR_PS_8 (0x0040) |
| 322 | #define MCF_FBCS_CSCR_PS_16 (0x0080) |
| 323 | #define MCF_FBCS_CSCR_PS_32 (0x0000) |
| 324 | |
| 325 | /********************************************************************* |
| 326 | * |
| 327 | * General Purpose I/O (GPIO) |
| 328 | * |
| 329 | *********************************************************************/ |
| 330 | |
| 331 | /* Register read/write macros */ |
| sfking@fdwdc.com | 7846fe8 | 2009-06-19 18:11:10 -0700 | [diff] [blame] | 332 | #define MCFGPIO_PODR_FECH (0xFC0A4000) |
| 333 | #define MCFGPIO_PODR_FECL (0xFC0A4001) |
| 334 | #define MCFGPIO_PODR_SSI (0xFC0A4002) |
| 335 | #define MCFGPIO_PODR_BUSCTL (0xFC0A4003) |
| 336 | #define MCFGPIO_PODR_BE (0xFC0A4004) |
| 337 | #define MCFGPIO_PODR_CS (0xFC0A4005) |
| 338 | #define MCFGPIO_PODR_PWM (0xFC0A4006) |
| 339 | #define MCFGPIO_PODR_FECI2C (0xFC0A4007) |
| 340 | #define MCFGPIO_PODR_UART (0xFC0A4009) |
| 341 | #define MCFGPIO_PODR_QSPI (0xFC0A400A) |
| 342 | #define MCFGPIO_PODR_TIMER (0xFC0A400B) |
| 343 | #define MCFGPIO_PODR_LCDDATAH (0xFC0A400D) |
| 344 | #define MCFGPIO_PODR_LCDDATAM (0xFC0A400E) |
| 345 | #define MCFGPIO_PODR_LCDDATAL (0xFC0A400F) |
| 346 | #define MCFGPIO_PODR_LCDCTLH (0xFC0A4010) |
| 347 | #define MCFGPIO_PODR_LCDCTLL (0xFC0A4011) |
| 348 | #define MCFGPIO_PDDR_FECH (0xFC0A4014) |
| 349 | #define MCFGPIO_PDDR_FECL (0xFC0A4015) |
| 350 | #define MCFGPIO_PDDR_SSI (0xFC0A4016) |
| 351 | #define MCFGPIO_PDDR_BUSCTL (0xFC0A4017) |
| 352 | #define MCFGPIO_PDDR_BE (0xFC0A4018) |
| 353 | #define MCFGPIO_PDDR_CS (0xFC0A4019) |
| 354 | #define MCFGPIO_PDDR_PWM (0xFC0A401A) |
| 355 | #define MCFGPIO_PDDR_FECI2C (0xFC0A401B) |
| 356 | #define MCFGPIO_PDDR_UART (0xFC0A401C) |
| 357 | #define MCFGPIO_PDDR_QSPI (0xFC0A401E) |
| 358 | #define MCFGPIO_PDDR_TIMER (0xFC0A401F) |
| 359 | #define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021) |
| 360 | #define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022) |
| 361 | #define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023) |
| 362 | #define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024) |
| 363 | #define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025) |
| 364 | #define MCFGPIO_PPDSDR_FECH (0xFC0A4028) |
| 365 | #define MCFGPIO_PPDSDR_FECL (0xFC0A4029) |
| 366 | #define MCFGPIO_PPDSDR_SSI (0xFC0A402A) |
| 367 | #define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B) |
| 368 | #define MCFGPIO_PPDSDR_BE (0xFC0A402C) |
| 369 | #define MCFGPIO_PPDSDR_CS (0xFC0A402D) |
| 370 | #define MCFGPIO_PPDSDR_PWM (0xFC0A402E) |
| 371 | #define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F) |
| 372 | #define MCFGPIO_PPDSDR_UART (0xFC0A4031) |
| 373 | #define MCFGPIO_PPDSDR_QSPI (0xFC0A4032) |
| 374 | #define MCFGPIO_PPDSDR_TIMER (0xFC0A4033) |
| 375 | #define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035) |
| 376 | #define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036) |
| 377 | #define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037) |
| 378 | #define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038) |
| 379 | #define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039) |
| 380 | #define MCFGPIO_PCLRR_FECH (0xFC0A403C) |
| 381 | #define MCFGPIO_PCLRR_FECL (0xFC0A403D) |
| 382 | #define MCFGPIO_PCLRR_SSI (0xFC0A403E) |
| 383 | #define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F) |
| 384 | #define MCFGPIO_PCLRR_BE (0xFC0A4040) |
| 385 | #define MCFGPIO_PCLRR_CS (0xFC0A4041) |
| 386 | #define MCFGPIO_PCLRR_PWM (0xFC0A4042) |
| 387 | #define MCFGPIO_PCLRR_FECI2C (0xFC0A4043) |
| 388 | #define MCFGPIO_PCLRR_UART (0xFC0A4045) |
| 389 | #define MCFGPIO_PCLRR_QSPI (0xFC0A4046) |
| 390 | #define MCFGPIO_PCLRR_TIMER (0xFC0A4047) |
| 391 | #define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049) |
| 392 | #define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A) |
| 393 | #define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B) |
| 394 | #define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C) |
| 395 | #define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D) |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 396 | #define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) |
| 397 | #define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) |
| 398 | #define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) |
| 399 | #define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) |
| 400 | #define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) |
| 401 | #define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) |
| 402 | #define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) |
| 403 | #define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) |
| 404 | #define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) |
| 405 | #define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) |
| 406 | #define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) |
| 407 | #define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) |
| 408 | #define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) |
| 409 | #define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) |
| 410 | #define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) |
| 411 | #define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) |
| 412 | #define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) |
| 413 | #define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) |
| 414 | #define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) |
| 415 | #define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) |
| 416 | #define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) |
| 417 | #define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) |
| 418 | #define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) |
| 419 | #define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) |
| 420 | #define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) |
| 421 | #define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) |
| 422 | |
| 423 | /* Bit definitions and macros for MCF_GPIO_PODR_FECH */ |
| 424 | #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) |
| 425 | #define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) |
| 426 | #define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) |
| 427 | #define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) |
| 428 | #define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) |
| 429 | #define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) |
| 430 | #define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) |
| 431 | #define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) |
| 432 | |
| 433 | /* Bit definitions and macros for MCF_GPIO_PODR_FECL */ |
| 434 | #define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) |
| 435 | #define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) |
| 436 | #define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) |
| 437 | #define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) |
| 438 | #define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) |
| 439 | #define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) |
| 440 | #define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) |
| 441 | #define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) |
| 442 | |
| 443 | /* Bit definitions and macros for MCF_GPIO_PODR_SSI */ |
| 444 | #define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) |
| 445 | #define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) |
| 446 | #define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) |
| 447 | #define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) |
| 448 | #define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) |
| 449 | |
| 450 | /* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ |
| 451 | #define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01) |
| 452 | #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) |
| 453 | #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) |
| 454 | #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) |
| 455 | |
| 456 | /* Bit definitions and macros for MCF_GPIO_PODR_BE */ |
| 457 | #define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) |
| 458 | #define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) |
| 459 | #define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) |
| 460 | #define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) |
| 461 | |
| 462 | /* Bit definitions and macros for MCF_GPIO_PODR_CS */ |
| 463 | #define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) |
| 464 | #define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) |
| 465 | #define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) |
| 466 | #define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) |
| 467 | #define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) |
| 468 | |
| 469 | /* Bit definitions and macros for MCF_GPIO_PODR_PWM */ |
| 470 | #define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) |
| 471 | #define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) |
| 472 | #define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) |
| 473 | #define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) |
| 474 | |
| 475 | /* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ |
| 476 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) |
| 477 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) |
| 478 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) |
| 479 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) |
| 480 | |
| 481 | /* Bit definitions and macros for MCF_GPIO_PODR_UART */ |
| 482 | #define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) |
| 483 | #define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) |
| 484 | #define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) |
| 485 | #define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) |
| 486 | #define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) |
| 487 | #define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) |
| 488 | #define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) |
| 489 | #define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) |
| 490 | |
| 491 | /* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ |
| 492 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) |
| 493 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) |
| 494 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) |
| 495 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) |
| 496 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) |
| 497 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) |
| 498 | |
| 499 | /* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ |
| 500 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) |
| 501 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) |
| 502 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) |
| 503 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) |
| 504 | |
| 505 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ |
| 506 | #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) |
| 507 | #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) |
| 508 | |
| 509 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ |
| 510 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) |
| 511 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) |
| 512 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) |
| 513 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) |
| 514 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) |
| 515 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) |
| 516 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) |
| 517 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) |
| 518 | |
| 519 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ |
| 520 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) |
| 521 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) |
| 522 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) |
| 523 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) |
| 524 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) |
| 525 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) |
| 526 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) |
| 527 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) |
| 528 | |
| 529 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ |
| 530 | #define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) |
| 531 | |
| 532 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ |
| 533 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) |
| 534 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) |
| 535 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) |
| 536 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) |
| 537 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) |
| 538 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) |
| 539 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) |
| 540 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) |
| 541 | |
| 542 | /* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ |
| 543 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) |
| 544 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) |
| 545 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) |
| 546 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) |
| 547 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) |
| 548 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) |
| 549 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) |
| 550 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) |
| 551 | |
| 552 | /* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ |
| 553 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) |
| 554 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) |
| 555 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) |
| 556 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) |
| 557 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) |
| 558 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) |
| 559 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) |
| 560 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) |
| 561 | |
| 562 | /* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ |
| 563 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) |
| 564 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) |
| 565 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) |
| 566 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) |
| 567 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) |
| 568 | |
| 569 | /* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ |
| 570 | #define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01) |
| 571 | #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) |
| 572 | #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) |
| 573 | #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) |
| 574 | |
| 575 | /* Bit definitions and macros for MCF_GPIO_PDDR_BE */ |
| 576 | #define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) |
| 577 | #define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) |
| 578 | #define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) |
| 579 | #define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) |
| 580 | |
| 581 | /* Bit definitions and macros for MCF_GPIO_PDDR_CS */ |
| 582 | #define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) |
| 583 | #define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) |
| 584 | #define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) |
| 585 | #define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) |
| 586 | #define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) |
| 587 | |
| 588 | /* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ |
| 589 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) |
| 590 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) |
| 591 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) |
| 592 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) |
| 593 | |
| 594 | /* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ |
| 595 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) |
| 596 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) |
| 597 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) |
| 598 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) |
| 599 | |
| 600 | /* Bit definitions and macros for MCF_GPIO_PDDR_UART */ |
| 601 | #define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) |
| 602 | #define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) |
| 603 | #define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) |
| 604 | #define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) |
| 605 | #define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) |
| 606 | #define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) |
| 607 | #define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) |
| 608 | #define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) |
| 609 | |
| 610 | /* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ |
| 611 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) |
| 612 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) |
| 613 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) |
| 614 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) |
| 615 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) |
| 616 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) |
| 617 | |
| 618 | /* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ |
| 619 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) |
| 620 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) |
| 621 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) |
| 622 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) |
| 623 | |
| 624 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ |
| 625 | #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) |
| 626 | #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) |
| 627 | |
| 628 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ |
| 629 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) |
| 630 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) |
| 631 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) |
| 632 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) |
| 633 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) |
| 634 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) |
| 635 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) |
| 636 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) |
| 637 | |
| 638 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ |
| 639 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) |
| 640 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) |
| 641 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) |
| 642 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) |
| 643 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) |
| 644 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) |
| 645 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) |
| 646 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) |
| 647 | |
| 648 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ |
| 649 | #define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) |
| 650 | |
| 651 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ |
| 652 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) |
| 653 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) |
| 654 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) |
| 655 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) |
| 656 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) |
| 657 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) |
| 658 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) |
| 659 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) |
| 660 | |
| 661 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ |
| 662 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) |
| 663 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) |
| 664 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) |
| 665 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) |
| 666 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) |
| 667 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) |
| 668 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) |
| 669 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) |
| 670 | |
| 671 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ |
| 672 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) |
| 673 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) |
| 674 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) |
| 675 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) |
| 676 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) |
| 677 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) |
| 678 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) |
| 679 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) |
| 680 | |
| 681 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ |
| 682 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) |
| 683 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) |
| 684 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) |
| 685 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) |
| 686 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) |
| 687 | |
| 688 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ |
| 689 | #define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01) |
| 690 | #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) |
| 691 | #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) |
| 692 | #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) |
| 693 | |
| 694 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ |
| 695 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) |
| 696 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) |
| 697 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) |
| 698 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) |
| 699 | |
| 700 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ |
| 701 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) |
| 702 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) |
| 703 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) |
| 704 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) |
| 705 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) |
| 706 | |
| 707 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ |
| 708 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) |
| 709 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) |
| 710 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) |
| 711 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) |
| 712 | |
| 713 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ |
| 714 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) |
| 715 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) |
| 716 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) |
| 717 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) |
| 718 | |
| 719 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ |
| 720 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) |
| 721 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) |
| 722 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) |
| 723 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) |
| 724 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) |
| 725 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) |
| 726 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) |
| 727 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) |
| 728 | |
| 729 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ |
| 730 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) |
| 731 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) |
| 732 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) |
| 733 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) |
| 734 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) |
| 735 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) |
| 736 | |
| 737 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ |
| 738 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) |
| 739 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) |
| 740 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) |
| 741 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) |
| 742 | |
| 743 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ |
| 744 | #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) |
| 745 | #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) |
| 746 | |
| 747 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ |
| 748 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) |
| 749 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) |
| 750 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) |
| 751 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) |
| 752 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) |
| 753 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) |
| 754 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) |
| 755 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) |
| 756 | |
| 757 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ |
| 758 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) |
| 759 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) |
| 760 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) |
| 761 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) |
| 762 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) |
| 763 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) |
| 764 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) |
| 765 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) |
| 766 | |
| 767 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ |
| 768 | #define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) |
| 769 | |
| 770 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ |
| 771 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) |
| 772 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) |
| 773 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) |
| 774 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) |
| 775 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) |
| 776 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) |
| 777 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) |
| 778 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) |
| 779 | |
| 780 | /* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ |
| 781 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) |
| 782 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) |
| 783 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) |
| 784 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) |
| 785 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) |
| 786 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) |
| 787 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) |
| 788 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) |
| 789 | |
| 790 | /* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ |
| 791 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) |
| 792 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) |
| 793 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) |
| 794 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) |
| 795 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) |
| 796 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) |
| 797 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) |
| 798 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) |
| 799 | |
| 800 | /* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ |
| 801 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) |
| 802 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) |
| 803 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) |
| 804 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) |
| 805 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) |
| 806 | |
| 807 | /* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ |
| 808 | #define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01) |
| 809 | #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) |
| 810 | #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) |
| 811 | #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) |
| 812 | |
| 813 | /* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ |
| 814 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) |
| 815 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) |
| 816 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) |
| 817 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) |
| 818 | |
| 819 | /* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ |
| 820 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) |
| 821 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) |
| 822 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) |
| 823 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) |
| 824 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) |
| 825 | |
| 826 | /* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ |
| 827 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) |
| 828 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) |
| 829 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) |
| 830 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) |
| 831 | |
| 832 | /* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ |
| 833 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) |
| 834 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) |
| 835 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) |
| 836 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) |
| 837 | |
| 838 | /* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ |
| 839 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) |
| 840 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) |
| 841 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) |
| 842 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) |
| 843 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) |
| 844 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) |
| 845 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) |
| 846 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) |
| 847 | |
| 848 | /* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ |
| 849 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) |
| 850 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) |
| 851 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) |
| 852 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) |
| 853 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) |
| 854 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) |
| 855 | |
| 856 | /* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ |
| 857 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) |
| 858 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) |
| 859 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) |
| 860 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) |
| 861 | |
| 862 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ |
| 863 | #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) |
| 864 | #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) |
| 865 | |
| 866 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ |
| 867 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) |
| 868 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) |
| 869 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) |
| 870 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) |
| 871 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) |
| 872 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) |
| 873 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) |
| 874 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) |
| 875 | |
| 876 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ |
| 877 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) |
| 878 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) |
| 879 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) |
| 880 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) |
| 881 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) |
| 882 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) |
| 883 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) |
| 884 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) |
| 885 | |
| 886 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ |
| 887 | #define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) |
| 888 | |
| 889 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ |
| 890 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) |
| 891 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) |
| 892 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) |
| 893 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) |
| 894 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) |
| 895 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) |
| 896 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) |
| 897 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) |
| 898 | |
| 899 | /* Bit definitions and macros for MCF_GPIO_PAR_FEC */ |
| 900 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) |
| 901 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) |
| 902 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) |
| 903 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) |
| 904 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) |
| 905 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) |
| 906 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) |
| 907 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) |
| 908 | |
| 909 | /* Bit definitions and macros for MCF_GPIO_PAR_PWM */ |
| 910 | #define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) |
| 911 | #define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) |
| 912 | #define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) |
| 913 | #define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) |
| 914 | |
| 915 | /* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ |
| 916 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) |
| 917 | #define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) |
| 918 | #define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) |
| 919 | #define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) |
| 920 | #define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) |
| 921 | #define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) |
| 922 | #define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) |
| 923 | #define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) |
| 924 | #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) |
| 925 | #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) |
| 926 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) |
| 927 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) |
| 928 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) |
| 929 | |
| 930 | /* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ |
| 931 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) |
| 932 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) |
| 933 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) |
| 934 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) |
| 935 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) |
| 936 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) |
| 937 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) |
| 938 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) |
| 939 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) |
| 940 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) |
| 941 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) |
| 942 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) |
| 943 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) |
| 944 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) |
| 945 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) |
| 946 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) |
| 947 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) |
| 948 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) |
| 949 | |
| 950 | /* Bit definitions and macros for MCF_GPIO_PAR_BE */ |
| 951 | #define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) |
| 952 | #define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) |
| 953 | #define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) |
| 954 | #define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) |
| 955 | |
| 956 | /* Bit definitions and macros for MCF_GPIO_PAR_CS */ |
| 957 | #define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) |
| 958 | #define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) |
| 959 | #define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) |
| 960 | #define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) |
| 961 | #define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) |
| 962 | #define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) |
| 963 | #define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) |
| 964 | #define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) |
| 965 | |
| 966 | /* Bit definitions and macros for MCF_GPIO_PAR_SSI */ |
| 967 | #define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) |
| 968 | #define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) |
| 969 | #define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) |
| 970 | #define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) |
| 971 | #define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) |
| 972 | |
| 973 | /* Bit definitions and macros for MCF_GPIO_PAR_UART */ |
| 974 | #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) |
| 975 | #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) |
| 976 | #define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) |
| 977 | #define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) |
| 978 | #define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) |
| 979 | #define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) |
| 980 | #define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) |
| 981 | #define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) |
| 982 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) |
| 983 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) |
| 984 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) |
| 985 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) |
| 986 | #define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) |
| 987 | #define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) |
| 988 | #define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) |
| 989 | #define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) |
| 990 | #define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) |
| 991 | #define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) |
| 992 | #define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) |
| 993 | #define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) |
| 994 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) |
| 995 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) |
| 996 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) |
| 997 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) |
| 998 | |
| 999 | /* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ |
| 1000 | #define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) |
| 1001 | #define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) |
| 1002 | #define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) |
| 1003 | #define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) |
| 1004 | #define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) |
| 1005 | #define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) |
| 1006 | |
| 1007 | /* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ |
| 1008 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) |
| 1009 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) |
| 1010 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) |
| 1011 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) |
| 1012 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) |
| 1013 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) |
| 1014 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) |
| 1015 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) |
| 1016 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) |
| 1017 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) |
| 1018 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) |
| 1019 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) |
| 1020 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) |
| 1021 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) |
| 1022 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) |
| 1023 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) |
| 1024 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) |
| 1025 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) |
| 1026 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) |
| 1027 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) |
| 1028 | |
| 1029 | /* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ |
| 1030 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) |
| 1031 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) |
| 1032 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) |
| 1033 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) |
| 1034 | |
| 1035 | /* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ |
| 1036 | #define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) |
| 1037 | #define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) |
| 1038 | #define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) |
| 1039 | #define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) |
| 1040 | #define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) |
| 1041 | #define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) |
| 1042 | #define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) |
| 1043 | #define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) |
| 1044 | #define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) |
| 1045 | |
| 1046 | /* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ |
| 1047 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) |
| 1048 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) |
| 1049 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) |
| 1050 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) |
| 1051 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) |
| 1052 | |
| 1053 | /* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ |
| 1054 | #define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) |
| 1055 | #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) |
| 1056 | #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) |
| 1057 | |
| 1058 | /* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ |
| 1059 | #define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) |
| 1060 | #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) |
| 1061 | #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) |
| 1062 | |
| 1063 | /* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ |
| 1064 | #define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) |
| 1065 | |
| 1066 | /* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ |
| 1067 | #define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) |
| 1068 | |
| 1069 | /* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ |
| 1070 | #define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) |
| 1071 | |
| 1072 | /* Bit definitions and macros for MCF_GPIO_DSCR_UART */ |
| 1073 | #define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) |
| 1074 | #define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) |
| 1075 | |
| 1076 | /* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ |
| 1077 | #define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) |
| 1078 | |
| 1079 | /* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ |
| 1080 | #define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) |
| 1081 | |
| 1082 | /* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ |
| 1083 | #define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) |
| 1084 | |
| 1085 | /* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ |
| 1086 | #define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) |
| 1087 | |
| 1088 | /* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ |
| 1089 | #define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) |
| 1090 | |
| 1091 | /* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ |
| 1092 | #define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0) |
| 1093 | |
| 1094 | /* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ |
| 1095 | #define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) |
| 1096 | |
| sfking@fdwdc.com | 7846fe8 | 2009-06-19 18:11:10 -0700 | [diff] [blame] | 1097 | /* |
| 1098 | * Generic GPIO support |
| 1099 | */ |
| 1100 | #define MCFGPIO_PODR MCFGPIO_PODR_FECH |
| 1101 | #define MCFGPIO_PDDR MCFGPIO_PDDR_FECH |
| 1102 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH |
| 1103 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH |
| 1104 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH |
| 1105 | |
| 1106 | #define MCFGPIO_PIN_MAX 136 |
| 1107 | #define MCFGPIO_IRQ_MAX 8 |
| 1108 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| 1109 | |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 1110 | /********************************************************************* |
| 1111 | * |
| 1112 | * Phase Locked Loop (PLL) |
| 1113 | * |
| 1114 | *********************************************************************/ |
| 1115 | |
| 1116 | /* Register read/write macros */ |
| 1117 | #define MCF_PLL_PODR MCF_REG08(0xFC0C0000) |
| 1118 | #define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004) |
| 1119 | #define MCF_PLL_PMDR MCF_REG08(0xFC0C0008) |
| 1120 | #define MCF_PLL_PFDR MCF_REG08(0xFC0C000C) |
| 1121 | |
| 1122 | /* Bit definitions and macros for MCF_PLL_PODR */ |
| 1123 | #define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) |
| 1124 | #define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) |
| 1125 | |
| 1126 | /* Bit definitions and macros for MCF_PLL_PLLCR */ |
| 1127 | #define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) |
| 1128 | #define MCF_PLL_PLLCR_DITHEN (0x80) |
| 1129 | |
| 1130 | /* Bit definitions and macros for MCF_PLL_PMDR */ |
| 1131 | #define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) |
| 1132 | |
| 1133 | /* Bit definitions and macros for MCF_PLL_PFDR */ |
| 1134 | #define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) |
| 1135 | |
| 1136 | /********************************************************************* |
| 1137 | * |
| 1138 | * System Control Module Registers (SCM) |
| 1139 | * |
| 1140 | *********************************************************************/ |
| 1141 | |
| 1142 | /* Register read/write macros */ |
| 1143 | #define MCF_SCM_MPR MCF_REG32(0xFC000000) |
| 1144 | #define MCF_SCM_PACRA MCF_REG32(0xFC000020) |
| 1145 | #define MCF_SCM_PACRB MCF_REG32(0xFC000024) |
| 1146 | #define MCF_SCM_PACRC MCF_REG32(0xFC000028) |
| 1147 | #define MCF_SCM_PACRD MCF_REG32(0xFC00002C) |
| 1148 | #define MCF_SCM_PACRE MCF_REG32(0xFC000040) |
| 1149 | #define MCF_SCM_PACRF MCF_REG32(0xFC000044) |
| 1150 | |
| 1151 | #define MCF_SCM_BCR MCF_REG32(0xFC040024) |
| 1152 | |
| 1153 | /********************************************************************* |
| 1154 | * |
| 1155 | * SDRAM Controller (SDRAMC) |
| 1156 | * |
| 1157 | *********************************************************************/ |
| 1158 | |
| 1159 | /* Register read/write macros */ |
| 1160 | #define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000) |
| 1161 | #define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004) |
| 1162 | #define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008) |
| 1163 | #define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C) |
| 1164 | #define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080) |
| 1165 | #define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100) |
| 1166 | #define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110) |
| 1167 | #define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114) |
| 1168 | #define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118) |
| 1169 | #define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C) |
| 1170 | #define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004)) |
| 1171 | |
| 1172 | /* Bit definitions and macros for MCF_SDRAMC_SDMR */ |
| 1173 | #define MCF_SDRAMC_SDMR_CMD (0x00010000) |
| 1174 | #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) |
| 1175 | #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) |
| 1176 | #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) |
| 1177 | #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) |
| 1178 | |
| 1179 | /* Bit definitions and macros for MCF_SDRAMC_SDCR */ |
| 1180 | #define MCF_SDRAMC_SDCR_IPALL (0x00000002) |
| 1181 | #define MCF_SDRAMC_SDCR_IREF (0x00000004) |
| 1182 | #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) |
| 1183 | #define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) |
| 1184 | #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) |
| 1185 | #define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) |
| 1186 | #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) |
| 1187 | #define MCF_SDRAMC_SDCR_REF (0x10000000) |
| 1188 | #define MCF_SDRAMC_SDCR_DDR (0x20000000) |
| 1189 | #define MCF_SDRAMC_SDCR_CKE (0x40000000) |
| 1190 | #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) |
| 1191 | #define MCF_SDRAMC_SDCR_PS_16 (0x00002000) |
| 1192 | #define MCF_SDRAMC_SDCR_PS_32 (0x00000000) |
| 1193 | |
| 1194 | /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ |
| 1195 | #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) |
| 1196 | #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) |
| 1197 | #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) |
| 1198 | #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) |
| 1199 | #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) |
| 1200 | #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) |
| 1201 | #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) |
| 1202 | |
| 1203 | /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ |
| 1204 | #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) |
| 1205 | #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) |
| 1206 | #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) |
| 1207 | #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) |
| 1208 | |
| 1209 | /* Device Errata - LIMP mode work around */ |
| 1210 | #define MCF_SDRAMC_REFRESH (0x40000000) |
| 1211 | |
| 1212 | /* Bit definitions and macros for MCF_SDRAMC_SDDS */ |
| 1213 | #define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) |
| 1214 | #define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) |
| 1215 | #define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) |
| 1216 | #define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) |
| 1217 | #define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) |
| 1218 | |
| 1219 | /* Bit definitions and macros for MCF_SDRAMC_SDCS */ |
| 1220 | #define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) |
| 1221 | #define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) |
| 1222 | #define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) |
| 1223 | #define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) |
| 1224 | #define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) |
| 1225 | #define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) |
| 1226 | #define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) |
| 1227 | #define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) |
| 1228 | #define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) |
| 1229 | #define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) |
| 1230 | #define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) |
| 1231 | #define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) |
| 1232 | #define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) |
| 1233 | #define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) |
| 1234 | #define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) |
| 1235 | #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) |
| 1236 | #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) |
| 1237 | |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 1238 | /* |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 1239 | * Edge Port Module (EPORT) |
| Greg Ungerer | 23bcdac | 2012-09-17 15:04:42 +1000 | [diff] [blame^] | 1240 | */ |
| sfking@fdwdc.com | 7846fe8 | 2009-06-19 18:11:10 -0700 | [diff] [blame] | 1241 | #define MCFEPORT_EPPAR (0xFC094000) |
| 1242 | #define MCFEPORT_EPDDR (0xFC094002) |
| 1243 | #define MCFEPORT_EPIER (0xFC094003) |
| 1244 | #define MCFEPORT_EPDR (0xFC094004) |
| 1245 | #define MCFEPORT_EPPDR (0xFC094005) |
| 1246 | #define MCFEPORT_EPFR (0xFC094006) |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 1247 | |
| Greg Ungerer | 7c99df6 | 2006-06-26 10:33:10 +1000 | [diff] [blame] | 1248 | /********************************************************************/ |
| 1249 | #endif /* m532xsim_h */ |