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gerrit-public.fairphone.software / kernel / msm-5.4 / e6afbe59710f65d92d00de1f3adb5514ef634110 / . / arch / mips / mm / cache.c
blob: 1d95cdb77bede13d834423f5417e188b5af34e45 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2003 by Ralf Baechle
7 */
8#include <linux/config.h>
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14
15#include <asm/cacheflush.h>
16#include <asm/processor.h>
17#include <asm/cpu.h>
18#include <asm/cpu-features.h>
19
20/* Cache operations. */
21void (*flush_cache_all)(void);
22void (*__flush_cache_all)(void);
23void (*flush_cache_mm)(struct mm_struct *mm);
24void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
25 unsigned long end);
26void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
27void (*flush_icache_range)(unsigned long start, unsigned long end);
28void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
29
30/* MIPS specific cache operations */
31void (*flush_cache_sigtramp)(unsigned long addr);
32void (*flush_data_cache_page)(unsigned long addr);
33void (*flush_icache_all)(void);
34
35#ifdef CONFIG_DMA_NONCOHERENT
36
37/* DMA cache operations. */
38void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
39void (*_dma_cache_wback)(unsigned long start, unsigned long size);
40void (*_dma_cache_inv)(unsigned long start, unsigned long size);
41
42EXPORT_SYMBOL(_dma_cache_wback_inv);
43EXPORT_SYMBOL(_dma_cache_wback);
44EXPORT_SYMBOL(_dma_cache_inv);
45
46#endif /* CONFIG_DMA_NONCOHERENT */
47
48/*
49 * We could optimize the case where the cache argument is not BCACHE but
50 * that seems very atypical use ...
51 */
52asmlinkage int sys_cacheflush(unsigned long addr, unsigned long int bytes,
53 unsigned int cache)
54{
55 if (!access_ok(VERIFY_WRITE, (void *) addr, bytes))
56 return -EFAULT;
57
58 flush_icache_range(addr, addr + bytes);
59
60 return 0;
61}
62
63void __flush_dcache_page(struct page *page)
64{
65 struct address_space *mapping = page_mapping(page);
66 unsigned long addr;
67
68 if (mapping && !mapping_mapped(mapping)) {
69 SetPageDcacheDirty(page);
70 return;
71 }
72
73 /*
74 * We could delay the flush for the !page_mapping case too. But that
75 * case is for exec env/arg pages and those are %99 certainly going to
76 * get faulted into the tlb (and thus flushed) anyways.
77 */
78 addr = (unsigned long) page_address(page);
79 flush_data_cache_page(addr);
80}
81
82EXPORT_SYMBOL(__flush_dcache_page);
83
84void __update_cache(struct vm_area_struct *vma, unsigned long address,
85 pte_t pte)
86{
87 struct page *page;
88 unsigned long pfn, addr;
89
90 pfn = pte_pfn(pte);
91 if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) &&
92 Page_dcache_dirty(page)) {
93 if (pages_do_alias((unsigned long)page_address(page),
94 address & PAGE_MASK)) {
95 addr = (unsigned long) page_address(page);
96 flush_data_cache_page(addr);
97 }
98
99 ClearPageDcacheDirty(page);
100 }
101}
102
103extern void ld_mmu_r23000(void);
104extern void ld_mmu_r4xx0(void);
105extern void ld_mmu_tx39(void);
106extern void ld_mmu_r6000(void);
107extern void ld_mmu_tfp(void);
108extern void ld_mmu_andes(void);
109extern void ld_mmu_sb1(void);
110
111void __init cpu_cache_init(void)
112{
113 if (cpu_has_4ktlb) {
114#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
115 defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
116 defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
117 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \
118 defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \
119 defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
120 ld_mmu_r4xx0();
121#endif
122 } else switch (current_cpu_data.cputype) {
123#ifdef CONFIG_CPU_R3000
124 case CPU_R2000:
125 case CPU_R3000:
126 case CPU_R3000A:
127 case CPU_R3081E:
128 ld_mmu_r23000();
129 break;
130#endif
131#ifdef CONFIG_CPU_TX39XX
132 case CPU_TX3912:
133 case CPU_TX3922:
134 case CPU_TX3927:
135 ld_mmu_tx39();
136 break;
137#endif
138#ifdef CONFIG_CPU_R10000
139 case CPU_R10000:
140 case CPU_R12000:
141 ld_mmu_r4xx0();
142 break;
143#endif
144#ifdef CONFIG_CPU_SB1
145 case CPU_SB1:
146 ld_mmu_sb1();
147 break;
148#endif
149
150 case CPU_R8000:
151 panic("R8000 is unsupported");
152 break;
153
154 default:
155 panic("Yeee, unsupported cache architecture.");
156 }
157}