blob: 4332da48b1b302763faa0138b89d09995667b653 [file] [log] [blame]
Maxime Ripard9026e0d2015-10-29 09:36:23 +01001/*
2 * Copyright (C) 2016 Free Electrons
3 * Copyright (C) 2016 NextThing Co
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/regmap.h>
15
16#include "sun4i_tcon.h"
Baoyou Xie0c3ff442016-09-08 18:59:22 +080017#include "sun4i_dotclock.h"
Maxime Ripard9026e0d2015-10-29 09:36:23 +010018
19struct sun4i_dclk {
20 struct clk_hw hw;
21 struct regmap *regmap;
22};
23
24static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
25{
26 return container_of(hw, struct sun4i_dclk, hw);
27}
28
29static void sun4i_dclk_disable(struct clk_hw *hw)
30{
31 struct sun4i_dclk *dclk = hw_to_dclk(hw);
32
33 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
34 BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
35}
36
37static int sun4i_dclk_enable(struct clk_hw *hw)
38{
39 struct sun4i_dclk *dclk = hw_to_dclk(hw);
40
41 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
42 BIT(SUN4I_TCON0_DCLK_GATE_BIT),
43 BIT(SUN4I_TCON0_DCLK_GATE_BIT));
44}
45
46static int sun4i_dclk_is_enabled(struct clk_hw *hw)
47{
48 struct sun4i_dclk *dclk = hw_to_dclk(hw);
49 u32 val;
50
51 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
52
53 return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
54}
55
56static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
57 unsigned long parent_rate)
58{
59 struct sun4i_dclk *dclk = hw_to_dclk(hw);
60 u32 val;
61
62 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
63
64 val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
65 val &= SUN4I_TCON0_DCLK_DIV_WIDTH;
66
67 if (!val)
68 val = 1;
69
70 return parent_rate / val;
71}
72
73static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
74 unsigned long *parent_rate)
75{
Maxime Ripard4731a722016-04-02 12:30:11 +020076 unsigned long best_parent = 0;
77 u8 best_div = 1;
78 int i;
79
80 for (i = 6; i < 127; i++) {
81 unsigned long ideal = rate * i;
82 unsigned long rounded;
83
84 rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
85 ideal);
86
87 if (rounded == ideal) {
88 best_parent = rounded;
89 best_div = i;
90 goto out;
91 }
92
93 if ((rounded < ideal) && (rounded > best_parent)) {
94 best_parent = rounded;
95 best_div = i;
96 }
97 }
98
99out:
100 *parent_rate = best_parent;
101
102 return best_parent / best_div;
Maxime Ripard9026e0d2015-10-29 09:36:23 +0100103}
104
105static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long parent_rate)
107{
108 struct sun4i_dclk *dclk = hw_to_dclk(hw);
Maxime Ripard4731a722016-04-02 12:30:11 +0200109 u8 div = parent_rate / rate;
Maxime Ripard9026e0d2015-10-29 09:36:23 +0100110
111 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
112 GENMASK(6, 0), div);
113}
114
115static int sun4i_dclk_get_phase(struct clk_hw *hw)
116{
117 struct sun4i_dclk *dclk = hw_to_dclk(hw);
118 u32 val;
119
120 regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
121
122 val >>= 28;
123 val &= 3;
124
125 return val * 120;
126}
127
128static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
129{
130 struct sun4i_dclk *dclk = hw_to_dclk(hw);
131
132 regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
133 GENMASK(29, 28),
134 degrees / 120);
135
136 return 0;
137}
138
139static const struct clk_ops sun4i_dclk_ops = {
140 .disable = sun4i_dclk_disable,
141 .enable = sun4i_dclk_enable,
142 .is_enabled = sun4i_dclk_is_enabled,
143
144 .recalc_rate = sun4i_dclk_recalc_rate,
145 .round_rate = sun4i_dclk_round_rate,
146 .set_rate = sun4i_dclk_set_rate,
147
148 .get_phase = sun4i_dclk_get_phase,
149 .set_phase = sun4i_dclk_set_phase,
150};
151
152int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
153{
154 const char *clk_name, *parent_name;
155 struct clk_init_data init;
156 struct sun4i_dclk *dclk;
Arnd Bergmann9fa25682016-05-05 22:10:52 +0200157 int ret;
Maxime Ripard9026e0d2015-10-29 09:36:23 +0100158
159 parent_name = __clk_get_name(tcon->sclk0);
Arnd Bergmann9fa25682016-05-05 22:10:52 +0200160 ret = of_property_read_string_index(dev->of_node,
161 "clock-output-names", 0,
162 &clk_name);
163 if (ret)
164 return ret;
Maxime Ripard9026e0d2015-10-29 09:36:23 +0100165
166 dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
167 if (!dclk)
168 return -ENOMEM;
169
170 init.name = clk_name;
171 init.ops = &sun4i_dclk_ops;
172 init.parent_names = &parent_name;
173 init.num_parents = 1;
Maxime Ripard4731a722016-04-02 12:30:11 +0200174 init.flags = CLK_SET_RATE_PARENT;
Maxime Ripard9026e0d2015-10-29 09:36:23 +0100175
176 dclk->regmap = tcon->regs;
177 dclk->hw.init = &init;
178
179 tcon->dclk = clk_register(dev, &dclk->hw);
180 if (IS_ERR(tcon->dclk))
181 return PTR_ERR(tcon->dclk);
182
183 return 0;
184}
185EXPORT_SYMBOL(sun4i_dclk_create);
186
187int sun4i_dclk_free(struct sun4i_tcon *tcon)
188{
189 clk_unregister(tcon->dclk);
190 return 0;
191}
192EXPORT_SYMBOL(sun4i_dclk_free);