blob: aaf8d28b5d008969786ee60522d0d2f2a2fae126 [file] [log] [blame]
H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_IRQ_VECTORS_H
2#define _ASM_X86_IRQ_VECTORS_H
Thomas Gleixner9b7dc562008-05-02 20:10:09 +02003
Shaohua Li60f6e652011-01-17 10:52:02 +08004#include <linux/threads.h>
Ingo Molnar9fc2e792009-01-31 02:48:17 +01005/*
6 * Linux IRQ vector layout.
7 *
8 * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
9 * be defined by Linux. They are used as a jump table by the CPU when a
10 * given vector is triggered - by a CPU-external, CPU-internal or
11 * software-triggered event.
12 *
13 * Linux sets the kernel code address each entry jumps to early during
14 * bootup, and never changes them. This is the general layout of the
15 * IDT entries:
16 *
17 * Vectors 0 ... 31 : system traps and exceptions - hardcoded events
18 * Vectors 32 ... 127 : device interrupts
19 * Vector 128 : legacy int80 syscall interface
Andy Lutomirski5cec93c2011-06-05 13:50:24 -040020 * Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts
Shaohua Li70e4a362011-01-17 10:52:07 +080021 * Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts
Ingo Molnar9fc2e792009-01-31 02:48:17 +010022 *
23 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
24 *
25 * This file enumerates the exact layout of them:
26 */
27
28#define NMI_VECTOR 0x02
Andi Kleen8fa8dd92009-05-27 21:56:58 +020029#define MCE_VECTOR 0x12
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020030
31/*
Suresh Siddha6579b472010-01-13 16:19:11 -080032 * IDT vectors usable for external interrupt sources start at 0x20.
33 * (0x80 is the syscall vector, 0x30-0x3f are for ISA)
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020034 */
Suresh Siddha6579b472010-01-13 16:19:11 -080035#define FIRST_EXTERNAL_VECTOR 0x20
36/*
37 * We start allocating at 0x21 to spread out vectors evenly between
38 * priority levels. (0x80 is the syscall vector)
39 */
40#define VECTOR_OFFSET_START 1
41
42/*
43 * Reserve the lowest usable vector (and hence lowest priority) 0x20 for
44 * triggering cleanup after irq migration. 0x21-0x2f will still be used
45 * for device interrupts.
46 */
47#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020048
H. Peter Anvin99d113b2010-01-04 16:16:06 -080049#define IA32_SYSCALL_VECTOR 0x80
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020050
51/*
Suresh Siddha6579b472010-01-13 16:19:11 -080052 * Vectors 0x30-0x3f are used for ISA interrupts.
H. Peter Anvin99d113b2010-01-04 16:16:06 -080053 * round up to the next 16-vector boundary
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020054 */
Brian Gerst8b455e62015-05-09 11:36:53 -040055#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020056
57/*
58 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
59 *
60 * some of the following vectors are 'rare', they are merged
61 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
62 * TLB, reschedule and local APIC vectors are performance-critical.
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020063 */
Ingo Molnar5da690d2009-01-31 02:10:03 +010064
65#define SPURIOUS_APIC_VECTOR 0xff
Ingo Molnar647ad942009-01-31 02:06:50 +010066/*
67 * Sanity check
68 */
69#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
70# error SPURIOUS_APIC_VECTOR definition error
71#endif
72
Ingo Molnar5da690d2009-01-31 02:10:03 +010073#define ERROR_APIC_VECTOR 0xfe
74#define RESCHEDULE_VECTOR 0xfd
75#define CALL_FUNCTION_VECTOR 0xfc
76#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
77#define THERMAL_APIC_VECTOR 0xfa
Andi Kleen7856f6c2009-04-28 23:32:56 +020078#define THRESHOLD_APIC_VECTOR 0xf9
Andi Kleen4ef702c2009-05-27 21:56:52 +020079#define REBOOT_VECTOR 0xf8
Thomas Gleixner9b7dc562008-05-02 20:10:09 +020080
Shaohua Li60f6e652011-01-17 10:52:02 +080081/*
82 * Generic system vector for platform specific use
83 */
84#define X86_PLATFORM_IPI_VECTOR 0xf7
85
86/*
87 * IRQ work vector:
88 */
89#define IRQ_WORK_VECTOR 0xf6
90
91#define UV_BAU_MESSAGE 0xf5
Aravind Gopalakrishnan24fd78a2015-05-06 06:58:56 -050092#define DEFERRED_ERROR_VECTOR 0xf4
Shaohua Li60f6e652011-01-17 10:52:02 +080093
K. Y. Srinivasanbc2b0332013-02-03 17:22:39 -080094/* Vector on which hypervisor callbacks will be delivered */
95#define HYPERVISOR_CALLBACK_VECTOR 0xf3
Ingo Molnar5da690d2009-01-31 02:10:03 +010096
Aravind Gopalakrishnan5c0d7282015-05-06 06:58:57 -050097/* Vector for KVM to deliver posted interrupt IPI */
98#ifdef CONFIG_HAVE_KVM
99#define POSTED_INTR_VECTOR 0xf2
Wincy Van210f84b2017-04-28 13:13:58 +0800100#define POSTED_INTR_WAKEUP_VECTOR 0xf1
101#define POSTED_INTR_NESTED_VECTOR 0xf0
Aravind Gopalakrishnan5c0d7282015-05-06 06:58:57 -0500102#endif
103
Thomas Gleixner9b7dc562008-05-02 20:10:09 +0200104/*
105 * Local APIC timer IRQ vector is on a different priority level,
106 * to work around the 'lost local interrupt if more than 2 IRQ
107 * sources per level' errata.
108 */
Ingo Molnar9fc2e792009-01-31 02:48:17 +0100109#define LOCAL_TIMER_VECTOR 0xef
Thomas Gleixner9b7dc562008-05-02 20:10:09 +0200110
Ingo Molnar9fc2e792009-01-31 02:48:17 +0100111#define NR_VECTORS 256
Thomas Gleixner9b7dc562008-05-02 20:10:09 +0200112
Jan Beulich2414e022014-11-03 08:39:43 +0000113#ifdef CONFIG_X86_LOCAL_APIC
114#define FIRST_SYSTEM_VECTOR LOCAL_TIMER_VECTOR
115#else
116#define FIRST_SYSTEM_VECTOR NR_VECTORS
117#endif
118
Ingo Molnar9fc2e792009-01-31 02:48:17 +0100119#define FPU_IRQ 13
Thomas Gleixner9b7dc562008-05-02 20:10:09 +0200120
Ingo Molnar009eb3f2009-01-31 02:56:44 +0100121/*
122 * Size the maximum number of interrupts.
123 *
124 * If the irq_desc[] array has a sparse layout, we can size things
125 * generously - it scales up linearly with the maximum number of CPUs,
126 * and the maximum number of IO-APICs, whichever is higher.
127 *
128 * In other cases we size more conservatively, to not create too large
129 * static arrays.
130 */
131
Jiang Liu4399b142015-04-14 10:30:04 +0800132#define NR_IRQS_LEGACY 16
Yinghai Lu99d093d2008-12-05 18:58:32 -0800133
Jiang Liu4399b142015-04-14 10:30:04 +0800134#define CPU_VECTOR_LIMIT (64 * NR_CPUS)
135#define IO_APIC_VECTOR_LIMIT (32 * MAX_IO_APICS)
Ingo Molnar009eb3f2009-01-31 02:56:44 +0100136
Jiang Liu4399b142015-04-14 10:30:04 +0800137#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI)
138#define NR_IRQS \
Ingo Molnar009eb3f2009-01-31 02:56:44 +0100139 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
140 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
141 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
Jiang Liu4399b142015-04-14 10:30:04 +0800142#elif defined(CONFIG_X86_IO_APIC)
143#define NR_IRQS (NR_VECTORS + IO_APIC_VECTOR_LIMIT)
144#elif defined(CONFIG_PCI_MSI)
145#define NR_IRQS (NR_VECTORS + CPU_VECTOR_LIMIT)
146#else
147#define NR_IRQS NR_IRQS_LEGACY
Yinghai Lu1b489762008-11-04 14:10:13 -0800148#endif
Thomas Gleixner9b7dc562008-05-02 20:10:09 +0200149
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700150#endif /* _ASM_X86_IRQ_VECTORS_H */