blob: 4db7987ec225f4d345efbb3249f0005897f95b2e [file] [log] [blame]
Jamie Iles7d4008e2011-08-26 19:04:50 +01001/*
2 * Synopsys DesignWare 8250 driver.
3 *
4 * Copyright 2011 Picochip, Jamie Iles.
Heikki Krogerus6a7320c2013-01-10 11:25:10 +02005 * Copyright 2013 Intel Corporation
Jamie Iles7d4008e2011-08-26 19:04:50 +01006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
15 */
16#include <linux/device.h>
Jamie Iles7d4008e2011-08-26 19:04:50 +010017#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/serial_8250.h>
20#include <linux/serial_core.h>
21#include <linux/serial_reg.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_platform.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
Heikki Krogerus6a7320c2013-01-10 11:25:10 +020027#include <linux/acpi.h>
Emilio Lópeze302cd92013-03-29 00:15:49 +010028#include <linux/clk.h>
Chen-Yu Tsai7fe090b2014-07-23 23:33:06 +080029#include <linux/reset.h>
Heikki Krogerusffc3ae62013-04-10 16:58:28 +030030#include <linux/pm_runtime.h>
Jamie Iles7d4008e2011-08-26 19:04:50 +010031
David Daneyd5f1af72013-06-19 20:37:27 +000032#include <asm/byteorder.h>
33
Heikki Krogerus7277b2a2013-01-10 11:25:12 +020034#include "8250.h"
35
Heikki Krogerus30046df2013-01-10 11:25:09 +020036/* Offsets for the DesignWare specific registers */
37#define DW_UART_USR 0x1f /* UART Status Register */
38#define DW_UART_CPR 0xf4 /* Component Parameter Register */
39#define DW_UART_UCV 0xf8 /* UART Component Version */
40
41/* Component Parameter Register bits */
42#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
43#define DW_UART_CPR_AFCE_MODE (1 << 4)
44#define DW_UART_CPR_THRE_MODE (1 << 5)
45#define DW_UART_CPR_SIR_MODE (1 << 6)
46#define DW_UART_CPR_SIR_LP_MODE (1 << 7)
47#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
48#define DW_UART_CPR_FIFO_ACCESS (1 << 9)
49#define DW_UART_CPR_FIFO_STAT (1 << 10)
50#define DW_UART_CPR_SHADOW (1 << 11)
51#define DW_UART_CPR_ENCODED_PARMS (1 << 12)
52#define DW_UART_CPR_DMA_EXTRA (1 << 13)
53#define DW_UART_CPR_FIFO_MODE (0xff << 16)
54/* Helper for fifo size calculation */
55#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
56
57
Jamie Iles7d4008e2011-08-26 19:04:50 +010058struct dw8250_data {
Heikki Krogerusfe95855532013-09-05 17:34:53 +030059 u8 usr_reg;
Heikki Krogerusfe95855532013-09-05 17:34:53 +030060 int last_mcr;
61 int line;
62 struct clk *clk;
Heiko Stübner7d78cbe2014-06-16 15:25:17 +020063 struct clk *pclk;
Chen-Yu Tsai7fe090b2014-07-23 23:33:06 +080064 struct reset_control *rst;
Heikki Krogerusfe95855532013-09-05 17:34:53 +030065 struct uart_8250_dma dma;
Jamie Iles7d4008e2011-08-26 19:04:50 +010066};
67
Loic Poulainc439c332014-04-24 11:46:14 +020068#define BYT_PRV_CLK 0x800
69#define BYT_PRV_CLK_EN (1 << 0)
70#define BYT_PRV_CLK_M_VAL_SHIFT 1
71#define BYT_PRV_CLK_N_VAL_SHIFT 16
72#define BYT_PRV_CLK_UPDATE (1 << 31)
73
Tim Kryger33acbb82013-08-16 13:50:15 -070074static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
75{
76 struct dw8250_data *d = p->private_data;
77
78 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
79 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
80 value |= UART_MSR_CTS;
81 value &= ~UART_MSR_DCTS;
82 }
83
84 return value;
85}
86
Tim Krygerc49436b2013-10-01 10:18:08 -070087static void dw8250_force_idle(struct uart_port *p)
88{
Andy Shevchenkob1261c82014-07-14 14:26:14 +030089 struct uart_8250_port *up = up_to_u8250p(p);
90
91 serial8250_clear_and_reinit_fifos(up);
Tim Krygerc49436b2013-10-01 10:18:08 -070092 (void)p->serial_in(p, UART_RX);
93}
94
Jamie Iles7d4008e2011-08-26 19:04:50 +010095static void dw8250_serial_out(struct uart_port *p, int offset, int value)
96{
97 struct dw8250_data *d = p->private_data;
98
Tim Kryger33acbb82013-08-16 13:50:15 -070099 if (offset == UART_MCR)
100 d->last_mcr = value;
101
102 writeb(value, p->membase + (offset << p->regshift));
Tim Krygerc49436b2013-10-01 10:18:08 -0700103
104 /* Make sure LCR write wasn't ignored */
105 if (offset == UART_LCR) {
106 int tries = 1000;
107 while (tries--) {
James Hogan6979f8d2013-12-10 22:28:04 +0000108 unsigned int lcr = p->serial_in(p, UART_LCR);
109 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
Tim Krygerc49436b2013-10-01 10:18:08 -0700110 return;
111 dw8250_force_idle(p);
112 writeb(value, p->membase + (UART_LCR << p->regshift));
113 }
114 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
115 }
Jamie Iles7d4008e2011-08-26 19:04:50 +0100116}
117
118static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
119{
Tim Kryger33acbb82013-08-16 13:50:15 -0700120 unsigned int value = readb(p->membase + (offset << p->regshift));
Jamie Iles7d4008e2011-08-26 19:04:50 +0100121
Tim Kryger33acbb82013-08-16 13:50:15 -0700122 return dw8250_modify_msr(p, offset, value);
Jamie Iles7d4008e2011-08-26 19:04:50 +0100123}
124
David Daneyd5f1af72013-06-19 20:37:27 +0000125/* Read Back (rb) version to ensure register access ording. */
126static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
127{
128 dw8250_serial_out(p, offset, value);
129 dw8250_serial_in(p, UART_LCR);
130}
131
Jamie Iles7d4008e2011-08-26 19:04:50 +0100132static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
133{
134 struct dw8250_data *d = p->private_data;
135
Tim Kryger33acbb82013-08-16 13:50:15 -0700136 if (offset == UART_MCR)
137 d->last_mcr = value;
138
139 writel(value, p->membase + (offset << p->regshift));
Tim Krygerc49436b2013-10-01 10:18:08 -0700140
141 /* Make sure LCR write wasn't ignored */
142 if (offset == UART_LCR) {
143 int tries = 1000;
144 while (tries--) {
James Hogan6979f8d2013-12-10 22:28:04 +0000145 unsigned int lcr = p->serial_in(p, UART_LCR);
146 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
Tim Krygerc49436b2013-10-01 10:18:08 -0700147 return;
148 dw8250_force_idle(p);
149 writel(value, p->membase + (UART_LCR << p->regshift));
150 }
151 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
152 }
Jamie Iles7d4008e2011-08-26 19:04:50 +0100153}
154
155static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
156{
Tim Kryger33acbb82013-08-16 13:50:15 -0700157 unsigned int value = readl(p->membase + (offset << p->regshift));
Jamie Iles7d4008e2011-08-26 19:04:50 +0100158
Tim Kryger33acbb82013-08-16 13:50:15 -0700159 return dw8250_modify_msr(p, offset, value);
Jamie Iles7d4008e2011-08-26 19:04:50 +0100160}
161
Jamie Iles7d4008e2011-08-26 19:04:50 +0100162static int dw8250_handle_irq(struct uart_port *p)
163{
164 struct dw8250_data *d = p->private_data;
165 unsigned int iir = p->serial_in(p, UART_IIR);
166
167 if (serial8250_handle_irq(p, iir)) {
168 return 1;
169 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
Tim Krygerc49436b2013-10-01 10:18:08 -0700170 /* Clear the USR */
David Daneyd5f1af72013-06-19 20:37:27 +0000171 (void)p->serial_in(p, d->usr_reg);
Jamie Iles7d4008e2011-08-26 19:04:50 +0100172
173 return 1;
174 }
175
176 return 0;
177}
178
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300179static void
180dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
181{
182 if (!state)
183 pm_runtime_get_sync(port->dev);
184
185 serial8250_do_pm(port, state, old);
186
187 if (state)
188 pm_runtime_put_sync_suspend(port->dev);
189}
190
Heikki Krogerus4e26b132014-06-05 16:51:40 +0300191static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
192 struct ktermios *old)
193{
194 unsigned int baud = tty_termios_baud_rate(termios);
195 struct dw8250_data *d = p->private_data;
196 unsigned int rate;
197 int ret;
198
199 if (IS_ERR(d->clk) || !old)
200 goto out;
201
202 /* Not requesting clock rates below 1.8432Mhz */
203 if (baud < 115200)
204 baud = 115200;
205
206 clk_disable_unprepare(d->clk);
207 rate = clk_round_rate(d->clk, baud * 16);
208 ret = clk_set_rate(d->clk, rate);
209 clk_prepare_enable(d->clk);
210
211 if (!ret)
212 p->uartclk = rate;
213out:
214 serial8250_do_set_termios(p, termios, old);
215}
216
Heikki Krogerus7fb8c562013-09-05 17:34:54 +0300217static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
218{
219 struct dw8250_data *data = param;
220
221 return chan->chan_id == data->dma.tx_chan_id ||
222 chan->chan_id == data->dma.rx_chan_id;
223}
224
Heikki Krogerus30046df2013-01-10 11:25:09 +0200225static void dw8250_setup_port(struct uart_8250_port *up)
226{
227 struct uart_port *p = &up->port;
228 u32 reg = readl(p->membase + DW_UART_UCV);
229
230 /*
231 * If the Component Version Register returns zero, we know that
232 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
233 */
234 if (!reg)
235 return;
236
237 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
238 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
239
240 reg = readl(p->membase + DW_UART_CPR);
241 if (!reg)
242 return;
243
244 /* Select the type based on fifo */
245 if (reg & DW_UART_CPR_FIFO_MODE) {
246 p->type = PORT_16550A;
247 p->flags |= UPF_FIXED_TYPE;
248 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
249 up->tx_loadsz = p->fifosize;
Heikki Krogerus2920adb2013-04-10 16:58:31 +0300250 up->capabilities = UART_CAP_FIFO;
Heikki Krogerus30046df2013-01-10 11:25:09 +0200251 }
Heikki Krogerus2920adb2013-04-10 16:58:31 +0300252
253 if (reg & DW_UART_CPR_AFCE_MODE)
254 up->capabilities |= UART_CAP_AFE;
Heikki Krogerus30046df2013-01-10 11:25:09 +0200255}
256
David Daneyd5f1af72013-06-19 20:37:27 +0000257static int dw8250_probe_of(struct uart_port *p,
258 struct dw8250_data *data)
259{
260 struct device_node *np = p->dev->of_node;
Andy Shevchenkob1261c82014-07-14 14:26:14 +0300261 struct uart_8250_port *up = up_to_u8250p(p);
David Daneyd5f1af72013-06-19 20:37:27 +0000262 u32 val;
263 bool has_ucv = true;
264
265 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
266#ifdef __BIG_ENDIAN
267 /*
268 * Low order bits of these 64-bit registers, when
269 * accessed as a byte, are 7 bytes further down in the
270 * address space in big endian mode.
271 */
272 p->membase += 7;
273#endif
274 p->serial_out = dw8250_serial_out_rb;
Andy Shevchenkod8782c72014-06-06 15:24:10 +0300275 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
David Daneyd5f1af72013-06-19 20:37:27 +0000276 p->type = PORT_OCTEON;
277 data->usr_reg = 0x27;
278 has_ucv = false;
279 } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
280 switch (val) {
281 case 1:
282 break;
283 case 4:
284 p->iotype = UPIO_MEM32;
285 p->serial_in = dw8250_serial_in32;
286 p->serial_out = dw8250_serial_out32;
287 break;
288 default:
289 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
290 return -EINVAL;
291 }
292 }
293 if (has_ucv)
Andy Shevchenkob1261c82014-07-14 14:26:14 +0300294 dw8250_setup_port(up);
David Daneyd5f1af72013-06-19 20:37:27 +0000295
296 if (!of_property_read_u32(np, "reg-shift", &val))
297 p->regshift = val;
298
299 /* clock got configured through clk api, all done */
300 if (p->uartclk)
301 return 0;
302
303 /* try to find out clock frequency from DT as fallback */
304 if (of_property_read_u32(np, "clock-frequency", &val)) {
305 dev_err(p->dev, "clk or clock-frequency not defined\n");
306 return -EINVAL;
307 }
308 p->uartclk = val;
309
310 return 0;
311}
312
Heikki Krogerusfe95855532013-09-05 17:34:53 +0300313static int dw8250_probe_acpi(struct uart_8250_port *up,
314 struct dw8250_data *data)
David Daneyd5f1af72013-06-19 20:37:27 +0000315{
David Daneyd5f1af72013-06-19 20:37:27 +0000316 struct uart_port *p = &up->port;
317
318 dw8250_setup_port(up);
319
David Daneyd5f1af72013-06-19 20:37:27 +0000320 p->iotype = UPIO_MEM32;
321 p->serial_in = dw8250_serial_in32;
322 p->serial_out = dw8250_serial_out32;
323 p->regshift = 2;
324
Heikki Krogerusfe95855532013-09-05 17:34:53 +0300325 up->dma = &data->dma;
David Daneyd5f1af72013-06-19 20:37:27 +0000326
327 up->dma->rxconf.src_maxburst = p->fifosize / 4;
328 up->dma->txconf.dst_maxburst = p->fifosize / 4;
329
Heikki Krogerus4e26b132014-06-05 16:51:40 +0300330 up->port.set_termios = dw8250_set_termios;
Loic Poulainc439c332014-04-24 11:46:14 +0200331
David Daneyd5f1af72013-06-19 20:37:27 +0000332 return 0;
333}
David Daneyd5f1af72013-06-19 20:37:27 +0000334
Bill Pemberton9671f092012-11-19 13:21:50 -0500335static int dw8250_probe(struct platform_device *pdev)
Jamie Iles7d4008e2011-08-26 19:04:50 +0100336{
Alan Cox2655a2c2012-07-12 12:59:50 +0100337 struct uart_8250_port uart = {};
Jamie Iles7d4008e2011-08-26 19:04:50 +0100338 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
Jamie Iles7d4008e2011-08-26 19:04:50 +0100340 struct dw8250_data *data;
Heikki Krogerusa7260c82013-01-10 11:25:08 +0200341 int err;
Jamie Iles7d4008e2011-08-26 19:04:50 +0100342
343 if (!regs || !irq) {
344 dev_err(&pdev->dev, "no registers/irq defined\n");
345 return -EINVAL;
346 }
347
Alan Cox2655a2c2012-07-12 12:59:50 +0100348 spin_lock_init(&uart.port.lock);
349 uart.port.mapbase = regs->start;
350 uart.port.irq = irq->start;
351 uart.port.handle_irq = dw8250_handle_irq;
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300352 uart.port.pm = dw8250_do_pm;
Alan Cox2655a2c2012-07-12 12:59:50 +0100353 uart.port.type = PORT_8250;
Heikki Krogerusf93366f2013-01-10 11:25:07 +0200354 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
Alan Cox2655a2c2012-07-12 12:59:50 +0100355 uart.port.dev = &pdev->dev;
Jamie Iles7d4008e2011-08-26 19:04:50 +0100356
Heikki Krogerusb88d0822013-04-11 15:43:21 +0300357 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
358 resource_size(regs));
Heikki Krogerusf93366f2013-01-10 11:25:07 +0200359 if (!uart.port.membase)
360 return -ENOMEM;
361
Emilio Lópeze302cd92013-03-29 00:15:49 +0100362 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
363 if (!data)
364 return -ENOMEM;
365
David Daneyd5f1af72013-06-19 20:37:27 +0000366 data->usr_reg = DW_UART_USR;
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200367 data->clk = devm_clk_get(&pdev->dev, "baudclk");
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800368 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200369 data->clk = devm_clk_get(&pdev->dev, NULL);
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800370 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
371 return -EPROBE_DEFER;
Emilio Lópeze302cd92013-03-29 00:15:49 +0100372 if (!IS_ERR(data->clk)) {
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200373 err = clk_prepare_enable(data->clk);
374 if (err)
375 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
376 err);
377 else
378 uart.port.uartclk = clk_get_rate(data->clk);
379 }
380
381 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800382 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
383 err = -EPROBE_DEFER;
384 goto err_clk;
385 }
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200386 if (!IS_ERR(data->pclk)) {
387 err = clk_prepare_enable(data->pclk);
388 if (err) {
389 dev_err(&pdev->dev, "could not enable apb_pclk\n");
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800390 goto err_clk;
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200391 }
Emilio Lópeze302cd92013-03-29 00:15:49 +0100392 }
393
Chen-Yu Tsai7fe090b2014-07-23 23:33:06 +0800394 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800395 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
396 err = -EPROBE_DEFER;
397 goto err_pclk;
398 }
Chen-Yu Tsai7fe090b2014-07-23 23:33:06 +0800399 if (!IS_ERR(data->rst))
400 reset_control_deassert(data->rst);
401
Heikki Krogerus7fb8c562013-09-05 17:34:54 +0300402 data->dma.rx_chan_id = -1;
403 data->dma.tx_chan_id = -1;
404 data->dma.rx_param = data;
405 data->dma.tx_param = data;
406 data->dma.fn = dw8250_dma_filter;
407
Alan Cox2655a2c2012-07-12 12:59:50 +0100408 uart.port.iotype = UPIO_MEM;
409 uart.port.serial_in = dw8250_serial_in;
410 uart.port.serial_out = dw8250_serial_out;
Emilio Lópeze302cd92013-03-29 00:15:49 +0100411 uart.port.private_data = data;
Heikki Krogerusa7260c82013-01-10 11:25:08 +0200412
413 if (pdev->dev.of_node) {
David Daneyd5f1af72013-06-19 20:37:27 +0000414 err = dw8250_probe_of(&uart.port, data);
Heikki Krogerusa7260c82013-01-10 11:25:08 +0200415 if (err)
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800416 goto err_reset;
Heikki Krogerus6a7320c2013-01-10 11:25:10 +0200417 } else if (ACPI_HANDLE(&pdev->dev)) {
Heikki Krogerusfe95855532013-09-05 17:34:53 +0300418 err = dw8250_probe_acpi(&uart, data);
Heikki Krogerus6a7320c2013-01-10 11:25:10 +0200419 if (err)
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800420 goto err_reset;
Heikki Krogerusa7260c82013-01-10 11:25:08 +0200421 } else {
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800422 err = -ENODEV;
423 goto err_reset;
Jamie Iles7d4008e2011-08-26 19:04:50 +0100424 }
425
Alan Cox2655a2c2012-07-12 12:59:50 +0100426 data->line = serial8250_register_8250_port(&uart);
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800427 if (data->line < 0) {
428 err = data->line;
429 goto err_reset;
430 }
Jamie Iles7d4008e2011-08-26 19:04:50 +0100431
432 platform_set_drvdata(pdev, data);
433
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300434 pm_runtime_set_active(&pdev->dev);
435 pm_runtime_enable(&pdev->dev);
436
Jamie Iles7d4008e2011-08-26 19:04:50 +0100437 return 0;
Chen-Yu Tsaic8ed99d2014-07-23 23:33:07 +0800438
439err_reset:
440 if (!IS_ERR(data->rst))
441 reset_control_assert(data->rst);
442
443err_pclk:
444 if (!IS_ERR(data->pclk))
445 clk_disable_unprepare(data->pclk);
446
447err_clk:
448 if (!IS_ERR(data->clk))
449 clk_disable_unprepare(data->clk);
450
451 return err;
Jamie Iles7d4008e2011-08-26 19:04:50 +0100452}
453
Bill Pembertonae8d8a12012-11-19 13:26:18 -0500454static int dw8250_remove(struct platform_device *pdev)
Jamie Iles7d4008e2011-08-26 19:04:50 +0100455{
456 struct dw8250_data *data = platform_get_drvdata(pdev);
457
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300458 pm_runtime_get_sync(&pdev->dev);
459
Jamie Iles7d4008e2011-08-26 19:04:50 +0100460 serial8250_unregister_port(data->line);
461
Chen-Yu Tsai7fe090b2014-07-23 23:33:06 +0800462 if (!IS_ERR(data->rst))
463 reset_control_assert(data->rst);
464
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200465 if (!IS_ERR(data->pclk))
466 clk_disable_unprepare(data->pclk);
467
Emilio Lópeze302cd92013-03-29 00:15:49 +0100468 if (!IS_ERR(data->clk))
469 clk_disable_unprepare(data->clk);
470
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300471 pm_runtime_disable(&pdev->dev);
472 pm_runtime_put_noidle(&pdev->dev);
473
Jamie Iles7d4008e2011-08-26 19:04:50 +0100474 return 0;
475}
476
Mika Westerberg13b949f2014-01-16 14:55:57 +0200477#ifdef CONFIG_PM_SLEEP
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300478static int dw8250_suspend(struct device *dev)
James Hoganb61c5ed2012-10-15 10:25:58 +0100479{
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300480 struct dw8250_data *data = dev_get_drvdata(dev);
James Hoganb61c5ed2012-10-15 10:25:58 +0100481
482 serial8250_suspend_port(data->line);
483
484 return 0;
485}
486
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300487static int dw8250_resume(struct device *dev)
James Hoganb61c5ed2012-10-15 10:25:58 +0100488{
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300489 struct dw8250_data *data = dev_get_drvdata(dev);
James Hoganb61c5ed2012-10-15 10:25:58 +0100490
491 serial8250_resume_port(data->line);
492
493 return 0;
494}
Mika Westerberg13b949f2014-01-16 14:55:57 +0200495#endif /* CONFIG_PM_SLEEP */
James Hoganb61c5ed2012-10-15 10:25:58 +0100496
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300497#ifdef CONFIG_PM_RUNTIME
498static int dw8250_runtime_suspend(struct device *dev)
499{
500 struct dw8250_data *data = dev_get_drvdata(dev);
501
Ezequiel Garciadbd2df82013-05-07 08:27:16 -0300502 if (!IS_ERR(data->clk))
503 clk_disable_unprepare(data->clk);
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300504
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200505 if (!IS_ERR(data->pclk))
506 clk_disable_unprepare(data->pclk);
507
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300508 return 0;
509}
510
511static int dw8250_runtime_resume(struct device *dev)
512{
513 struct dw8250_data *data = dev_get_drvdata(dev);
514
Heiko Stübner7d78cbe2014-06-16 15:25:17 +0200515 if (!IS_ERR(data->pclk))
516 clk_prepare_enable(data->pclk);
517
Ezequiel Garciadbd2df82013-05-07 08:27:16 -0300518 if (!IS_ERR(data->clk))
519 clk_prepare_enable(data->clk);
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300520
521 return 0;
522}
523#endif
524
525static const struct dev_pm_ops dw8250_pm_ops = {
526 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
527 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
528};
529
Heikki Krogerusa7260c82013-01-10 11:25:08 +0200530static const struct of_device_id dw8250_of_match[] = {
Jamie Iles7d4008e2011-08-26 19:04:50 +0100531 { .compatible = "snps,dw-apb-uart" },
David Daneyd5f1af72013-06-19 20:37:27 +0000532 { .compatible = "cavium,octeon-3860-uart" },
Jamie Iles7d4008e2011-08-26 19:04:50 +0100533 { /* Sentinel */ }
534};
Heikki Krogerusa7260c82013-01-10 11:25:08 +0200535MODULE_DEVICE_TABLE(of, dw8250_of_match);
Jamie Iles7d4008e2011-08-26 19:04:50 +0100536
Heikki Krogerus6a7320c2013-01-10 11:25:10 +0200537static const struct acpi_device_id dw8250_acpi_match[] = {
Heikki Krogerusaea02e82013-04-10 16:58:29 +0300538 { "INT33C4", 0 },
539 { "INT33C5", 0 },
Mika Westerbergd24c1952013-12-10 12:56:59 +0200540 { "INT3434", 0 },
541 { "INT3435", 0 },
Heikki Krogerus4e26b132014-06-05 16:51:40 +0300542 { "80860F0A", 0 },
Heikki Krogerus6a7320c2013-01-10 11:25:10 +0200543 { },
544};
545MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
546
Jamie Iles7d4008e2011-08-26 19:04:50 +0100547static struct platform_driver dw8250_platform_driver = {
548 .driver = {
549 .name = "dw-apb-uart",
550 .owner = THIS_MODULE,
Heikki Krogerusffc3ae62013-04-10 16:58:28 +0300551 .pm = &dw8250_pm_ops,
Heikki Krogerusa7260c82013-01-10 11:25:08 +0200552 .of_match_table = dw8250_of_match,
Heikki Krogerus6a7320c2013-01-10 11:25:10 +0200553 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
Jamie Iles7d4008e2011-08-26 19:04:50 +0100554 },
555 .probe = dw8250_probe,
Bill Pemberton2d47b712012-11-19 13:21:34 -0500556 .remove = dw8250_remove,
Jamie Iles7d4008e2011-08-26 19:04:50 +0100557};
558
Axel Linc8381c152011-11-28 19:22:15 +0800559module_platform_driver(dw8250_platform_driver);
Jamie Iles7d4008e2011-08-26 19:04:50 +0100560
561MODULE_AUTHOR("Jamie Iles");
562MODULE_LICENSE("GPL");
563MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");