blob: cb924aa2b321b3e0b499876770b86f76eb78a751 [file] [log] [blame]
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +02001/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Vincent Abriou <vincent.abriou@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
7 */
8
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/module.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/reset.h>
15
16#include <drm/drmP.h>
17#include <drm/drm_crtc_helper.h>
18
Benjamin Gaignard5e03abc2014-12-08 17:32:36 +010019#include "sti_drm_crtc.h"
20
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +020021/* glue registers */
22#define TVO_CSC_MAIN_M0 0x000
23#define TVO_CSC_MAIN_M1 0x004
24#define TVO_CSC_MAIN_M2 0x008
25#define TVO_CSC_MAIN_M3 0x00c
26#define TVO_CSC_MAIN_M4 0x010
27#define TVO_CSC_MAIN_M5 0x014
28#define TVO_CSC_MAIN_M6 0x018
29#define TVO_CSC_MAIN_M7 0x01c
30#define TVO_MAIN_IN_VID_FORMAT 0x030
31#define TVO_CSC_AUX_M0 0x100
32#define TVO_CSC_AUX_M1 0x104
33#define TVO_CSC_AUX_M2 0x108
34#define TVO_CSC_AUX_M3 0x10c
35#define TVO_CSC_AUX_M4 0x110
36#define TVO_CSC_AUX_M5 0x114
37#define TVO_CSC_AUX_M6 0x118
38#define TVO_CSC_AUX_M7 0x11c
39#define TVO_AUX_IN_VID_FORMAT 0x130
40#define TVO_VIP_HDF 0x400
41#define TVO_HD_SYNC_SEL 0x418
42#define TVO_HD_DAC_CFG_OFF 0x420
43#define TVO_VIP_HDMI 0x500
44#define TVO_HDMI_FORCE_COLOR_0 0x504
45#define TVO_HDMI_FORCE_COLOR_1 0x508
46#define TVO_HDMI_CLIP_VALUE_B_CB 0x50c
47#define TVO_HDMI_CLIP_VALUE_Y_G 0x510
48#define TVO_HDMI_CLIP_VALUE_R_CR 0x514
49#define TVO_HDMI_SYNC_SEL 0x518
50#define TVO_HDMI_DFV_OBS 0x540
51
52#define TVO_IN_FMT_SIGNED BIT(0)
53#define TVO_SYNC_EXT BIT(4)
54
55#define TVO_VIP_REORDER_R_SHIFT 24
56#define TVO_VIP_REORDER_G_SHIFT 20
57#define TVO_VIP_REORDER_B_SHIFT 16
58#define TVO_VIP_REORDER_MASK 0x3
59#define TVO_VIP_REORDER_Y_G_SEL 0
60#define TVO_VIP_REORDER_CB_B_SEL 1
61#define TVO_VIP_REORDER_CR_R_SEL 2
62
63#define TVO_VIP_CLIP_SHIFT 8
64#define TVO_VIP_CLIP_MASK 0x7
65#define TVO_VIP_CLIP_DISABLED 0
66#define TVO_VIP_CLIP_EAV_SAV 1
67#define TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y 2
68#define TVO_VIP_CLIP_LIMITED_RANGE_CB_CR 3
69#define TVO_VIP_CLIP_PROG_RANGE 4
70
71#define TVO_VIP_RND_SHIFT 4
72#define TVO_VIP_RND_MASK 0x3
73#define TVO_VIP_RND_8BIT_ROUNDED 0
74#define TVO_VIP_RND_10BIT_ROUNDED 1
75#define TVO_VIP_RND_12BIT_ROUNDED 2
76
77#define TVO_VIP_SEL_INPUT_MASK 0xf
78#define TVO_VIP_SEL_INPUT_MAIN 0x0
79#define TVO_VIP_SEL_INPUT_AUX 0x8
80#define TVO_VIP_SEL_INPUT_FORCE_COLOR 0xf
81#define TVO_VIP_SEL_INPUT_BYPASS_MASK 0x1
82#define TVO_VIP_SEL_INPUT_BYPASSED 1
83
84#define TVO_SYNC_MAIN_VTG_SET_REF 0x00
85#define TVO_SYNC_MAIN_VTG_SET_1 0x01
86#define TVO_SYNC_MAIN_VTG_SET_2 0x02
87#define TVO_SYNC_MAIN_VTG_SET_3 0x03
88#define TVO_SYNC_MAIN_VTG_SET_4 0x04
89#define TVO_SYNC_MAIN_VTG_SET_5 0x05
90#define TVO_SYNC_MAIN_VTG_SET_6 0x06
91#define TVO_SYNC_AUX_VTG_SET_REF 0x10
92#define TVO_SYNC_AUX_VTG_SET_1 0x11
93#define TVO_SYNC_AUX_VTG_SET_2 0x12
94#define TVO_SYNC_AUX_VTG_SET_3 0x13
95#define TVO_SYNC_AUX_VTG_SET_4 0x14
96#define TVO_SYNC_AUX_VTG_SET_5 0x15
97#define TVO_SYNC_AUX_VTG_SET_6 0x16
98
99#define TVO_SYNC_HD_DCS_SHIFT 8
100
Benjamin Gaignard5e03abc2014-12-08 17:32:36 +0100101#define ENCODER_CRTC_MASK (BIT(0) | BIT(1))
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200102
103/* enum listing the supported output data format */
104enum sti_tvout_video_out_type {
105 STI_TVOUT_VIDEO_OUT_RGB,
106 STI_TVOUT_VIDEO_OUT_YUV,
107};
108
109struct sti_tvout {
110 struct device *dev;
111 struct drm_device *drm_dev;
112 void __iomem *regs;
113 struct reset_control *reset;
114 struct drm_encoder *hdmi;
115 struct drm_encoder *hda;
116};
117
118struct sti_tvout_encoder {
119 struct drm_encoder encoder;
120 struct sti_tvout *tvout;
121};
122
123#define to_sti_tvout_encoder(x) \
124 container_of(x, struct sti_tvout_encoder, encoder)
125
126#define to_sti_tvout(x) to_sti_tvout_encoder(x)->tvout
127
128/* preformatter conversion matrix */
129static const u32 rgb_to_ycbcr_601[8] = {
130 0xF927082E, 0x04C9FEAB, 0x01D30964, 0xFA95FD3D,
131 0x0000082E, 0x00002000, 0x00002000, 0x00000000
132};
133
134/* 709 RGB to YCbCr */
135static const u32 rgb_to_ycbcr_709[8] = {
136 0xF891082F, 0x0367FF40, 0x01280B71, 0xF9B1FE20,
137 0x0000082F, 0x00002000, 0x00002000, 0x00000000
138};
139
140static u32 tvout_read(struct sti_tvout *tvout, int offset)
141{
142 return readl(tvout->regs + offset);
143}
144
145static void tvout_write(struct sti_tvout *tvout, u32 val, int offset)
146{
147 writel(val, tvout->regs + offset);
148}
149
150/**
151 * Set the clipping mode of a VIP
152 *
153 * @tvout: tvout structure
Benjamin Gaignardca279602014-12-04 11:31:37 +0100154 * @reg: register to set
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200155 * @cr_r:
156 * @y_g:
157 * @cb_b:
158 */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100159static void tvout_vip_set_color_order(struct sti_tvout *tvout, int reg,
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200160 u32 cr_r, u32 y_g, u32 cb_b)
161{
Benjamin Gaignardca279602014-12-04 11:31:37 +0100162 u32 val = tvout_read(tvout, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200163
164 val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT);
165 val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT);
166 val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT);
167 val |= cr_r << TVO_VIP_REORDER_R_SHIFT;
168 val |= y_g << TVO_VIP_REORDER_G_SHIFT;
169 val |= cb_b << TVO_VIP_REORDER_B_SHIFT;
170
Benjamin Gaignardca279602014-12-04 11:31:37 +0100171 tvout_write(tvout, val, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200172}
173
174/**
175 * Set the clipping mode of a VIP
176 *
177 * @tvout: tvout structure
Benjamin Gaignardca279602014-12-04 11:31:37 +0100178 * @reg: register to set
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200179 * @range: clipping range
180 */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100181static void tvout_vip_set_clip_mode(struct sti_tvout *tvout, int reg, u32 range)
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200182{
Benjamin Gaignardca279602014-12-04 11:31:37 +0100183 u32 val = tvout_read(tvout, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200184
185 val &= ~(TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT);
186 val |= range << TVO_VIP_CLIP_SHIFT;
Benjamin Gaignardca279602014-12-04 11:31:37 +0100187 tvout_write(tvout, val, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200188}
189
190/**
191 * Set the rounded value of a VIP
192 *
193 * @tvout: tvout structure
Benjamin Gaignardca279602014-12-04 11:31:37 +0100194 * @reg: register to set
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200195 * @rnd: rounded val per component
196 */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100197static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd)
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200198{
Benjamin Gaignardca279602014-12-04 11:31:37 +0100199 u32 val = tvout_read(tvout, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200200
201 val &= ~(TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT);
202 val |= rnd << TVO_VIP_RND_SHIFT;
Benjamin Gaignardca279602014-12-04 11:31:37 +0100203 tvout_write(tvout, val, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200204}
205
206/**
207 * Select the VIP input
208 *
209 * @tvout: tvout structure
Benjamin Gaignardca279602014-12-04 11:31:37 +0100210 * @reg: register to set
211 * @main_path: main or auxiliary path
212 * @sel_input_logic_inverted: need to invert the logic
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200213 * @sel_input: selected_input (main/aux + conv)
214 */
215static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
Benjamin Gaignardca279602014-12-04 11:31:37 +0100216 int reg,
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200217 bool main_path,
218 bool sel_input_logic_inverted,
219 enum sti_tvout_video_out_type video_out)
220{
221 u32 sel_input;
Benjamin Gaignardca279602014-12-04 11:31:37 +0100222 u32 val = tvout_read(tvout, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200223
224 if (main_path)
225 sel_input = TVO_VIP_SEL_INPUT_MAIN;
226 else
227 sel_input = TVO_VIP_SEL_INPUT_AUX;
228
229 switch (video_out) {
230 case STI_TVOUT_VIDEO_OUT_RGB:
231 sel_input |= TVO_VIP_SEL_INPUT_BYPASSED;
232 break;
233 case STI_TVOUT_VIDEO_OUT_YUV:
234 sel_input &= ~TVO_VIP_SEL_INPUT_BYPASSED;
235 break;
236 }
237
238 /* on stih407 chip the sel_input bypass mode logic is inverted */
239 if (sel_input_logic_inverted)
240 sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
241
242 val &= ~TVO_VIP_SEL_INPUT_MASK;
243 val |= sel_input;
Benjamin Gaignardca279602014-12-04 11:31:37 +0100244 tvout_write(tvout, val, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200245}
246
247/**
248 * Select the input video signed or unsigned
249 *
250 * @tvout: tvout structure
Benjamin Gaignardca279602014-12-04 11:31:37 +0100251 * @reg: register to set
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200252 * @in_vid_signed: used video input format
253 */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100254static void tvout_vip_set_in_vid_fmt(struct sti_tvout *tvout,
255 int reg, u32 in_vid_fmt)
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200256{
Benjamin Gaignardca279602014-12-04 11:31:37 +0100257 u32 val = tvout_read(tvout, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200258
259 val &= ~TVO_IN_FMT_SIGNED;
260 val |= in_vid_fmt;
Benjamin Gaignardca279602014-12-04 11:31:37 +0100261 tvout_write(tvout, val, reg);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200262}
263
264/**
265 * Start VIP block for HDMI output
266 *
267 * @tvout: pointer on tvout structure
268 * @main_path: true if main path has to be used in the vip configuration
269 * else aux path is used.
270 */
271static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
272{
273 struct device_node *node = tvout->dev->of_node;
274 bool sel_input_logic_inverted = false;
Benjamin Gaignardca279602014-12-04 11:31:37 +0100275 u32 tvo_in_vid_format;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200276
277 dev_dbg(tvout->dev, "%s\n", __func__);
278
279 if (main_path) {
280 DRM_DEBUG_DRIVER("main vip for hdmi\n");
281 /* select the input sync for hdmi = VTG set 1 */
282 tvout_write(tvout, TVO_SYNC_MAIN_VTG_SET_1, TVO_HDMI_SYNC_SEL);
Benjamin Gaignardca279602014-12-04 11:31:37 +0100283 tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200284 } else {
285 DRM_DEBUG_DRIVER("aux vip for hdmi\n");
286 /* select the input sync for hdmi = VTG set 1 */
287 tvout_write(tvout, TVO_SYNC_AUX_VTG_SET_1, TVO_HDMI_SYNC_SEL);
Benjamin Gaignardca279602014-12-04 11:31:37 +0100288 tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200289 }
290
291 /* set color channel order */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100292 tvout_vip_set_color_order(tvout, TVO_VIP_HDMI,
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200293 TVO_VIP_REORDER_CR_R_SEL,
294 TVO_VIP_REORDER_Y_G_SEL,
295 TVO_VIP_REORDER_CB_B_SEL);
296
297 /* set clipping mode (Limited range RGB/Y) */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100298 tvout_vip_set_clip_mode(tvout, TVO_VIP_HDMI,
299 TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200300
301 /* set round mode (rounded to 8-bit per component) */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100302 tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200303
304 if (of_device_is_compatible(node, "st,stih407-tvout")) {
305 /* set input video format */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100306 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
307 TVO_IN_FMT_SIGNED);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200308 sel_input_logic_inverted = true;
309 }
310
311 /* input selection */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100312 tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path,
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200313 sel_input_logic_inverted, STI_TVOUT_VIDEO_OUT_RGB);
314}
315
316/**
317 * Start HDF VIP and HD DAC
318 *
319 * @tvout: pointer on tvout structure
320 * @main_path: true if main path has to be used in the vip configuration
321 * else aux path is used.
322 */
323static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
324{
325 struct device_node *node = tvout->dev->of_node;
326 bool sel_input_logic_inverted = false;
Benjamin Gaignardca279602014-12-04 11:31:37 +0100327 u32 tvo_in_vid_format;
328 int val;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200329
330 dev_dbg(tvout->dev, "%s\n", __func__);
331
Benjamin Gaignardca279602014-12-04 11:31:37 +0100332 if (main_path) {
333 val = TVO_SYNC_MAIN_VTG_SET_2 << TVO_SYNC_HD_DCS_SHIFT;
334 val |= TVO_SYNC_MAIN_VTG_SET_3;
335 tvout_write(tvout, val, TVO_HD_SYNC_SEL);
336 tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
337 } else {
338 val = TVO_SYNC_AUX_VTG_SET_2 << TVO_SYNC_HD_DCS_SHIFT;
339 val |= TVO_SYNC_AUX_VTG_SET_3;
340 tvout_write(tvout, val, TVO_HD_SYNC_SEL);
341 tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200342 }
343
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200344 /* set color channel order */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100345 tvout_vip_set_color_order(tvout, TVO_VIP_HDF,
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200346 TVO_VIP_REORDER_CR_R_SEL,
347 TVO_VIP_REORDER_Y_G_SEL,
348 TVO_VIP_REORDER_CB_B_SEL);
349
Benjamin Gaignardca279602014-12-04 11:31:37 +0100350 /* set clipping mode (EAV/SAV clipping) */
351 tvout_vip_set_clip_mode(tvout, TVO_VIP_HDF, TVO_VIP_CLIP_EAV_SAV);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200352
353 /* set round mode (rounded to 10-bit per component) */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100354 tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200355
356 if (of_device_is_compatible(node, "st,stih407-tvout")) {
357 /* set input video format */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100358 tvout_vip_set_in_vid_fmt(tvout,
359 tvo_in_vid_format, TVO_IN_FMT_SIGNED);
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200360 sel_input_logic_inverted = true;
361 }
362
363 /* Input selection */
Benjamin Gaignardca279602014-12-04 11:31:37 +0100364 tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path,
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200365 sel_input_logic_inverted,
366 STI_TVOUT_VIDEO_OUT_YUV);
367
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200368 /* power up HD DAC */
369 tvout_write(tvout, 0, TVO_HD_DAC_CFG_OFF);
370}
371
372static void sti_tvout_encoder_dpms(struct drm_encoder *encoder, int mode)
373{
374}
375
376static bool sti_tvout_encoder_mode_fixup(struct drm_encoder *encoder,
377 const struct drm_display_mode *mode,
378 struct drm_display_mode *adjusted_mode)
379{
380 return true;
381}
382
383static void sti_tvout_encoder_mode_set(struct drm_encoder *encoder,
384 struct drm_display_mode *mode,
385 struct drm_display_mode *adjusted_mode)
386{
387}
388
389static void sti_tvout_encoder_prepare(struct drm_encoder *encoder)
390{
391}
392
393static void sti_tvout_encoder_destroy(struct drm_encoder *encoder)
394{
395 struct sti_tvout_encoder *sti_encoder = to_sti_tvout_encoder(encoder);
396
397 drm_encoder_cleanup(encoder);
398 kfree(sti_encoder);
399}
400
401static const struct drm_encoder_funcs sti_tvout_encoder_funcs = {
402 .destroy = sti_tvout_encoder_destroy,
403};
404
405static void sti_hda_encoder_commit(struct drm_encoder *encoder)
406{
407 struct sti_tvout *tvout = to_sti_tvout(encoder);
408
Benjamin Gaignard5e03abc2014-12-08 17:32:36 +0100409 tvout_hda_start(tvout, sti_drm_crtc_is_main(encoder->crtc));
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200410}
411
412static void sti_hda_encoder_disable(struct drm_encoder *encoder)
413{
414 struct sti_tvout *tvout = to_sti_tvout(encoder);
415
416 /* reset VIP register */
417 tvout_write(tvout, 0x0, TVO_VIP_HDF);
418
419 /* power down HD DAC */
420 tvout_write(tvout, 1, TVO_HD_DAC_CFG_OFF);
421}
422
423static const struct drm_encoder_helper_funcs sti_hda_encoder_helper_funcs = {
424 .dpms = sti_tvout_encoder_dpms,
425 .mode_fixup = sti_tvout_encoder_mode_fixup,
426 .mode_set = sti_tvout_encoder_mode_set,
427 .prepare = sti_tvout_encoder_prepare,
428 .commit = sti_hda_encoder_commit,
429 .disable = sti_hda_encoder_disable,
430};
431
432static struct drm_encoder *sti_tvout_create_hda_encoder(struct drm_device *dev,
433 struct sti_tvout *tvout)
434{
435 struct sti_tvout_encoder *encoder;
436 struct drm_encoder *drm_encoder;
437
438 encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
439 if (!encoder)
440 return NULL;
441
442 encoder->tvout = tvout;
443
444 drm_encoder = (struct drm_encoder *) encoder;
445
Benjamin Gaignard5e03abc2014-12-08 17:32:36 +0100446 drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200447 drm_encoder->possible_clones = 1 << 0;
448
449 drm_encoder_init(dev, drm_encoder,
450 &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_DAC);
451
452 drm_encoder_helper_add(drm_encoder, &sti_hda_encoder_helper_funcs);
453
454 return drm_encoder;
455}
456
457static void sti_hdmi_encoder_commit(struct drm_encoder *encoder)
458{
459 struct sti_tvout *tvout = to_sti_tvout(encoder);
460
Benjamin Gaignard5e03abc2014-12-08 17:32:36 +0100461 tvout_hdmi_start(tvout, sti_drm_crtc_is_main(encoder->crtc));
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200462}
463
464static void sti_hdmi_encoder_disable(struct drm_encoder *encoder)
465{
466 struct sti_tvout *tvout = to_sti_tvout(encoder);
467
468 /* reset VIP register */
469 tvout_write(tvout, 0x0, TVO_VIP_HDMI);
470}
471
472static const struct drm_encoder_helper_funcs sti_hdmi_encoder_helper_funcs = {
473 .dpms = sti_tvout_encoder_dpms,
474 .mode_fixup = sti_tvout_encoder_mode_fixup,
475 .mode_set = sti_tvout_encoder_mode_set,
476 .prepare = sti_tvout_encoder_prepare,
477 .commit = sti_hdmi_encoder_commit,
478 .disable = sti_hdmi_encoder_disable,
479};
480
481static struct drm_encoder *sti_tvout_create_hdmi_encoder(struct drm_device *dev,
482 struct sti_tvout *tvout)
483{
484 struct sti_tvout_encoder *encoder;
485 struct drm_encoder *drm_encoder;
486
487 encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
488 if (!encoder)
489 return NULL;
490
491 encoder->tvout = tvout;
492
493 drm_encoder = (struct drm_encoder *) encoder;
494
Benjamin Gaignard5e03abc2014-12-08 17:32:36 +0100495 drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200496 drm_encoder->possible_clones = 1 << 1;
497
498 drm_encoder_init(dev, drm_encoder,
499 &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_TMDS);
500
501 drm_encoder_helper_add(drm_encoder, &sti_hdmi_encoder_helper_funcs);
502
503 return drm_encoder;
504}
505
506static void sti_tvout_create_encoders(struct drm_device *dev,
507 struct sti_tvout *tvout)
508{
509 tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout);
510 tvout->hda = sti_tvout_create_hda_encoder(dev, tvout);
511}
512
513static void sti_tvout_destroy_encoders(struct sti_tvout *tvout)
514{
515 if (tvout->hdmi)
516 drm_encoder_cleanup(tvout->hdmi);
517 tvout->hdmi = NULL;
518
519 if (tvout->hda)
520 drm_encoder_cleanup(tvout->hda);
521 tvout->hda = NULL;
522}
523
524static int sti_tvout_bind(struct device *dev, struct device *master, void *data)
525{
526 struct sti_tvout *tvout = dev_get_drvdata(dev);
527 struct drm_device *drm_dev = data;
528 unsigned int i;
529 int ret;
530
531 tvout->drm_dev = drm_dev;
532
533 /* set preformatter matrix */
534 for (i = 0; i < 8; i++) {
535 tvout_write(tvout, rgb_to_ycbcr_601[i],
536 TVO_CSC_MAIN_M0 + (i * 4));
537 tvout_write(tvout, rgb_to_ycbcr_601[i],
538 TVO_CSC_AUX_M0 + (i * 4));
539 }
540
541 sti_tvout_create_encoders(drm_dev, tvout);
542
543 ret = component_bind_all(dev, drm_dev);
544 if (ret)
545 sti_tvout_destroy_encoders(tvout);
546
547 return ret;
548}
549
550static void sti_tvout_unbind(struct device *dev, struct device *master,
551 void *data)
552{
553 /* do nothing */
554}
555
556static const struct component_ops sti_tvout_ops = {
557 .bind = sti_tvout_bind,
558 .unbind = sti_tvout_unbind,
559};
560
561static int compare_of(struct device *dev, void *data)
562{
563 return dev->of_node == data;
564}
565
566static int sti_tvout_master_bind(struct device *dev)
567{
568 return 0;
569}
570
571static void sti_tvout_master_unbind(struct device *dev)
572{
573 /* do nothing */
574}
575
576static const struct component_master_ops sti_tvout_master_ops = {
577 .bind = sti_tvout_master_bind,
578 .unbind = sti_tvout_master_unbind,
579};
580
581static int sti_tvout_probe(struct platform_device *pdev)
582{
583 struct device *dev = &pdev->dev;
584 struct device_node *node = dev->of_node;
585 struct sti_tvout *tvout;
586 struct resource *res;
587 struct device_node *child_np;
588 struct component_match *match = NULL;
589
590 DRM_INFO("%s\n", __func__);
591
592 if (!node)
593 return -ENODEV;
594
595 tvout = devm_kzalloc(dev, sizeof(*tvout), GFP_KERNEL);
596 if (!tvout)
597 return -ENOMEM;
598
599 tvout->dev = dev;
600
601 /* get Memory ressources */
602 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg");
603 if (!res) {
604 DRM_ERROR("Invalid glue resource\n");
605 return -ENOMEM;
606 }
607 tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
Wei Yongjun31f32a22014-08-26 12:17:36 +0200608 if (!tvout->regs)
609 return -ENOMEM;
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200610
611 /* get reset resources */
612 tvout->reset = devm_reset_control_get(dev, "tvout");
613 /* take tvout out of reset */
614 if (!IS_ERR(tvout->reset))
615 reset_control_deassert(tvout->reset);
616
617 platform_set_drvdata(pdev, tvout);
618
619 of_platform_populate(node, NULL, NULL, dev);
620
621 child_np = of_get_next_available_child(node, NULL);
622
623 while (child_np) {
624 component_match_add(dev, &match, compare_of, child_np);
625 of_node_put(child_np);
626 child_np = of_get_next_available_child(node, child_np);
627 }
628
629 component_master_add_with_match(dev, &sti_tvout_master_ops, match);
630
631 return component_add(dev, &sti_tvout_ops);
632}
633
634static int sti_tvout_remove(struct platform_device *pdev)
635{
636 component_master_del(&pdev->dev, &sti_tvout_master_ops);
637 component_del(&pdev->dev, &sti_tvout_ops);
638 return 0;
639}
640
Kiran Padwal8e932cf2014-08-26 12:25:24 +0200641static const struct of_device_id tvout_of_match[] = {
Benjamin Gaignardcdfbff72014-07-30 19:26:17 +0200642 { .compatible = "st,stih416-tvout", },
643 { .compatible = "st,stih407-tvout", },
644 { /* end node */ }
645};
646MODULE_DEVICE_TABLE(of, tvout_of_match);
647
648struct platform_driver sti_tvout_driver = {
649 .driver = {
650 .name = "sti-tvout",
651 .owner = THIS_MODULE,
652 .of_match_table = tvout_of_match,
653 },
654 .probe = sti_tvout_probe,
655 .remove = sti_tvout_remove,
656};
657
658module_platform_driver(sti_tvout_driver);
659
660MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
661MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
662MODULE_LICENSE("GPL");