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gerrit-public.fairphone.software / kernel / msm-5.4 / f4af3c14113d1b0d98d5a5e717b8aa1f484065b6 / . / drivers / scsi / mpt2sas / mpi / mpi2.h
blob: 9958d847a88dad016aa639388f299a15b068bb3e [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame^]11 * mpi2.h Version: 02.00.14
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]12 *
13 * Version History
14 * ---------------
15 *
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved.
54 * Added RAID Accelerator functionality.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame^]56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
58 * Index register.
59 * Added function code for Host Based Discovery Action.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]60 * --------------------------------------------------------------------------
61 */
62
63#ifndef MPI2_H
64#define MPI2_H
65
66
67/*****************************************************************************
68*
69* MPI Version Definitions
70*
71*****************************************************************************/
72
73#define MPI2_VERSION_MAJOR (0x02)
74#define MPI2_VERSION_MINOR (0x00)
75#define MPI2_VERSION_MAJOR_MASK (0xFF00)
76#define MPI2_VERSION_MAJOR_SHIFT (8)
77#define MPI2_VERSION_MINOR_MASK (0x00FF)
78#define MPI2_VERSION_MINOR_SHIFT (0)
79#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
80 MPI2_VERSION_MINOR)
81
82#define MPI2_VERSION_02_00 (0x0200)
83
84/* versioning for this MPI header set */
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame^]85#define MPI2_HEADER_VERSION_UNIT (0x0E)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]86#define MPI2_HEADER_VERSION_DEV (0x00)
87#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
88#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
89#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
90#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
91#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
92
93
94/*****************************************************************************
95*
96* IOC State Definitions
97*
98*****************************************************************************/
99
100#define MPI2_IOC_STATE_RESET (0x00000000)
101#define MPI2_IOC_STATE_READY (0x10000000)
102#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
103#define MPI2_IOC_STATE_FAULT (0x40000000)
104
105#define MPI2_IOC_STATE_MASK (0xF0000000)
106#define MPI2_IOC_STATE_SHIFT (28)
107
108/* Fault state range for prodcut specific codes */
109#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
110#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
111
112
113/*****************************************************************************
114*
115* System Interface Register Definitions
116*
117*****************************************************************************/
118
119typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
120{
121 U32 Doorbell; /* 0x00 */
122 U32 WriteSequence; /* 0x04 */
123 U32 HostDiagnostic; /* 0x08 */
124 U32 Reserved1; /* 0x0C */
125 U32 DiagRWData; /* 0x10 */
126 U32 DiagRWAddressLow; /* 0x14 */
127 U32 DiagRWAddressHigh; /* 0x18 */
128 U32 Reserved2[5]; /* 0x1C */
129 U32 HostInterruptStatus; /* 0x30 */
130 U32 HostInterruptMask; /* 0x34 */
131 U32 DCRData; /* 0x38 */
132 U32 DCRAddress; /* 0x3C */
133 U32 Reserved3[2]; /* 0x40 */
134 U32 ReplyFreeHostIndex; /* 0x48 */
135 U32 Reserved4[8]; /* 0x4C */
136 U32 ReplyPostHostIndex; /* 0x6C */
137 U32 Reserved5; /* 0x70 */
138 U32 HCBSize; /* 0x74 */
139 U32 HCBAddressLow; /* 0x78 */
140 U32 HCBAddressHigh; /* 0x7C */
141 U32 Reserved6[16]; /* 0x80 */
142 U32 RequestDescriptorPostLow; /* 0xC0 */
143 U32 RequestDescriptorPostHigh; /* 0xC4 */
144 U32 Reserved7[14]; /* 0xC8 */
145} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
146 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
147
148/*
149 * Defines for working with the Doorbell register.
150 */
151#define MPI2_DOORBELL_OFFSET (0x00000000)
152
153/* IOC --> System values */
154#define MPI2_DOORBELL_USED (0x08000000)
155#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
156#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
157#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
158#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
159
160/* System --> IOC values */
161#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
162#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
163#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
164#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
165
166
167/*
168 * Defines for the WriteSequence register
169 */
170#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
171#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
172#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
173#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
174#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
175#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
176#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
177#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
178#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
179
180/*
181 * Defines for the HostDiagnostic register
182 */
183#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
184
185#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
186#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
187#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
188
189#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
190#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
191#define MPI2_DIAG_HCB_MODE (0x00000100)
192#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
193#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
194#define MPI2_DIAG_RESET_HISTORY (0x00000020)
195#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
196#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
197#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
198
199/*
200 * Offsets for DiagRWData and address
201 */
202#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
203#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
204#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
205
206/*
207 * Defines for the HostInterruptStatus register
208 */
209#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
210#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
211#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
212#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
213#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
214#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
215#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
216
217/*
218 * Defines for the HostInterruptMask register
219 */
220#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
221#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
222#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
223#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
224#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
225#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
226
227/*
228 * Offsets for DCRData and address
229 */
230#define MPI2_DCR_DATA_OFFSET (0x00000038)
231#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
232
233/*
234 * Offset for the Reply Free Queue
235 */
236#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
237
238/*
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame^]239 * Defines for the Reply Descriptor Post Queue
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]240 */
241#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame^]242#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
243#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
244#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]245
246/*
247 * Defines for the HCBSize and address
248 */
249#define MPI2_HCB_SIZE_OFFSET (0x00000074)
250#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
251#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
252
253#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
254#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
255
256/*
257 * Offsets for the Request Queue
258 */
259#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
260#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
261
262
263/*****************************************************************************
264*
265* Message Descriptors
266*
267*****************************************************************************/
268
269/* Request Descriptors */
270
271/* Default Request Descriptor */
272typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
273{
274 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]275 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]276 U16 SMID; /* 0x02 */
277 U16 LMID; /* 0x04 */
278 U16 DescriptorTypeDependent; /* 0x06 */
279} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
280 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
281 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
282
283/* defines for the RequestFlags field */
284#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
285#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
286#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
287#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
288#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]289#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]290
291#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
292
293
294/* High Priority Request Descriptor */
295typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
296{
297 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]298 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]299 U16 SMID; /* 0x02 */
300 U16 LMID; /* 0x04 */
301 U16 Reserved1; /* 0x06 */
302} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
303 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
304 Mpi2HighPriorityRequestDescriptor_t,
305 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
306
307
308/* SCSI IO Request Descriptor */
309typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
310{
311 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]312 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]313 U16 SMID; /* 0x02 */
314 U16 LMID; /* 0x04 */
315 U16 DevHandle; /* 0x06 */
316} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
317 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
318 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
319
320
321/* SCSI Target Request Descriptor */
322typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
323{
324 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]325 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]326 U16 SMID; /* 0x02 */
327 U16 LMID; /* 0x04 */
328 U16 IoIndex; /* 0x06 */
329} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
330 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
331 Mpi2SCSITargetRequestDescriptor_t,
332 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
333
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]334
335/* RAID Accelerator Request Descriptor */
336typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
337 U8 RequestFlags; /* 0x00 */
338 U8 MSIxIndex; /* 0x01 */
339 U16 SMID; /* 0x02 */
340 U16 LMID; /* 0x04 */
341 U16 Reserved; /* 0x06 */
342} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
343 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
344 Mpi2RAIDAcceleratorRequestDescriptor_t,
345 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
346
347
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]348/* union of Request Descriptors */
349typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
350{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]351 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
352 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
353 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
354 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
355 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
356 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]357} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
358 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
359
360
361/* Reply Descriptors */
362
363/* Default Reply Descriptor */
364typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
365{
366 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]367 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]368 U16 DescriptorTypeDependent1; /* 0x02 */
369 U32 DescriptorTypeDependent2; /* 0x04 */
370} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
371 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
372
373/* defines for the ReplyFlags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]374#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
375#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
376#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
377#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
378#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
379#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
380#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]381
382/* values for marking a reply descriptor as unused */
383#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
384#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
385
386/* Address Reply Descriptor */
387typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
388{
389 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]390 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]391 U16 SMID; /* 0x02 */
392 U32 ReplyFrameAddress; /* 0x04 */
393} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
394 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
395
396#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
397
398
399/* SCSI IO Success Reply Descriptor */
400typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
401{
402 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]403 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]404 U16 SMID; /* 0x02 */
405 U16 TaskTag; /* 0x04 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]406 U16 Reserved1; /* 0x06 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]407} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
408 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
409 Mpi2SCSIIOSuccessReplyDescriptor_t,
410 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
411
412
413/* TargetAssist Success Reply Descriptor */
414typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
415{
416 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]417 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]418 U16 SMID; /* 0x02 */
419 U8 SequenceNumber; /* 0x04 */
420 U8 Reserved1; /* 0x05 */
421 U16 IoIndex; /* 0x06 */
422} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
423 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
424 Mpi2TargetAssistSuccessReplyDescriptor_t,
425 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
426
427
428/* Target Command Buffer Reply Descriptor */
429typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
430{
431 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]432 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]433 U8 VP_ID; /* 0x02 */
434 U8 Flags; /* 0x03 */
435 U16 InitiatorDevHandle; /* 0x04 */
436 U16 IoIndex; /* 0x06 */
437} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
438 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
439 Mpi2TargetCommandBufferReplyDescriptor_t,
440 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
441
442/* defines for Flags field */
443#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
444
445
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]446/* RAID Accelerator Success Reply Descriptor */
447typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
448 U8 ReplyFlags; /* 0x00 */
449 U8 MSIxIndex; /* 0x01 */
450 U16 SMID; /* 0x02 */
451 U32 Reserved; /* 0x04 */
452} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
453 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
454 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
455 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
456
457
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]458/* union of Reply Descriptors */
459typedef union _MPI2_REPLY_DESCRIPTORS_UNION
460{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]461 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
462 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
463 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
464 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
465 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
466 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
467 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]468} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
469 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
470
471
472
473/*****************************************************************************
474*
475* Message Functions
476* 0x80 -> 0x8F reserved for private message use per product
477*
478*
479*****************************************************************************/
480
481#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
482#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
483#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
484#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
485#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
486#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
487#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
488#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
489#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
490#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
491#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
492#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
493#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
494#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
495#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
496#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
497#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
498#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
499#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
500#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
501#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
502#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
503#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
504#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
505#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]506#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame^]507/* Host Based Discovery Action */
508#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]509
510
511
512/* Doorbell functions */
513#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]514#define MPI2_FUNCTION_HANDSHAKE (0x42)
515
516
517/*****************************************************************************
518*
519* IOC Status Values
520*
521*****************************************************************************/
522
523/* mask for IOCStatus status value */
524#define MPI2_IOCSTATUS_MASK (0x7FFF)
525
526/****************************************************************************
527* Common IOCStatus values for all replies
528****************************************************************************/
529
530#define MPI2_IOCSTATUS_SUCCESS (0x0000)
531#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
532#define MPI2_IOCSTATUS_BUSY (0x0002)
533#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
534#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
535#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
536#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
537#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
538#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
539#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
540
541/****************************************************************************
542* Config IOCStatus values
543****************************************************************************/
544
545#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
546#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
547#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
548#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
549#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
550#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
551
552/****************************************************************************
553* SCSI IO Reply
554****************************************************************************/
555
556#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
557#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
558#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
559#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
560#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
561#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
562#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
563#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
564#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
565#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
566#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
567#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
568
569/****************************************************************************
570* For use by SCSI Initiator and SCSI Target end-to-end data protection
571****************************************************************************/
572
573#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
574#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
575#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
576
577/****************************************************************************
578* SCSI Target values
579****************************************************************************/
580
581#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
582#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
583#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
584#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
585#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
586#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
587#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
588#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
589#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
590#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
591
592/****************************************************************************
593* Serial Attached SCSI values
594****************************************************************************/
595
596#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
597#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
598
599/****************************************************************************
600* Diagnostic Buffer Post / Diagnostic Release values
601****************************************************************************/
602
603#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
604
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]605/****************************************************************************
606* RAID Accelerator values
607****************************************************************************/
608
609#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]610
611/****************************************************************************
612* IOCStatus flag to indicate that log info is available
613****************************************************************************/
614
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]615#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]616
617/****************************************************************************
618* IOCLogInfo Types
619****************************************************************************/
620
621#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
622#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
623#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
624#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
625#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
626#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
627#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
628#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
629
630
631/*****************************************************************************
632*
633* Standard Message Structures
634*
635*****************************************************************************/
636
637/****************************************************************************
638* Request Message Header for all request messages
639****************************************************************************/
640
641typedef struct _MPI2_REQUEST_HEADER
642{
643 U16 FunctionDependent1; /* 0x00 */
644 U8 ChainOffset; /* 0x02 */
645 U8 Function; /* 0x03 */
646 U16 FunctionDependent2; /* 0x04 */
647 U8 FunctionDependent3; /* 0x06 */
648 U8 MsgFlags; /* 0x07 */
649 U8 VP_ID; /* 0x08 */
650 U8 VF_ID; /* 0x09 */
651 U16 Reserved1; /* 0x0A */
652} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
653 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
654
655
656/****************************************************************************
657* Default Reply
658****************************************************************************/
659
660typedef struct _MPI2_DEFAULT_REPLY
661{
662 U16 FunctionDependent1; /* 0x00 */
663 U8 MsgLength; /* 0x02 */
664 U8 Function; /* 0x03 */
665 U16 FunctionDependent2; /* 0x04 */
666 U8 FunctionDependent3; /* 0x06 */
667 U8 MsgFlags; /* 0x07 */
668 U8 VP_ID; /* 0x08 */
669 U8 VF_ID; /* 0x09 */
670 U16 Reserved1; /* 0x0A */
671 U16 FunctionDependent5; /* 0x0C */
672 U16 IOCStatus; /* 0x0E */
673 U32 IOCLogInfo; /* 0x10 */
674} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
675 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
676
677
678/* common version structure/union used in messages and configuration pages */
679
680typedef struct _MPI2_VERSION_STRUCT
681{
682 U8 Dev; /* 0x00 */
683 U8 Unit; /* 0x01 */
684 U8 Minor; /* 0x02 */
685 U8 Major; /* 0x03 */
686} MPI2_VERSION_STRUCT;
687
688typedef union _MPI2_VERSION_UNION
689{
690 MPI2_VERSION_STRUCT Struct;
691 U32 Word;
692} MPI2_VERSION_UNION;
693
694
695/* LUN field defines, common to many structures */
696#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
697#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
698#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
699#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
700#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
701#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
702
703
704/*****************************************************************************
705*
706* Fusion-MPT MPI Scatter Gather Elements
707*
708*****************************************************************************/
709
710/****************************************************************************
711* MPI Simple Element structures
712****************************************************************************/
713
714typedef struct _MPI2_SGE_SIMPLE32
715{
716 U32 FlagsLength;
717 U32 Address;
718} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
719 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
720
721typedef struct _MPI2_SGE_SIMPLE64
722{
723 U32 FlagsLength;
724 U64 Address;
725} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
726 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
727
728typedef struct _MPI2_SGE_SIMPLE_UNION
729{
730 U32 FlagsLength;
731 union
732 {
733 U32 Address32;
734 U64 Address64;
735 } u;
736} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
737 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
738
739
740/****************************************************************************
741* MPI Chain Element structures
742****************************************************************************/
743
744typedef struct _MPI2_SGE_CHAIN32
745{
746 U16 Length;
747 U8 NextChainOffset;
748 U8 Flags;
749 U32 Address;
750} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
751 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
752
753typedef struct _MPI2_SGE_CHAIN64
754{
755 U16 Length;
756 U8 NextChainOffset;
757 U8 Flags;
758 U64 Address;
759} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
760 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
761
762typedef struct _MPI2_SGE_CHAIN_UNION
763{
764 U16 Length;
765 U8 NextChainOffset;
766 U8 Flags;
767 union
768 {
769 U32 Address32;
770 U64 Address64;
771 } u;
772} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
773 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
774
775
776/****************************************************************************
777* MPI Transaction Context Element structures
778****************************************************************************/
779
780typedef struct _MPI2_SGE_TRANSACTION32
781{
782 U8 Reserved;
783 U8 ContextSize;
784 U8 DetailsLength;
785 U8 Flags;
786 U32 TransactionContext[1];
787 U32 TransactionDetails[1];
788} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
789 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
790
791typedef struct _MPI2_SGE_TRANSACTION64
792{
793 U8 Reserved;
794 U8 ContextSize;
795 U8 DetailsLength;
796 U8 Flags;
797 U32 TransactionContext[2];
798 U32 TransactionDetails[1];
799} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
800 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
801
802typedef struct _MPI2_SGE_TRANSACTION96
803{
804 U8 Reserved;
805 U8 ContextSize;
806 U8 DetailsLength;
807 U8 Flags;
808 U32 TransactionContext[3];
809 U32 TransactionDetails[1];
810} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
811 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
812
813typedef struct _MPI2_SGE_TRANSACTION128
814{
815 U8 Reserved;
816 U8 ContextSize;
817 U8 DetailsLength;
818 U8 Flags;
819 U32 TransactionContext[4];
820 U32 TransactionDetails[1];
821} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
822 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
823
824typedef struct _MPI2_SGE_TRANSACTION_UNION
825{
826 U8 Reserved;
827 U8 ContextSize;
828 U8 DetailsLength;
829 U8 Flags;
830 union
831 {
832 U32 TransactionContext32[1];
833 U32 TransactionContext64[2];
834 U32 TransactionContext96[3];
835 U32 TransactionContext128[4];
836 } u;
837 U32 TransactionDetails[1];
838} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
839 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
840
841
842/****************************************************************************
843* MPI SGE union for IO SGL's
844****************************************************************************/
845
846typedef struct _MPI2_MPI_SGE_IO_UNION
847{
848 union
849 {
850 MPI2_SGE_SIMPLE_UNION Simple;
851 MPI2_SGE_CHAIN_UNION Chain;
852 } u;
853} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
854 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
855
856
857/****************************************************************************
858* MPI SGE union for SGL's with Simple and Transaction elements
859****************************************************************************/
860
861typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
862{
863 union
864 {
865 MPI2_SGE_SIMPLE_UNION Simple;
866 MPI2_SGE_TRANSACTION_UNION Transaction;
867 } u;
868} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
869 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
870
871
872/****************************************************************************
873* All MPI SGE types union
874****************************************************************************/
875
876typedef struct _MPI2_MPI_SGE_UNION
877{
878 union
879 {
880 MPI2_SGE_SIMPLE_UNION Simple;
881 MPI2_SGE_CHAIN_UNION Chain;
882 MPI2_SGE_TRANSACTION_UNION Transaction;
883 } u;
884} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
885 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
886
887
888/****************************************************************************
889* MPI SGE field definition and masks
890****************************************************************************/
891
892/* Flags field bit definitions */
893
894#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
895#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
896#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
897#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
898#define MPI2_SGE_FLAGS_DIRECTION (0x04)
899#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
900#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
901
902#define MPI2_SGE_FLAGS_SHIFT (24)
903
904#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
905#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
906
907/* Element Type */
908
909#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
910#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
911#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
912#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
913
914/* Address location */
915
916#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
917
918/* Direction */
919
920#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
921#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
922
923/* Address Size */
924
925#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
926#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
927
928/* Context Size */
929
930#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
931#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
932#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
933#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
934
935#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
936#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
937
938/****************************************************************************
939* MPI SGE operation Macros
940****************************************************************************/
941
942/* SIMPLE FlagsLength manipulations... */
943#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
944#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
945#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
946#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
947
948#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
949
950#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
951#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
952#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
953
954/* CAUTION - The following are READ-MODIFY-WRITE! */
955#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
956#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
957
958#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
959
960
961/*****************************************************************************
962*
963* Fusion-MPT IEEE Scatter Gather Elements
964*
965*****************************************************************************/
966
967/****************************************************************************
968* IEEE Simple Element structures
969****************************************************************************/
970
971typedef struct _MPI2_IEEE_SGE_SIMPLE32
972{
973 U32 Address;
974 U32 FlagsLength;
975} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
976 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
977
978typedef struct _MPI2_IEEE_SGE_SIMPLE64
979{
980 U64 Address;
981 U32 Length;
982 U16 Reserved1;
983 U8 Reserved2;
984 U8 Flags;
985} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
986 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
987
988typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
989{
990 MPI2_IEEE_SGE_SIMPLE32 Simple32;
991 MPI2_IEEE_SGE_SIMPLE64 Simple64;
992} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
993 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
994
995
996/****************************************************************************
997* IEEE Chain Element structures
998****************************************************************************/
999
1000typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1001
1002typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1003
1004typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1005{
1006 MPI2_IEEE_SGE_CHAIN32 Chain32;
1007 MPI2_IEEE_SGE_CHAIN64 Chain64;
1008} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1009 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1010
1011
1012/****************************************************************************
1013* All IEEE SGE types union
1014****************************************************************************/
1015
1016typedef struct _MPI2_IEEE_SGE_UNION
1017{
1018 union
1019 {
1020 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1021 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1022 } u;
1023} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1024 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1025
1026
1027/****************************************************************************
1028* IEEE SGE field definitions and masks
1029****************************************************************************/
1030
1031/* Flags field bit definitions */
1032
1033#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1034
1035#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1036
1037#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1038
1039/* Element Type */
1040
1041#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1042#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1043
1044/* Data Location Address Space */
1045
1046#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1047#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1048#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1049#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1050#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1051
1052
1053/****************************************************************************
1054* IEEE SGE operation Macros
1055****************************************************************************/
1056
1057/* SIMPLE FlagsLength manipulations... */
1058#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1059#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1060#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1061
1062#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1063
1064#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1065#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1066#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1067
1068/* CAUTION - The following are READ-MODIFY-WRITE! */
1069#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1070#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1071
1072
1073
1074
1075/*****************************************************************************
1076*
1077* Fusion-MPT MPI/IEEE Scatter Gather Unions
1078*
1079*****************************************************************************/
1080
1081typedef union _MPI2_SIMPLE_SGE_UNION
1082{
1083 MPI2_SGE_SIMPLE_UNION MpiSimple;
1084 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1085} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1086 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1087
1088
1089typedef union _MPI2_SGE_IO_UNION
1090{
1091 MPI2_SGE_SIMPLE_UNION MpiSimple;
1092 MPI2_SGE_CHAIN_UNION MpiChain;
1093 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1094 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1095} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1096 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1097
1098
1099/****************************************************************************
1100*
1101* Values for SGLFlags field, used in many request messages with an SGL
1102*
1103****************************************************************************/
1104
1105/* values for MPI SGL Data Location Address Space subfield */
1106#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1107#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1108#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1109#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1110#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1111/* values for SGL Type subfield */
1112#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1113#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1114#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1115#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1116
1117
1118#endif
1119