blob: 991ee01731b2066044e88359dbe8a68a1331416c [file] [log] [blame]
Marek Vasut646781d2012-08-03 17:26:11 +02001/*
2 * Freescale MXS SPI master driver
3 *
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7 *
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
10 *
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
13 *
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
16 *
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 */
30
31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/ioport.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/of_gpio.h>
37#include <linux/platform_device.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/dma-mapping.h>
41#include <linux/dmaengine.h>
42#include <linux/highmem.h>
43#include <linux/clk.h>
44#include <linux/err.h>
45#include <linux/completion.h>
46#include <linux/gpio.h>
47#include <linux/regulator/consumer.h>
48#include <linux/module.h>
Marek Vasut646781d2012-08-03 17:26:11 +020049#include <linux/stmp_device.h>
50#include <linux/spi/spi.h>
51#include <linux/spi/mxs-spi.h>
52
53#define DRIVER_NAME "mxs-spi"
54
Marek Vasut010b4812012-09-04 04:40:15 +020055/* Use 10S timeout for very long transfers, it should suffice. */
56#define SSP_TIMEOUT 10000
Marek Vasut646781d2012-08-03 17:26:11 +020057
Marek Vasut474afc02012-08-03 17:26:13 +020058#define SG_MAXLEN 0xff00
59
Marek Vasut646781d2012-08-03 17:26:11 +020060struct mxs_spi {
61 struct mxs_ssp ssp;
Marek Vasut474afc02012-08-03 17:26:13 +020062 struct completion c;
Marek Vasut646781d2012-08-03 17:26:11 +020063};
64
65static int mxs_spi_setup_transfer(struct spi_device *dev,
66 struct spi_transfer *t)
67{
68 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
69 struct mxs_ssp *ssp = &spi->ssp;
Marek Vasut646781d2012-08-03 17:26:11 +020070 uint32_t hz = 0;
71
Marek Vasut646781d2012-08-03 17:26:11 +020072 hz = dev->max_speed_hz;
73 if (t && t->speed_hz)
74 hz = min(hz, t->speed_hz);
75 if (hz == 0) {
76 dev_err(&dev->dev, "Cannot continue with zero clock\n");
77 return -EINVAL;
78 }
79
80 mxs_ssp_set_clk_rate(ssp, hz);
81
Trent Piepho58f46e42013-10-01 13:14:25 -070082 writel(BM_SSP_CTRL0_LOCK_CS,
83 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +020084 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
85 BF_SSP_CTRL1_WORD_LENGTH
86 (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
87 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
88 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
89 ssp->base + HW_SSP_CTRL1(ssp));
90
91 writel(0x0, ssp->base + HW_SSP_CMD0);
92 writel(0x0, ssp->base + HW_SSP_CMD1);
93
94 return 0;
95}
96
97static int mxs_spi_setup(struct spi_device *dev)
98{
99 int err = 0;
100
101 if (!dev->bits_per_word)
102 dev->bits_per_word = 8;
103
104 if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
105 return -EINVAL;
106
107 err = mxs_spi_setup_transfer(dev, NULL);
108 if (err) {
109 dev_err(&dev->dev,
110 "Failed to setup transfer, error = %d\n", err);
111 }
112
113 return err;
114}
115
116static uint32_t mxs_spi_cs_to_reg(unsigned cs)
117{
118 uint32_t select = 0;
119
120 /*
121 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
122 *
123 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
124 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
125 * the datasheet for further details. In SPI mode, they are used to
126 * toggle the chip-select lines (nCS pins).
127 */
128 if (cs & 1)
129 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
130 if (cs & 2)
131 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
132
133 return select;
134}
135
136static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
137{
138 const uint32_t mask =
139 BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
140 uint32_t select;
141 struct mxs_ssp *ssp = &spi->ssp;
142
143 writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
144 select = mxs_spi_cs_to_reg(cs);
145 writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
146}
147
Marek Vasut646781d2012-08-03 17:26:11 +0200148static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
149{
Marek Vasutf13639d2012-09-04 04:40:18 +0200150 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
Marek Vasut646781d2012-08-03 17:26:11 +0200151 struct mxs_ssp *ssp = &spi->ssp;
152 uint32_t reg;
153
Marek Vasutf13639d2012-09-04 04:40:18 +0200154 do {
Marek Vasut646781d2012-08-03 17:26:11 +0200155 reg = readl_relaxed(ssp->base + offset);
156
Marek Vasutf13639d2012-09-04 04:40:18 +0200157 if (!set)
158 reg = ~reg;
Marek Vasut646781d2012-08-03 17:26:11 +0200159
Marek Vasutf13639d2012-09-04 04:40:18 +0200160 reg &= mask;
Marek Vasut646781d2012-08-03 17:26:11 +0200161
Marek Vasutf13639d2012-09-04 04:40:18 +0200162 if (reg == mask)
163 return 0;
164 } while (time_before(jiffies, timeout));
Marek Vasut646781d2012-08-03 17:26:11 +0200165
Marek Vasutf13639d2012-09-04 04:40:18 +0200166 return -ETIMEDOUT;
Marek Vasut646781d2012-08-03 17:26:11 +0200167}
168
Marek Vasut474afc02012-08-03 17:26:13 +0200169static void mxs_ssp_dma_irq_callback(void *param)
170{
171 struct mxs_spi *spi = param;
172 complete(&spi->c);
173}
174
175static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
176{
177 struct mxs_ssp *ssp = dev_id;
178 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
179 __func__, __LINE__,
180 readl(ssp->base + HW_SSP_CTRL1(ssp)),
181 readl(ssp->base + HW_SSP_STATUS(ssp)));
182 return IRQ_HANDLED;
183}
184
185static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
186 unsigned char *buf, int len,
187 int *first, int *last, int write)
188{
189 struct mxs_ssp *ssp = &spi->ssp;
Marek Vasut010b4812012-09-04 04:40:15 +0200190 struct dma_async_tx_descriptor *desc = NULL;
191 const bool vmalloced_buf = is_vmalloc_addr(buf);
192 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
193 const int sgs = DIV_ROUND_UP(len, desc_len);
Marek Vasut474afc02012-08-03 17:26:13 +0200194 int sg_count;
Marek Vasut010b4812012-09-04 04:40:15 +0200195 int min, ret;
196 uint32_t ctrl0;
197 struct page *vm_page;
198 void *sg_buf;
199 struct {
200 uint32_t pio[4];
201 struct scatterlist sg;
202 } *dma_xfer;
Marek Vasut474afc02012-08-03 17:26:13 +0200203
Marek Vasut010b4812012-09-04 04:40:15 +0200204 if (!len)
Marek Vasut474afc02012-08-03 17:26:13 +0200205 return -EINVAL;
Marek Vasut010b4812012-09-04 04:40:15 +0200206
207 dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
208 if (!dma_xfer)
209 return -ENOMEM;
Marek Vasut474afc02012-08-03 17:26:13 +0200210
Marek Vasut41682e02012-08-24 04:56:27 +0200211 INIT_COMPLETION(spi->c);
Marek Vasut474afc02012-08-03 17:26:13 +0200212
Marek Vasut010b4812012-09-04 04:40:15 +0200213 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
Juha Lummeba486a22012-12-26 14:48:51 +0900214 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
Marek Vasut010b4812012-09-04 04:40:15 +0200215 ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);
216
Marek Vasut474afc02012-08-03 17:26:13 +0200217 if (!write)
Marek Vasut010b4812012-09-04 04:40:15 +0200218 ctrl0 |= BM_SSP_CTRL0_READ;
Marek Vasut474afc02012-08-03 17:26:13 +0200219
220 /* Queue the DMA data transfer. */
Marek Vasut010b4812012-09-04 04:40:15 +0200221 for (sg_count = 0; sg_count < sgs; sg_count++) {
222 min = min(len, desc_len);
Marek Vasut474afc02012-08-03 17:26:13 +0200223
Marek Vasut010b4812012-09-04 04:40:15 +0200224 /* Prepare the transfer descriptor. */
225 if ((sg_count + 1 == sgs) && *last)
226 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
Marek Vasut474afc02012-08-03 17:26:13 +0200227
Juha Lummeba486a22012-12-26 14:48:51 +0900228 if (ssp->devid == IMX23_SSP) {
229 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
Marek Vasut010b4812012-09-04 04:40:15 +0200230 ctrl0 |= min;
Juha Lummeba486a22012-12-26 14:48:51 +0900231 }
Marek Vasut010b4812012-09-04 04:40:15 +0200232
233 dma_xfer[sg_count].pio[0] = ctrl0;
234 dma_xfer[sg_count].pio[3] = min;
235
236 if (vmalloced_buf) {
237 vm_page = vmalloc_to_page(buf);
238 if (!vm_page) {
239 ret = -ENOMEM;
240 goto err_vmalloc;
241 }
242 sg_buf = page_address(vm_page) +
243 ((size_t)buf & ~PAGE_MASK);
244 } else {
245 sg_buf = buf;
246 }
247
248 sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
249 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
250 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
251
252 len -= min;
253 buf += min;
254
255 /* Queue the PIO register write transfer. */
256 desc = dmaengine_prep_slave_sg(ssp->dmach,
257 (struct scatterlist *)dma_xfer[sg_count].pio,
258 (ssp->devid == IMX23_SSP) ? 1 : 4,
259 DMA_TRANS_NONE,
260 sg_count ? DMA_PREP_INTERRUPT : 0);
261 if (!desc) {
262 dev_err(ssp->dev,
263 "Failed to get PIO reg. write descriptor.\n");
264 ret = -EINVAL;
265 goto err_mapped;
266 }
267
268 desc = dmaengine_prep_slave_sg(ssp->dmach,
269 &dma_xfer[sg_count].sg, 1,
270 write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
271 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
272
273 if (!desc) {
274 dev_err(ssp->dev,
275 "Failed to get DMA data write descriptor.\n");
276 ret = -EINVAL;
277 goto err_mapped;
278 }
Marek Vasut474afc02012-08-03 17:26:13 +0200279 }
280
281 /*
282 * The last descriptor must have this callback,
283 * to finish the DMA transaction.
284 */
285 desc->callback = mxs_ssp_dma_irq_callback;
286 desc->callback_param = spi;
287
288 /* Start the transfer. */
289 dmaengine_submit(desc);
290 dma_async_issue_pending(ssp->dmach);
291
292 ret = wait_for_completion_timeout(&spi->c,
293 msecs_to_jiffies(SSP_TIMEOUT));
Marek Vasut474afc02012-08-03 17:26:13 +0200294 if (!ret) {
295 dev_err(ssp->dev, "DMA transfer timeout\n");
296 ret = -ETIMEDOUT;
Marek Vasut44968462012-10-14 04:32:56 +0200297 dmaengine_terminate_all(ssp->dmach);
Marek Vasut010b4812012-09-04 04:40:15 +0200298 goto err_vmalloc;
Marek Vasut474afc02012-08-03 17:26:13 +0200299 }
300
301 ret = 0;
302
Marek Vasut010b4812012-09-04 04:40:15 +0200303err_vmalloc:
304 while (--sg_count >= 0) {
305err_mapped:
306 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
Marek Vasut474afc02012-08-03 17:26:13 +0200307 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
308 }
309
Marek Vasut010b4812012-09-04 04:40:15 +0200310 kfree(dma_xfer);
311
Marek Vasut474afc02012-08-03 17:26:13 +0200312 return ret;
313}
314
Marek Vasut646781d2012-08-03 17:26:11 +0200315static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
316 unsigned char *buf, int len,
317 int *first, int *last, int write)
318{
319 struct mxs_ssp *ssp = &spi->ssp;
320
321 if (*first)
Trent Piephof5bc7382013-10-01 13:14:32 -0700322 writel(BM_SSP_CTRL0_IGNORE_CRC,
323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
Marek Vasut646781d2012-08-03 17:26:11 +0200324
325 mxs_spi_set_cs(spi, cs);
326
327 while (len--) {
328 if (*last && len == 0)
Trent Piephof5bc7382013-10-01 13:14:32 -0700329 writel(BM_SSP_CTRL0_IGNORE_CRC,
330 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +0200331
332 if (ssp->devid == IMX23_SSP) {
333 writel(BM_SSP_CTRL0_XFER_COUNT,
334 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
335 writel(1,
336 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
337 } else {
338 writel(1, ssp->base + HW_SSP_XFER_SIZE);
339 }
340
341 if (write)
342 writel(BM_SSP_CTRL0_READ,
343 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
344 else
345 writel(BM_SSP_CTRL0_READ,
346 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
347
348 writel(BM_SSP_CTRL0_RUN,
349 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
350
351 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
352 return -ETIMEDOUT;
353
354 if (write)
355 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
356
357 writel(BM_SSP_CTRL0_DATA_XFER,
358 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
359
360 if (!write) {
361 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
362 BM_SSP_STATUS_FIFO_EMPTY, 0))
363 return -ETIMEDOUT;
364
365 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
366 }
367
368 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
369 return -ETIMEDOUT;
370
371 buf++;
372 }
373
374 if (len <= 0)
375 return 0;
376
377 return -ETIMEDOUT;
378}
379
380static int mxs_spi_transfer_one(struct spi_master *master,
381 struct spi_message *m)
382{
383 struct mxs_spi *spi = spi_master_get_devdata(master);
384 struct mxs_ssp *ssp = &spi->ssp;
385 int first, last;
386 struct spi_transfer *t, *tmp_t;
387 int status = 0;
388 int cs;
389
390 first = last = 0;
391
392 cs = m->spi->chip_select;
393
394 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
395
396 status = mxs_spi_setup_transfer(m->spi, t);
397 if (status)
398 break;
399
400 if (&t->transfer_list == m->transfers.next)
401 first = 1;
402 if (&t->transfer_list == m->transfers.prev)
403 last = 1;
Marek Vasut474afc02012-08-03 17:26:13 +0200404 if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
Marek Vasut646781d2012-08-03 17:26:11 +0200405 dev_err(ssp->dev,
406 "Cannot send and receive simultaneously\n");
407 status = -EINVAL;
408 break;
409 }
410
Marek Vasut474afc02012-08-03 17:26:13 +0200411 /*
412 * Small blocks can be transfered via PIO.
413 * Measured by empiric means:
414 *
415 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
416 *
417 * DMA only: 2.164808 seconds, 473.0KB/s
418 * Combined: 1.676276 seconds, 610.9KB/s
419 */
Marek Vasut727c10e2012-09-04 04:40:17 +0200420 if (t->len < 32) {
Marek Vasut474afc02012-08-03 17:26:13 +0200421 writel(BM_SSP_CTRL1_DMA_ENABLE,
422 ssp->base + HW_SSP_CTRL1(ssp) +
423 STMP_OFFSET_REG_CLR);
424
425 if (t->tx_buf)
426 status = mxs_spi_txrx_pio(spi, cs,
427 (void *)t->tx_buf,
428 t->len, &first, &last, 1);
429 if (t->rx_buf)
430 status = mxs_spi_txrx_pio(spi, cs,
431 t->rx_buf, t->len,
432 &first, &last, 0);
433 } else {
434 writel(BM_SSP_CTRL1_DMA_ENABLE,
435 ssp->base + HW_SSP_CTRL1(ssp) +
436 STMP_OFFSET_REG_SET);
437
438 if (t->tx_buf)
439 status = mxs_spi_txrx_dma(spi, cs,
440 (void *)t->tx_buf, t->len,
441 &first, &last, 1);
442 if (t->rx_buf)
443 status = mxs_spi_txrx_dma(spi, cs,
444 t->rx_buf, t->len,
445 &first, &last, 0);
446 }
Marek Vasut646781d2012-08-03 17:26:11 +0200447
Marek Vasutc895db02012-08-24 04:34:18 +0200448 if (status) {
449 stmp_reset_block(ssp->base);
Marek Vasut646781d2012-08-03 17:26:11 +0200450 break;
Marek Vasutc895db02012-08-24 04:34:18 +0200451 }
Marek Vasut646781d2012-08-03 17:26:11 +0200452
Marek Vasut204e7062012-09-04 04:40:16 +0200453 m->actual_length += t->len;
Marek Vasut646781d2012-08-03 17:26:11 +0200454 first = last = 0;
455 }
456
Marek Vasutd856f1eb2012-10-14 04:32:55 +0200457 m->status = status;
Marek Vasut646781d2012-08-03 17:26:11 +0200458 spi_finalize_current_message(master);
459
460 return status;
461}
462
463static const struct of_device_id mxs_spi_dt_ids[] = {
464 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
465 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
466 { /* sentinel */ }
467};
468MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
469
Grant Likelyfd4a3192012-12-07 16:57:14 +0000470static int mxs_spi_probe(struct platform_device *pdev)
Marek Vasut646781d2012-08-03 17:26:11 +0200471{
472 const struct of_device_id *of_id =
473 of_match_device(mxs_spi_dt_ids, &pdev->dev);
474 struct device_node *np = pdev->dev.of_node;
475 struct spi_master *master;
476 struct mxs_spi *spi;
477 struct mxs_ssp *ssp;
Shawn Guo26aafa72013-02-26 11:07:32 +0800478 struct resource *iores;
Marek Vasut646781d2012-08-03 17:26:11 +0200479 struct clk *clk;
480 void __iomem *base;
Shawn Guo26aafa72013-02-26 11:07:32 +0800481 int devid, clk_freq;
482 int ret = 0, irq_err;
Marek Vasut646781d2012-08-03 17:26:11 +0200483
Marek Vasute64d07a2012-08-22 22:38:35 +0200484 /*
485 * Default clock speed for the SPI core. 160MHz seems to
486 * work reasonably well with most SPI flashes, so use this
487 * as a default. Override with "clock-frequency" DT prop.
488 */
489 const int clk_freq_default = 160000000;
490
Marek Vasut646781d2012-08-03 17:26:11 +0200491 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Marek Vasut474afc02012-08-03 17:26:13 +0200492 irq_err = platform_get_irq(pdev, 0);
Fabio Estevam796305a2013-07-21 22:29:54 -0300493 if (irq_err < 0)
Marek Vasut646781d2012-08-03 17:26:11 +0200494 return -EINVAL;
495
Thierry Redingb0ee5602013-01-21 11:09:18 +0100496 base = devm_ioremap_resource(&pdev->dev, iores);
497 if (IS_ERR(base))
498 return PTR_ERR(base);
Marek Vasut646781d2012-08-03 17:26:11 +0200499
Marek Vasut646781d2012-08-03 17:26:11 +0200500 clk = devm_clk_get(&pdev->dev, NULL);
501 if (IS_ERR(clk))
502 return PTR_ERR(clk);
503
Shawn Guo26aafa72013-02-26 11:07:32 +0800504 devid = (enum mxs_ssp_id) of_id->data;
505 ret = of_property_read_u32(np, "clock-frequency",
506 &clk_freq);
507 if (ret)
Marek Vasute64d07a2012-08-22 22:38:35 +0200508 clk_freq = clk_freq_default;
Marek Vasut646781d2012-08-03 17:26:11 +0200509
510 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
511 if (!master)
512 return -ENOMEM;
513
514 master->transfer_one_message = mxs_spi_transfer_one;
515 master->setup = mxs_spi_setup;
Stephen Warren24778be2013-05-21 20:36:35 -0600516 master->bits_per_word_mask = SPI_BPW_MASK(8);
Marek Vasut646781d2012-08-03 17:26:11 +0200517 master->mode_bits = SPI_CPOL | SPI_CPHA;
518 master->num_chipselect = 3;
519 master->dev.of_node = np;
520 master->flags = SPI_MASTER_HALF_DUPLEX;
521
522 spi = spi_master_get_devdata(master);
523 ssp = &spi->ssp;
524 ssp->dev = &pdev->dev;
525 ssp->clk = clk;
526 ssp->base = base;
527 ssp->devid = devid;
528
Marek Vasut41682e02012-08-24 04:56:27 +0200529 init_completion(&spi->c);
530
Marek Vasut474afc02012-08-03 17:26:13 +0200531 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
532 DRIVER_NAME, ssp);
533 if (ret)
534 goto out_master_free;
535
Shawn Guo26aafa72013-02-26 11:07:32 +0800536 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
Marek Vasut474afc02012-08-03 17:26:13 +0200537 if (!ssp->dmach) {
538 dev_err(ssp->dev, "Failed to request DMA\n");
Wei Yongjun58ad60b2013-04-03 21:06:40 +0800539 ret = -ENODEV;
Marek Vasut474afc02012-08-03 17:26:13 +0200540 goto out_master_free;
541 }
542
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300543 ret = clk_prepare_enable(ssp->clk);
544 if (ret)
545 goto out_dma_release;
546
Marek Vasute64d07a2012-08-22 22:38:35 +0200547 clk_set_rate(ssp->clk, clk_freq);
Marek Vasut646781d2012-08-03 17:26:11 +0200548 ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
549
Fabio Estevam8498bce2013-07-10 00:16:29 -0300550 ret = stmp_reset_block(ssp->base);
551 if (ret)
552 goto out_disable_clk;
Marek Vasut646781d2012-08-03 17:26:11 +0200553
554 platform_set_drvdata(pdev, master);
555
556 ret = spi_register_master(master);
557 if (ret) {
558 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300559 goto out_disable_clk;
Marek Vasut646781d2012-08-03 17:26:11 +0200560 }
561
562 return 0;
563
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300564out_disable_clk:
Marek Vasut646781d2012-08-03 17:26:11 +0200565 clk_disable_unprepare(ssp->clk);
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300566out_dma_release:
Fabio Estevame11933f2013-07-10 00:16:27 -0300567 dma_release_channel(ssp->dmach);
Marek Vasut474afc02012-08-03 17:26:13 +0200568out_master_free:
Marek Vasut646781d2012-08-03 17:26:11 +0200569 spi_master_put(master);
570 return ret;
571}
572
Grant Likelyfd4a3192012-12-07 16:57:14 +0000573static int mxs_spi_remove(struct platform_device *pdev)
Marek Vasut646781d2012-08-03 17:26:11 +0200574{
575 struct spi_master *master;
576 struct mxs_spi *spi;
577 struct mxs_ssp *ssp;
578
Guenter Roeck7d520d22012-08-24 11:03:02 -0700579 master = spi_master_get(platform_get_drvdata(pdev));
Marek Vasut646781d2012-08-03 17:26:11 +0200580 spi = spi_master_get_devdata(master);
581 ssp = &spi->ssp;
582
583 spi_unregister_master(master);
Marek Vasut646781d2012-08-03 17:26:11 +0200584 clk_disable_unprepare(ssp->clk);
Fabio Estevame11933f2013-07-10 00:16:27 -0300585 dma_release_channel(ssp->dmach);
Marek Vasut646781d2012-08-03 17:26:11 +0200586 spi_master_put(master);
587
588 return 0;
589}
590
591static struct platform_driver mxs_spi_driver = {
592 .probe = mxs_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000593 .remove = mxs_spi_remove,
Marek Vasut646781d2012-08-03 17:26:11 +0200594 .driver = {
595 .name = DRIVER_NAME,
596 .owner = THIS_MODULE,
597 .of_match_table = mxs_spi_dt_ids,
598 },
599};
600
601module_platform_driver(mxs_spi_driver);
602
603MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
604MODULE_DESCRIPTION("MXS SPI master driver");
605MODULE_LICENSE("GPL");
606MODULE_ALIAS("platform:mxs-spi");