blob: 241abc140896f84cb1959c9b99eb53bf6ec4f6cb [file] [log] [blame]
Alex Deucher97b2e202015-04-20 16:51:00 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
Christian Königa9f87f62017-03-30 14:03:59 +020035#include <linux/rbtree.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040036#include <linux/hashtable.h>
Chris Wilsonf54d1862016-10-25 13:00:45 +010037#include <linux/dma-fence.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040038
Masahiro Yamada248a1d62017-04-24 13:50:21 +090039#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040044
Chunming Zhoud03846a2015-07-28 14:20:03 -040045#include <drm/drmP.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040046#include <drm/drm_gem.h>
Chunming Zhou7e5a5472015-04-24 17:37:30 +080047#include <drm/amdgpu_drm.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040048
Andres Rodriguez78c16832017-02-02 00:38:22 -050049#include <kgd_kfd_interface.h>
50
yanyang15fc3aee2015-05-22 14:39:35 -040051#include "amd_shared.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040052#include "amdgpu_mode.h"
53#include "amdgpu_ih.h"
54#include "amdgpu_irq.h"
55#include "amdgpu_ucode.h"
Flora Cuic632d792016-08-02 11:32:41 +080056#include "amdgpu_ttm.h"
Huang Rui0e5ca0d2017-03-03 18:37:23 -050057#include "amdgpu_psp.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040058#include "amdgpu_gds.h"
Christian König56113502016-09-28 12:36:44 +020059#include "amdgpu_sync.h"
Christian König78023012016-09-28 15:33:18 +020060#include "amdgpu_ring.h"
Christian König073440d2016-09-28 15:41:50 +020061#include "amdgpu_vm.h"
Alex Deucher1f7371b2015-12-02 17:46:21 -050062#include "amd_powerplay.h"
Alex Deuchercf0978812016-10-07 11:40:09 -040063#include "amdgpu_dpm.h"
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -040064#include "amdgpu_acp.h"
Leo Liu4df654d2017-01-02 10:07:33 -050065#include "amdgpu_uvd.h"
Leo Liu5e568172017-01-10 11:02:58 -050066#include "amdgpu_vce.h"
Leo Liu95aa13f2017-05-11 16:27:33 -040067#include "amdgpu_vcn.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040068
Alex Deucherb80d8472015-08-16 22:55:02 -040069#include "gpu_scheduler.h"
Monk Liuceeb50e2016-09-19 12:13:58 +080070#include "amdgpu_virt.h"
Christian König3490bdb2017-07-06 22:02:41 +020071#include "amdgpu_gart.h"
Alex Deucherb80d8472015-08-16 22:55:02 -040072
Alex Deucher97b2e202015-04-20 16:51:00 -040073/*
74 * Modules parameters.
75 */
76extern int amdgpu_modeset;
77extern int amdgpu_vram_limit;
John Brooks218b5dc2017-06-27 22:33:17 -040078extern int amdgpu_vis_vram_limit;
Christian Königf9321cc2017-07-07 13:44:05 +020079extern unsigned amdgpu_gart_size;
Christian König36d38372017-07-07 13:17:45 +020080extern int amdgpu_gtt_size;
Marek Olšák95844d22016-08-17 23:49:27 +020081extern int amdgpu_moverate;
Alex Deucher97b2e202015-04-20 16:51:00 -040082extern int amdgpu_benchmarking;
83extern int amdgpu_testing;
84extern int amdgpu_audio;
85extern int amdgpu_disp_priority;
86extern int amdgpu_hw_i2c;
87extern int amdgpu_pcie_gen2;
88extern int amdgpu_msi;
89extern int amdgpu_lockup_timeout;
90extern int amdgpu_dpm;
Huang Ruie635ee02016-11-01 15:35:38 +080091extern int amdgpu_fw_load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -040092extern int amdgpu_aspm;
93extern int amdgpu_runtime_pm;
Alex Deucher97b2e202015-04-20 16:51:00 -040094extern unsigned amdgpu_ip_block_mask;
95extern int amdgpu_bapm;
96extern int amdgpu_deep_color;
97extern int amdgpu_vm_size;
98extern int amdgpu_vm_block_size;
Christian Königd9c13152015-09-28 12:31:26 +020099extern int amdgpu_vm_fault_stop;
Christian Königb495bd32015-09-10 14:00:35 +0200100extern int amdgpu_vm_debug;
Harish Kasiviswanathan9a4b7d42017-06-09 11:26:57 -0400101extern int amdgpu_vm_update_mode;
Jammy Zhou1333f722015-07-30 16:36:58 +0800102extern int amdgpu_sched_jobs;
Jammy Zhou4afcb302015-07-30 16:44:05 +0800103extern int amdgpu_sched_hw_submission;
Rex Zhu3ca67302016-11-02 13:38:37 +0800104extern int amdgpu_no_evict;
105extern int amdgpu_direct_gma_size;
Alex Deuchercd474ba2016-02-04 10:21:23 -0500106extern unsigned amdgpu_pcie_gen_cap;
107extern unsigned amdgpu_pcie_lane_cap;
Nicolai Hähnle395d1fb2016-06-02 12:32:07 +0200108extern unsigned amdgpu_cg_mask;
109extern unsigned amdgpu_pg_mask;
Felix Kuehlinga6673862016-07-15 18:37:05 -0400110extern unsigned amdgpu_sdma_phase_quantum;
Nicolai Hähnle6f8941a2016-06-17 19:31:33 +0200111extern char *amdgpu_disable_cu;
Emily Deng9accf2f2016-08-10 16:01:25 +0800112extern char *amdgpu_virtual_display;
Rex Zhu5141e9d2016-09-06 16:34:37 +0800113extern unsigned amdgpu_pp_feature_mask;
Christian König6a7f76e2016-08-24 15:51:49 +0200114extern int amdgpu_vram_page_split;
Alex Deucherbce23e02017-03-28 12:52:08 -0400115extern int amdgpu_ngg;
116extern int amdgpu_prim_buf_per_se;
117extern int amdgpu_pos_buf_per_se;
118extern int amdgpu_cntl_sb_buf_per_se;
119extern int amdgpu_param_buf_per_se;
Monk Liu65781c72017-05-11 13:36:44 +0800120extern int amdgpu_job_hang_limit;
Hawking Zhange8835e02017-05-26 14:40:36 +0800121extern int amdgpu_lbpw;
Alex Deucher97b2e202015-04-20 16:51:00 -0400122
Felix Kuehling6dd13092017-06-05 18:53:55 +0900123#ifdef CONFIG_DRM_AMDGPU_SI
124extern int amdgpu_si_support;
125#endif
Felix Kuehling7df28982017-06-05 18:43:27 +0900126#ifdef CONFIG_DRM_AMDGPU_CIK
127extern int amdgpu_cik_support;
128#endif
Alex Deucher97b2e202015-04-20 16:51:00 -0400129
Chunming Zhou55ed8caf2017-04-21 16:40:00 +0800130#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
Chunming Zhou4b559c92015-07-21 15:53:04 +0800131#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
Alex Deucher97b2e202015-04-20 16:51:00 -0400132#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
133#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
134/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
135#define AMDGPU_IB_POOL_SIZE 16
136#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
137#define AMDGPUFB_CONN_LIMIT 4
Alex Deuchera5bde2f2016-09-23 16:23:41 -0400138#define AMDGPU_BIOS_NUM_SCRATCH 16
Alex Deucher97b2e202015-04-20 16:51:00 -0400139
Jammy Zhou36f523a2015-09-01 12:54:27 +0800140/* max number of IP instances */
141#define AMDGPU_MAX_SDMA_INSTANCES 2
142
Alex Deucher97b2e202015-04-20 16:51:00 -0400143/* hard reset data */
144#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
145
146/* reset flags */
147#define AMDGPU_RESET_GFX (1 << 0)
148#define AMDGPU_RESET_COMPUTE (1 << 1)
149#define AMDGPU_RESET_DMA (1 << 2)
150#define AMDGPU_RESET_CP (1 << 3)
151#define AMDGPU_RESET_GRBM (1 << 4)
152#define AMDGPU_RESET_DMA1 (1 << 5)
153#define AMDGPU_RESET_RLC (1 << 6)
154#define AMDGPU_RESET_SEM (1 << 7)
155#define AMDGPU_RESET_IH (1 << 8)
156#define AMDGPU_RESET_VMC (1 << 9)
157#define AMDGPU_RESET_MC (1 << 10)
158#define AMDGPU_RESET_DISPLAY (1 << 11)
159#define AMDGPU_RESET_UVD (1 << 12)
160#define AMDGPU_RESET_VCE (1 << 13)
161#define AMDGPU_RESET_VCE1 (1 << 14)
162
Alex Deucher97b2e202015-04-20 16:51:00 -0400163/* GFX current status */
164#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
165#define AMDGPU_GFX_SAFE_MODE 0x00000001L
166#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
167#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
168#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
169
170/* max cursor sizes (in pixels) */
171#define CIK_CURSOR_WIDTH 128
172#define CIK_CURSOR_HEIGHT 128
173
174struct amdgpu_device;
Alex Deucher97b2e202015-04-20 16:51:00 -0400175struct amdgpu_ib;
Alex Deucher97b2e202015-04-20 16:51:00 -0400176struct amdgpu_cs_parser;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800177struct amdgpu_job;
Alex Deucher97b2e202015-04-20 16:51:00 -0400178struct amdgpu_irq_src;
Alex Deucher0b492a42015-08-16 22:48:26 -0400179struct amdgpu_fpriv;
Alex Deucher97b2e202015-04-20 16:51:00 -0400180
181enum amdgpu_cp_irq {
182 AMDGPU_CP_IRQ_GFX_EOP = 0,
183 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
184 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
191
192 AMDGPU_CP_IRQ_LAST
193};
194
195enum amdgpu_sdma_irq {
196 AMDGPU_SDMA_IRQ_TRAP0 = 0,
197 AMDGPU_SDMA_IRQ_TRAP1,
198
199 AMDGPU_SDMA_IRQ_LAST
200};
201
202enum amdgpu_thermal_irq {
203 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
204 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
205
206 AMDGPU_THERMAL_IRQ_LAST
207};
208
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800209enum amdgpu_kiq_irq {
210 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
211 AMDGPU_CP_KIQ_IRQ_LAST
212};
213
Alex Deucher97b2e202015-04-20 16:51:00 -0400214int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400215 enum amd_ip_block_type block_type,
216 enum amd_clockgating_state state);
Alex Deucher97b2e202015-04-20 16:51:00 -0400217int amdgpu_set_powergating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400218 enum amd_ip_block_type block_type,
219 enum amd_powergating_state state);
Huang Rui6cb2d4e2017-01-05 18:44:41 +0800220void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
Alex Deucher5dbbb602016-06-23 11:41:04 -0400221int amdgpu_wait_for_idle(struct amdgpu_device *adev,
222 enum amd_ip_block_type block_type);
223bool amdgpu_is_idle(struct amdgpu_device *adev,
224 enum amd_ip_block_type block_type);
Alex Deucher97b2e202015-04-20 16:51:00 -0400225
Alex Deuchera1255102016-10-13 17:41:13 -0400226#define AMDGPU_MAX_IP_NUM 16
227
228struct amdgpu_ip_block_status {
229 bool valid;
230 bool sw;
231 bool hw;
232 bool late_initialized;
233 bool hang;
234};
235
Alex Deucher97b2e202015-04-20 16:51:00 -0400236struct amdgpu_ip_block_version {
Alex Deuchera1255102016-10-13 17:41:13 -0400237 const enum amd_ip_block_type type;
238 const u32 major;
239 const u32 minor;
240 const u32 rev;
yanyang15fc3aee2015-05-22 14:39:35 -0400241 const struct amd_ip_funcs *funcs;
Alex Deucher97b2e202015-04-20 16:51:00 -0400242};
243
Alex Deuchera1255102016-10-13 17:41:13 -0400244struct amdgpu_ip_block {
245 struct amdgpu_ip_block_status status;
246 const struct amdgpu_ip_block_version *version;
247};
248
Alex Deucher97b2e202015-04-20 16:51:00 -0400249int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400250 enum amd_ip_block_type type,
Alex Deucher97b2e202015-04-20 16:51:00 -0400251 u32 major, u32 minor);
252
Alex Deuchera1255102016-10-13 17:41:13 -0400253struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
254 enum amd_ip_block_type type);
255
256int amdgpu_ip_block_add(struct amdgpu_device *adev,
257 const struct amdgpu_ip_block_version *ip_block_version);
Alex Deucher97b2e202015-04-20 16:51:00 -0400258
259/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
260struct amdgpu_buffer_funcs {
261 /* maximum bytes in a single operation */
262 uint32_t copy_max_bytes;
263
264 /* number of dw to reserve per operation */
265 unsigned copy_num_dw;
266
267 /* used for buffer migration */
Chunming Zhouc7ae72c2015-08-25 17:23:45 +0800268 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400269 /* src addr in bytes */
270 uint64_t src_offset,
271 /* dst addr in bytes */
272 uint64_t dst_offset,
273 /* number of byte to transfer */
274 uint32_t byte_count);
275
276 /* maximum bytes in a single operation */
277 uint32_t fill_max_bytes;
278
279 /* number of dw to reserve per operation */
280 unsigned fill_num_dw;
281
282 /* used for buffer clearing */
Chunming Zhou6e7a3842015-08-27 13:46:09 +0800283 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400284 /* value to write to memory */
285 uint32_t src_data,
286 /* dst addr in bytes */
287 uint64_t dst_offset,
288 /* number of byte to fill */
289 uint32_t byte_count);
290};
291
292/* provided by hw blocks that can write ptes, e.g., sdma */
293struct amdgpu_vm_pte_funcs {
294 /* copy pte entries from GART */
295 void (*copy_pte)(struct amdgpu_ib *ib,
296 uint64_t pe, uint64_t src,
297 unsigned count);
298 /* write pte one entry at a time with addr mapping */
Christian Königde9ea7b2016-08-12 11:33:30 +0200299 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
300 uint64_t value, unsigned count,
301 uint32_t incr);
Alex Deucher97b2e202015-04-20 16:51:00 -0400302 /* for linear pte/pde updates without addr mapping */
303 void (*set_pte_pde)(struct amdgpu_ib *ib,
304 uint64_t pe,
305 uint64_t addr, unsigned count,
Chunming Zhou6b777602016-09-21 16:19:19 +0800306 uint32_t incr, uint64_t flags);
Alex Deucher97b2e202015-04-20 16:51:00 -0400307};
308
309/* provided by the gmc block */
310struct amdgpu_gart_funcs {
311 /* flush the vm tlb via mmio */
312 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
313 uint32_t vmid);
314 /* write pte/pde updates using the cpu */
315 int (*set_pte_pde)(struct amdgpu_device *adev,
316 void *cpu_pt_addr, /* cpu addr of page table */
317 uint32_t gpu_page_idx, /* pte/pde to update */
318 uint64_t addr, /* addr to write into pte/pde */
Chunming Zhou6b777602016-09-21 16:19:19 +0800319 uint64_t flags); /* access flags */
Christian König284710f2017-01-30 11:09:31 +0100320 /* enable/disable PRT support */
321 void (*set_prt)(struct amdgpu_device *adev, bool enable);
Alex Xie54635452017-02-14 12:22:57 -0500322 /* set pte flags based per asic */
323 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
324 uint32_t flags);
Christian Königb1166322017-05-12 15:39:39 +0200325 /* get the pde for a given mc addr */
326 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
Christian König03f89fe2017-04-04 16:07:45 +0200327 uint32_t (*get_invalidate_req)(unsigned int vm_id);
Alex Xiee60f8db2017-03-09 11:36:26 -0500328};
329
Alex Deucher97b2e202015-04-20 16:51:00 -0400330/* provided by the ih block */
331struct amdgpu_ih_funcs {
332 /* ring read/write ptr handling, called from interrupt context */
333 u32 (*get_wptr)(struct amdgpu_device *adev);
334 void (*decode_iv)(struct amdgpu_device *adev,
335 struct amdgpu_iv_entry *entry);
336 void (*set_rptr)(struct amdgpu_device *adev);
337};
338
Alex Deucher97b2e202015-04-20 16:51:00 -0400339/*
340 * BIOS.
341 */
342bool amdgpu_get_bios(struct amdgpu_device *adev);
343bool amdgpu_read_bios(struct amdgpu_device *adev);
344
345/*
346 * Dummy page
347 */
348struct amdgpu_dummy_page {
349 struct page *page;
350 dma_addr_t addr;
351};
352int amdgpu_dummy_page_init(struct amdgpu_device *adev);
353void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
354
355
356/*
357 * Clocks
358 */
359
360#define AMDGPU_MAX_PPLL 3
361
362struct amdgpu_clock {
363 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
364 struct amdgpu_pll spll;
365 struct amdgpu_pll mpll;
366 /* 10 Khz units */
367 uint32_t default_mclk;
368 uint32_t default_sclk;
369 uint32_t default_dispclk;
370 uint32_t current_dispclk;
371 uint32_t dp_extclk;
372 uint32_t max_pixel_clock;
373};
374
375/*
Flora Cuic632d792016-08-02 11:32:41 +0800376 * BO.
Alex Deucher97b2e202015-04-20 16:51:00 -0400377 */
Alex Deucher97b2e202015-04-20 16:51:00 -0400378struct amdgpu_bo_list_entry {
379 struct amdgpu_bo *robj;
380 struct ttm_validate_buffer tv;
381 struct amdgpu_bo_va *bo_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400382 uint32_t priority;
Christian König2f568db2016-02-23 12:36:59 +0100383 struct page **user_pages;
384 int user_invalidated;
Alex Deucher97b2e202015-04-20 16:51:00 -0400385};
386
387struct amdgpu_bo_va_mapping {
388 struct list_head list;
Christian Königa9f87f62017-03-30 14:03:59 +0200389 struct rb_node rb;
390 uint64_t start;
391 uint64_t last;
392 uint64_t __subtree_last;
Alex Deucher97b2e202015-04-20 16:51:00 -0400393 uint64_t offset;
Christian König268c3002017-01-18 14:49:43 +0100394 uint64_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400395};
396
397/* bo virtual addresses in a specific vm */
398struct amdgpu_bo_va {
399 /* protected by bo being reserved */
400 struct list_head bo_list;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100401 struct dma_fence *last_pt_update;
Alex Deucher97b2e202015-04-20 16:51:00 -0400402 unsigned ref_count;
403
Christian König7fc11952015-07-30 11:53:42 +0200404 /* protected by vm mutex and spinlock */
Alex Deucher97b2e202015-04-20 16:51:00 -0400405 struct list_head vm_status;
406
Christian König7fc11952015-07-30 11:53:42 +0200407 /* mappings for this bo_va */
408 struct list_head invalids;
409 struct list_head valids;
410
Alex Deucher97b2e202015-04-20 16:51:00 -0400411 /* constant after initialization */
412 struct amdgpu_vm *vm;
413 struct amdgpu_bo *bo;
414};
415
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800416#define AMDGPU_GEM_DOMAIN_MAX 0x3
417
Alex Deucher97b2e202015-04-20 16:51:00 -0400418struct amdgpu_bo {
Alex Deucher97b2e202015-04-20 16:51:00 -0400419 /* Protected by tbo.reserved */
Christian König1ea863f2015-12-18 22:13:12 +0100420 u32 prefered_domains;
421 u32 allowed_domains;
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800422 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400423 struct ttm_placement placement;
424 struct ttm_buffer_object tbo;
425 struct ttm_bo_kmap_obj kmap;
426 u64 flags;
427 unsigned pin_count;
Alex Deucher97b2e202015-04-20 16:51:00 -0400428 u64 tiling_flags;
429 u64 metadata_flags;
430 void *metadata;
431 u32 metadata_size;
Mario Kleiner8e94a462016-11-09 02:25:15 +0100432 unsigned prime_shared_count;
Alex Deucher97b2e202015-04-20 16:51:00 -0400433 /* list of all virtual address to which this bo
434 * is associated to
435 */
436 struct list_head va;
437 /* Constant after initialization */
Alex Deucher97b2e202015-04-20 16:51:00 -0400438 struct drm_gem_object gem_base;
Christian König82b9c552015-11-27 16:49:00 +0100439 struct amdgpu_bo *parent;
Chunming Zhoue7893c42016-07-26 14:13:21 +0800440 struct amdgpu_bo *shadow;
Alex Deucher97b2e202015-04-20 16:51:00 -0400441
442 struct ttm_bo_kmap_obj dma_buf_vmap;
Alex Deucher97b2e202015-04-20 16:51:00 -0400443 struct amdgpu_mn *mn;
444 struct list_head mn_list;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +0800445 struct list_head shadow_list;
Alex Deucher97b2e202015-04-20 16:51:00 -0400446};
447#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
448
449void amdgpu_gem_object_free(struct drm_gem_object *obj);
450int amdgpu_gem_object_open(struct drm_gem_object *obj,
451 struct drm_file *file_priv);
452void amdgpu_gem_object_close(struct drm_gem_object *obj,
453 struct drm_file *file_priv);
454unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
455struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
Christian König4d9c5142016-05-03 18:46:19 +0200456struct drm_gem_object *
457amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
458 struct dma_buf_attachment *attach,
459 struct sg_table *sg);
Alex Deucher97b2e202015-04-20 16:51:00 -0400460struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
461 struct drm_gem_object *gobj,
462 int flags);
463int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
464void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
465struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
466void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
467void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
468int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
469
470/* sub-allocation manager, it has to be protected by another lock.
471 * By conception this is an helper for other part of the driver
472 * like the indirect buffer or semaphore, which both have their
473 * locking.
474 *
475 * Principe is simple, we keep a list of sub allocation in offset
476 * order (first entry has offset == 0, last entry has the highest
477 * offset).
478 *
479 * When allocating new object we first check if there is room at
480 * the end total_size - (last_object_offset + last_object_size) >=
481 * alloc_size. If so we allocate new object there.
482 *
483 * When there is not enough room at the end, we start waiting for
484 * each sub object until we reach object_offset+object_size >=
485 * alloc_size, this object then become the sub object we return.
486 *
487 * Alignment can't be bigger than page size.
488 *
489 * Hole are not considered for allocation to keep things simple.
490 * Assumption is that there won't be hole (all object on same
491 * alignment).
492 */
Christian König6ba60b82016-03-11 14:50:08 +0100493
494#define AMDGPU_SA_NUM_FENCE_LISTS 32
495
Alex Deucher97b2e202015-04-20 16:51:00 -0400496struct amdgpu_sa_manager {
497 wait_queue_head_t wq;
498 struct amdgpu_bo *bo;
499 struct list_head *hole;
Christian König6ba60b82016-03-11 14:50:08 +0100500 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
Alex Deucher97b2e202015-04-20 16:51:00 -0400501 struct list_head olist;
502 unsigned size;
503 uint64_t gpu_addr;
504 void *cpu_ptr;
505 uint32_t domain;
506 uint32_t align;
507};
508
Alex Deucher97b2e202015-04-20 16:51:00 -0400509/* sub-allocation buffer */
510struct amdgpu_sa_bo {
511 struct list_head olist;
512 struct list_head flist;
513 struct amdgpu_sa_manager *manager;
514 unsigned soffset;
515 unsigned eoffset;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100516 struct dma_fence *fence;
Alex Deucher97b2e202015-04-20 16:51:00 -0400517};
518
519/*
520 * GEM objects.
521 */
Christian König418aa0c2016-02-15 16:59:57 +0100522void amdgpu_gem_force_release(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400523int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
524 int alignment, u32 initial_domain,
525 u64 flags, bool kernel,
526 struct drm_gem_object **obj);
527
528int amdgpu_mode_dumb_create(struct drm_file *file_priv,
529 struct drm_device *dev,
530 struct drm_mode_create_dumb *args);
531int amdgpu_mode_dumb_mmap(struct drm_file *filp,
532 struct drm_device *dev,
533 uint32_t handle, uint64_t *offset_p);
Rex Zhud573de22016-05-12 13:27:28 +0800534int amdgpu_fence_slab_init(void);
535void amdgpu_fence_slab_fini(void);
Alex Deucher97b2e202015-04-20 16:51:00 -0400536
537/*
Alex Xiee60f8db2017-03-09 11:36:26 -0500538 * VMHUB structures, functions & helpers
539 */
540struct amdgpu_vmhub {
541 uint32_t ctx0_ptb_addr_lo32;
542 uint32_t ctx0_ptb_addr_hi32;
543 uint32_t vm_inv_eng0_req;
544 uint32_t vm_inv_eng0_ack;
545 uint32_t vm_context0_cntl;
546 uint32_t vm_l2_pro_fault_status;
547 uint32_t vm_l2_pro_fault_cntl;
Alex Xiee60f8db2017-03-09 11:36:26 -0500548};
549
550/*
Alex Deucher97b2e202015-04-20 16:51:00 -0400551 * GPU MC structures, functions & helpers
552 */
553struct amdgpu_mc {
554 resource_size_t aper_size;
555 resource_size_t aper_base;
556 resource_size_t agp_base;
557 /* for some chips with <= 32MB we need to lie
558 * about vram size near mc fb location */
559 u64 mc_vram_size;
560 u64 visible_vram_size;
Christian König6f02a692017-07-07 11:56:59 +0200561 u64 gart_size;
562 u64 gart_start;
563 u64 gart_end;
Alex Deucher97b2e202015-04-20 16:51:00 -0400564 u64 vram_start;
565 u64 vram_end;
566 unsigned vram_width;
567 u64 real_vram_size;
568 int vram_mtrr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400569 u64 mc_mask;
570 const struct firmware *fw; /* MC firmware */
571 uint32_t fw_version;
572 struct amdgpu_irq_src vm_fault;
Ken Wang81c59f52015-06-03 21:02:01 +0800573 uint32_t vram_type;
Chunming Zhou50b01972016-07-18 16:59:24 +0800574 uint32_t srbm_soft_reset;
Christian Königf7c35ab2017-01-27 11:56:05 +0100575 bool prt_warning;
Huang Rui916910a2017-05-31 10:35:42 +0800576 uint64_t stolen_size;
Junwei Zhang8fe73322016-03-10 14:20:39 +0800577 /* apertures */
578 u64 shared_aperture_start;
579 u64 shared_aperture_end;
580 u64 private_aperture_start;
581 u64 private_aperture_end;
Alex Xiee60f8db2017-03-09 11:36:26 -0500582 /* protects concurrent invalidation */
583 spinlock_t invalidate_lock;
Alex Deucher97b2e202015-04-20 16:51:00 -0400584};
585
586/*
587 * GPU doorbell structures, functions & helpers
588 */
589typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
590{
591 AMDGPU_DOORBELL_KIQ = 0x000,
592 AMDGPU_DOORBELL_HIQ = 0x001,
593 AMDGPU_DOORBELL_DIQ = 0x002,
594 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
595 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
596 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
597 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
598 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
599 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
600 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
601 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
602 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
603 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
604 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
605 AMDGPU_DOORBELL_IH = 0x1E8,
606 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
607 AMDGPU_DOORBELL_INVALID = 0xFFFF
608} AMDGPU_DOORBELL_ASSIGNMENT;
609
610struct amdgpu_doorbell {
611 /* doorbell mmio */
612 resource_size_t base;
613 resource_size_t size;
614 u32 __iomem *ptr;
615 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
616};
617
Ken Wang39807b92016-03-18 15:41:42 +0800618/*
619 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
620 */
621typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
622{
623 /*
624 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
625 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
626 * Compute related doorbells are allocated from 0x00 to 0x8a
627 */
628
629
630 /* kernel scheduling */
631 AMDGPU_DOORBELL64_KIQ = 0x00,
632
633 /* HSA interface queue and debug queue */
634 AMDGPU_DOORBELL64_HIQ = 0x01,
635 AMDGPU_DOORBELL64_DIQ = 0x02,
636
637 /* Compute engines */
638 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
639 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
640 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
641 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
642 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
643 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
644 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
645 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
646
647 /* User queue doorbell range (128 doorbells) */
648 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
649 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
650
651 /* Graphics engine */
652 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
653
654 /*
655 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
656 * Graphics voltage island aperture 1
657 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
658 */
659
660 /* sDMA engines */
661 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
662 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
663 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
664 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
665
666 /* Interrupt handler */
667 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
668 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
669 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
670
Monk Liue6b3ecb2016-12-30 16:18:56 +0800671 /* VCN engine use 32 bits doorbell */
672 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
673 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
674 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
675 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
676
677 /* overlap the doorbell assignment with VCN as they are mutually exclusive
678 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
679 */
Frank Min4ed11d72017-06-12 10:57:43 +0800680 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
681 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
682 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
683 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
Monk Liue6b3ecb2016-12-30 16:18:56 +0800684
Frank Min4ed11d72017-06-12 10:57:43 +0800685 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
686 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
687 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
688 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
Ken Wang39807b92016-03-18 15:41:42 +0800689
690 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
691 AMDGPU_DOORBELL64_INVALID = 0xFFFF
692} AMDGPU_DOORBELL64_ASSIGNMENT;
693
694
Alex Deucher97b2e202015-04-20 16:51:00 -0400695void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
696 phys_addr_t *aperture_base,
697 size_t *aperture_size,
698 size_t *start_offset);
699
700/*
701 * IRQS.
702 */
703
704struct amdgpu_flip_work {
Michel Dänzer325cbba2016-08-04 12:39:37 +0900705 struct delayed_work flip_work;
Alex Deucher97b2e202015-04-20 16:51:00 -0400706 struct work_struct unpin_work;
707 struct amdgpu_device *adev;
708 int crtc_id;
Michel Dänzer325cbba2016-08-04 12:39:37 +0900709 u32 target_vblank;
Alex Deucher97b2e202015-04-20 16:51:00 -0400710 uint64_t base;
711 struct drm_pending_vblank_event *event;
Christian König765e7fb2016-09-15 15:06:50 +0200712 struct amdgpu_bo *old_abo;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100713 struct dma_fence *excl;
Christian König1ffd2652015-08-11 17:29:52 +0200714 unsigned shared_count;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100715 struct dma_fence **shared;
716 struct dma_fence_cb cb;
Alex Deuchercb9e59d2016-05-05 16:03:57 -0400717 bool async;
Alex Deucher97b2e202015-04-20 16:51:00 -0400718};
719
720
721/*
722 * CP & rings.
723 */
724
725struct amdgpu_ib {
726 struct amdgpu_sa_bo *sa_bo;
727 uint32_t length_dw;
728 uint64_t gpu_addr;
729 uint32_t *ptr;
Jammy Zhoude807f82015-05-11 23:41:41 +0800730 uint32_t flags;
Alex Deucher97b2e202015-04-20 16:51:00 -0400731};
732
Nils Wallménius62250a92016-04-10 16:30:00 +0200733extern const struct amd_sched_backend_ops amdgpu_sched_ops;
Chunming Zhouc1b69ed2015-07-21 13:45:14 +0800734
Christian König50838c82016-02-03 13:44:52 +0100735int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
Monk Liuc5637832016-04-19 20:11:32 +0800736 struct amdgpu_job **job, struct amdgpu_vm *vm);
Christian Königd71518b2016-02-01 12:20:25 +0100737int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
738 struct amdgpu_job **job);
Monk Liub6723c82016-03-10 12:14:44 +0800739
Christian Königa5fb4ec2016-06-29 15:10:31 +0200740void amdgpu_job_free_resources(struct amdgpu_job *job);
Christian König50838c82016-02-03 13:44:52 +0100741void amdgpu_job_free(struct amdgpu_job *job);
Christian Königd71518b2016-02-01 12:20:25 +0100742int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
Christian König2bd9ccf2016-02-01 12:53:58 +0100743 struct amd_sched_entity *entity, void *owner,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100744 struct dma_fence **f);
Christian König8b4fb002015-11-15 16:04:16 +0100745
Alex Deucher97b2e202015-04-20 16:51:00 -0400746/*
Andres Rodriguezeffd9242017-02-16 00:47:32 -0500747 * Queue manager
748 */
749struct amdgpu_queue_mapper {
750 int hw_ip;
751 struct mutex lock;
752 /* protected by lock */
753 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
754};
755
756struct amdgpu_queue_mgr {
757 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
758};
759
760int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
761 struct amdgpu_queue_mgr *mgr);
762int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
763 struct amdgpu_queue_mgr *mgr);
764int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
765 struct amdgpu_queue_mgr *mgr,
766 int hw_ip, int instance, int ring,
767 struct amdgpu_ring **out_ring);
768
769/*
Alex Deucher97b2e202015-04-20 16:51:00 -0400770 * context related structures
771 */
772
Christian König21c16bf2015-07-07 17:24:49 +0200773struct amdgpu_ctx_ring {
Christian König91404fb2015-08-05 18:33:21 +0200774 uint64_t sequence;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100775 struct dma_fence **fences;
Christian König91404fb2015-08-05 18:33:21 +0200776 struct amd_sched_entity entity;
Christian König21c16bf2015-07-07 17:24:49 +0200777};
778
Alex Deucher97b2e202015-04-20 16:51:00 -0400779struct amdgpu_ctx {
Alex Deucher0b492a42015-08-16 22:48:26 -0400780 struct kref refcount;
Chunming Zhou9cb7e5a2015-07-21 13:17:19 +0800781 struct amdgpu_device *adev;
Andres Rodriguezeffd9242017-02-16 00:47:32 -0500782 struct amdgpu_queue_mgr queue_mgr;
Alex Deucher0b492a42015-08-16 22:48:26 -0400783 unsigned reset_counter;
Christian König21c16bf2015-07-07 17:24:49 +0200784 spinlock_t ring_lock;
Chris Wilsonf54d1862016-10-25 13:00:45 +0100785 struct dma_fence **fences;
Christian König21c16bf2015-07-07 17:24:49 +0200786 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
Monk Liu753ad492016-08-26 13:28:28 +0800787 bool preamble_presented;
Alex Deucher97b2e202015-04-20 16:51:00 -0400788};
789
790struct amdgpu_ctx_mgr {
Alex Deucher0b492a42015-08-16 22:48:26 -0400791 struct amdgpu_device *adev;
792 struct mutex lock;
793 /* protected by lock */
794 struct idr ctx_handles;
Alex Deucher97b2e202015-04-20 16:51:00 -0400795};
796
Alex Deucher0b492a42015-08-16 22:48:26 -0400797struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
798int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
799
Christian König21c16bf2015-07-07 17:24:49 +0200800uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
Chris Wilsonf54d1862016-10-25 13:00:45 +0100801 struct dma_fence *fence);
802struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
Christian König21c16bf2015-07-07 17:24:49 +0200803 struct amdgpu_ring *ring, uint64_t seq);
804
Alex Deucher0b492a42015-08-16 22:48:26 -0400805int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
806 struct drm_file *filp);
807
Christian Königefd4ccb2015-08-04 16:20:31 +0200808void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
809void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
Alex Deucher0b492a42015-08-16 22:48:26 -0400810
Alex Deucher97b2e202015-04-20 16:51:00 -0400811/*
812 * file private structure
813 */
814
815struct amdgpu_fpriv {
816 struct amdgpu_vm vm;
Junwei Zhangb85891b2017-01-16 13:59:01 +0800817 struct amdgpu_bo_va *prt_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400818 struct mutex bo_list_lock;
819 struct idr bo_list_handles;
Alex Deucher0b492a42015-08-16 22:48:26 -0400820 struct amdgpu_ctx_mgr ctx_mgr;
Chunming Zhouf1892132017-05-15 16:48:27 +0800821 u32 vram_lost_counter;
Alex Deucher97b2e202015-04-20 16:51:00 -0400822};
823
824/*
825 * residency list
826 */
827
828struct amdgpu_bo_list {
829 struct mutex lock;
Alex Xie5ac55622017-06-16 09:07:29 -0400830 struct rcu_head rhead;
831 struct kref refcount;
Alex Deucher97b2e202015-04-20 16:51:00 -0400832 struct amdgpu_bo *gds_obj;
833 struct amdgpu_bo *gws_obj;
834 struct amdgpu_bo *oa_obj;
Christian König211dff52016-02-22 15:40:59 +0100835 unsigned first_userptr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400836 unsigned num_entries;
837 struct amdgpu_bo_list_entry *array;
838};
839
840struct amdgpu_bo_list *
841amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
Christian König636ce252015-12-18 21:26:47 +0100842void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
843 struct list_head *validated);
Alex Deucher97b2e202015-04-20 16:51:00 -0400844void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
845void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
846
847/*
848 * GFX stuff
849 */
850#include "clearstate_defs.h"
851
Alex Deucher79e54122016-04-08 15:45:13 -0400852struct amdgpu_rlc_funcs {
853 void (*enter_safe_mode)(struct amdgpu_device *adev);
854 void (*exit_safe_mode)(struct amdgpu_device *adev);
855};
856
Alex Deucher97b2e202015-04-20 16:51:00 -0400857struct amdgpu_rlc {
858 /* for power gating */
859 struct amdgpu_bo *save_restore_obj;
860 uint64_t save_restore_gpu_addr;
861 volatile uint32_t *sr_ptr;
862 const u32 *reg_list;
863 u32 reg_list_size;
864 /* for clear state */
865 struct amdgpu_bo *clear_state_obj;
866 uint64_t clear_state_gpu_addr;
867 volatile uint32_t *cs_ptr;
868 const struct cs_section_def *cs_data;
869 u32 clear_state_size;
870 /* for cp tables */
871 struct amdgpu_bo *cp_table_obj;
872 uint64_t cp_table_gpu_addr;
873 volatile uint32_t *cp_table_ptr;
874 u32 cp_table_size;
Alex Deucher79e54122016-04-08 15:45:13 -0400875
876 /* safe mode for updating CG/PG state */
877 bool in_safe_mode;
878 const struct amdgpu_rlc_funcs *funcs;
Eric Huang2b6cd972016-04-14 17:26:07 -0400879
880 /* for firmware data */
881 u32 save_and_restore_offset;
882 u32 clear_state_descriptor_offset;
883 u32 avail_scratch_ram_locations;
884 u32 reg_restore_list_size;
885 u32 reg_list_format_start;
886 u32 reg_list_format_separate_start;
887 u32 starting_offsets_start;
888 u32 reg_list_format_size_bytes;
889 u32 reg_list_size_bytes;
890
891 u32 *register_list_format;
892 u32 *register_restore;
Alex Deucher97b2e202015-04-20 16:51:00 -0400893};
894
Andres Rodriguez78c16832017-02-02 00:38:22 -0500895#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
896
Alex Deucher97b2e202015-04-20 16:51:00 -0400897struct amdgpu_mec {
898 struct amdgpu_bo *hpd_eop_obj;
899 u64 hpd_eop_gpu_addr;
Ken Wangb1023572017-03-03 17:59:39 -0500900 struct amdgpu_bo *mec_fw_obj;
901 u64 mec_fw_gpu_addr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400902 u32 num_mec;
Andres Rodriguez42794b22017-02-01 19:08:23 -0500903 u32 num_pipe_per_mec;
904 u32 num_queue_per_pipe;
Xiangliang Yu59a82d72017-02-17 16:03:10 +0800905 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
Andres Rodriguez78c16832017-02-02 00:38:22 -0500906
907 /* These are the resources for which amdgpu takes ownership */
908 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
Alex Deucher97b2e202015-04-20 16:51:00 -0400909};
910
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800911struct amdgpu_kiq {
912 u64 eop_gpu_addr;
913 struct amdgpu_bo *eop_obj;
Shaoyun Liucdf6adb2017-04-28 17:18:26 -0400914 struct mutex ring_mutex;
Xiangliang Yu4e638ae2016-12-23 15:00:01 +0800915 struct amdgpu_ring ring;
916 struct amdgpu_irq_src irq;
917};
918
Alex Deucher97b2e202015-04-20 16:51:00 -0400919/*
920 * GPU scratch registers structures, functions & helpers
921 */
922struct amdgpu_scratch {
923 unsigned num_reg;
924 uint32_t reg_base;
Nils Wallménius50261152017-01-16 21:56:48 +0100925 uint32_t free_mask;
Alex Deucher97b2e202015-04-20 16:51:00 -0400926};
927
928/*
929 * GFX configurations
930 */
Alex Deuchere3fa7632016-10-10 10:56:21 -0400931#define AMDGPU_GFX_MAX_SE 4
932#define AMDGPU_GFX_MAX_SH_PER_SE 2
933
934struct amdgpu_rb_config {
935 uint32_t rb_backend_disable;
936 uint32_t user_rb_backend_disable;
937 uint32_t raster_config;
938 uint32_t raster_config_1;
939};
940
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500941struct gb_addr_config {
942 uint16_t pipe_interleave_size;
943 uint8_t num_pipes;
944 uint8_t max_compress_frags;
945 uint8_t num_banks;
946 uint8_t num_se;
947 uint8_t num_rb_per_se;
948};
949
Junwei Zhangea323f82017-02-21 10:32:37 +0800950struct amdgpu_gfx_config {
Alex Deucher97b2e202015-04-20 16:51:00 -0400951 unsigned max_shader_engines;
952 unsigned max_tile_pipes;
953 unsigned max_cu_per_sh;
954 unsigned max_sh_per_se;
955 unsigned max_backends_per_se;
956 unsigned max_texture_channel_caches;
957 unsigned max_gprs;
958 unsigned max_gs_threads;
959 unsigned max_hw_contexts;
960 unsigned sc_prim_fifo_size_frontend;
961 unsigned sc_prim_fifo_size_backend;
962 unsigned sc_hiz_tile_fifo_size;
963 unsigned sc_earlyz_tile_fifo_size;
964
965 unsigned num_tile_pipes;
966 unsigned backend_enable_mask;
967 unsigned mem_max_burst_length_bytes;
968 unsigned mem_row_size_in_kb;
969 unsigned shader_engine_tile_size;
970 unsigned num_gpus;
971 unsigned multi_gpu_tile_size;
972 unsigned mc_arb_ramcfg;
973 unsigned gb_addr_config;
Alex Deucher8f8e00c2016-02-12 00:39:13 -0500974 unsigned num_rbs;
Junwei Zhang408bfe72017-04-27 11:12:07 +0800975 unsigned gs_vgt_table_depth;
976 unsigned gs_prim_buffer_depth;
Alex Deucher97b2e202015-04-20 16:51:00 -0400977
978 uint32_t tile_mode_array[32];
979 uint32_t macrotile_mode_array[16];
Alex Deuchere3fa7632016-10-10 10:56:21 -0400980
Andrey Grodzovskyd0e95752016-12-12 13:40:37 -0500981 struct gb_addr_config gb_addr_config_fields;
Alex Deuchere3fa7632016-10-10 10:56:21 -0400982 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
Junwei Zhangdf6e2c42017-02-17 11:05:49 +0800983
984 /* gfx configure feature */
985 uint32_t double_offchip_lds_buf;
Alex Deucher97b2e202015-04-20 16:51:00 -0400986};
987
Alex Deucher7dae69a2016-05-03 16:25:53 -0400988struct amdgpu_cu_info {
Hawking Zhang51fd0372017-06-09 22:30:52 +0800989 uint32_t max_waves_per_simd;
Junwei Zhang408bfe72017-04-27 11:12:07 +0800990 uint32_t wave_front_size;
Hawking Zhang51fd0372017-06-09 22:30:52 +0800991 uint32_t max_scratch_slots_per_cu;
992 uint32_t lds_size;
Flora Cuidbfe85e2017-06-20 11:08:35 +0800993
994 /* total active CU number */
995 uint32_t number;
996 uint32_t ao_cu_mask;
997 uint32_t ao_cu_bitmap[4][4];
Alex Deucher7dae69a2016-05-03 16:25:53 -0400998 uint32_t bitmap[4][4];
999};
1000
Alex Deucherb95e31f2016-07-07 15:01:42 -04001001struct amdgpu_gfx_funcs {
1002 /* get the gpu clock counter */
1003 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
Tom St Denis9559ef52016-06-28 10:26:48 -04001004 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
Tom St Denis472259f2016-10-14 09:49:09 -04001005 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
Tom St Denisc5a60ce2016-12-05 11:39:19 -05001006 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
1007 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
Alex Deucherb95e31f2016-07-07 15:01:42 -04001008};
1009
Alex Deucherbce23e02017-03-28 12:52:08 -04001010struct amdgpu_ngg_buf {
1011 struct amdgpu_bo *bo;
1012 uint64_t gpu_addr;
1013 uint32_t size;
1014 uint32_t bo_size;
1015};
1016
1017enum {
Guenter Roeckaf8baf12017-05-03 23:49:18 -07001018 NGG_PRIM = 0,
1019 NGG_POS,
1020 NGG_CNTL,
1021 NGG_PARAM,
Alex Deucherbce23e02017-03-28 12:52:08 -04001022 NGG_BUF_MAX
1023};
1024
1025struct amdgpu_ngg {
1026 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1027 uint32_t gds_reserve_addr;
1028 uint32_t gds_reserve_size;
1029 bool init;
1030};
1031
Alex Deucher97b2e202015-04-20 16:51:00 -04001032struct amdgpu_gfx {
1033 struct mutex gpu_clock_mutex;
Junwei Zhangea323f82017-02-21 10:32:37 +08001034 struct amdgpu_gfx_config config;
Alex Deucher97b2e202015-04-20 16:51:00 -04001035 struct amdgpu_rlc rlc;
1036 struct amdgpu_mec mec;
Xiangliang Yu4e638ae2016-12-23 15:00:01 +08001037 struct amdgpu_kiq kiq;
Alex Deucher97b2e202015-04-20 16:51:00 -04001038 struct amdgpu_scratch scratch;
1039 const struct firmware *me_fw; /* ME firmware */
1040 uint32_t me_fw_version;
1041 const struct firmware *pfp_fw; /* PFP firmware */
1042 uint32_t pfp_fw_version;
1043 const struct firmware *ce_fw; /* CE firmware */
1044 uint32_t ce_fw_version;
1045 const struct firmware *rlc_fw; /* RLC firmware */
1046 uint32_t rlc_fw_version;
1047 const struct firmware *mec_fw; /* MEC firmware */
1048 uint32_t mec_fw_version;
1049 const struct firmware *mec2_fw; /* MEC2 firmware */
1050 uint32_t mec2_fw_version;
Ken Wang02558a02015-06-03 19:52:06 +08001051 uint32_t me_feature_version;
1052 uint32_t ce_feature_version;
1053 uint32_t pfp_feature_version;
Jammy Zhou351643d2015-08-04 10:43:50 +08001054 uint32_t rlc_feature_version;
1055 uint32_t mec_feature_version;
1056 uint32_t mec2_feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001057 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1058 unsigned num_gfx_rings;
1059 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1060 unsigned num_compute_rings;
1061 struct amdgpu_irq_src eop_irq;
1062 struct amdgpu_irq_src priv_reg_irq;
1063 struct amdgpu_irq_src priv_inst_irq;
1064 /* gfx status */
Alex Deucher7dae69a2016-05-03 16:25:53 -04001065 uint32_t gfx_current_status;
Ken Wanga101a892015-06-03 17:47:54 +08001066 /* ce ram size*/
Alex Deucher7dae69a2016-05-03 16:25:53 -04001067 unsigned ce_ram_size;
1068 struct amdgpu_cu_info cu_info;
Alex Deucherb95e31f2016-07-07 15:01:42 -04001069 const struct amdgpu_gfx_funcs *funcs;
Chunming Zhou3d7c6382016-07-15 11:28:30 +08001070
1071 /* reset mask */
1072 uint32_t grbm_soft_reset;
1073 uint32_t srbm_soft_reset;
Monk Liu223049c2017-01-26 15:32:16 +08001074 bool in_reset;
David Panaritib4e40672017-03-28 12:57:31 -04001075 /* s3/s4 mask */
1076 bool in_suspend;
Alex Deucherbce23e02017-03-28 12:52:08 -04001077 /* NGG */
1078 struct amdgpu_ngg ngg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001079};
1080
Christian Königb07c60c2016-01-31 12:29:04 +01001081int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
Alex Deucher97b2e202015-04-20 16:51:00 -04001082 unsigned size, struct amdgpu_ib *ib);
Christian König4d9c5142016-05-03 18:46:19 +02001083void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
Chris Wilsonf54d1862016-10-25 13:00:45 +01001084 struct dma_fence *f);
Christian Königb07c60c2016-01-31 12:29:04 +01001085int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
Junwei Zhang50ddc752017-01-23 16:30:38 +08001086 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1087 struct dma_fence **f);
Alex Deucher97b2e202015-04-20 16:51:00 -04001088int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1089void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1090int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001091
1092/*
1093 * CS.
1094 */
1095struct amdgpu_cs_chunk {
1096 uint32_t chunk_id;
1097 uint32_t length_dw;
Christian König758ac172016-05-06 22:14:00 +02001098 void *kdata;
Alex Deucher97b2e202015-04-20 16:51:00 -04001099};
1100
1101struct amdgpu_cs_parser {
1102 struct amdgpu_device *adev;
1103 struct drm_file *filp;
Christian König3cb485f2015-05-11 15:34:59 +02001104 struct amdgpu_ctx *ctx;
Christian Königc3cca412015-12-15 14:41:33 +01001105
Alex Deucher97b2e202015-04-20 16:51:00 -04001106 /* chunks */
1107 unsigned nchunks;
1108 struct amdgpu_cs_chunk *chunks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001109
Christian König50838c82016-02-03 13:44:52 +01001110 /* scheduler job object */
1111 struct amdgpu_job *job;
Alex Deucher97b2e202015-04-20 16:51:00 -04001112
Christian Königc3cca412015-12-15 14:41:33 +01001113 /* buffer objects */
1114 struct ww_acquire_ctx ticket;
1115 struct amdgpu_bo_list *bo_list;
1116 struct amdgpu_bo_list_entry vm_pd;
1117 struct list_head validated;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001118 struct dma_fence *fence;
Christian Königc3cca412015-12-15 14:41:33 +01001119 uint64_t bytes_moved_threshold;
John Brooks00f06b22017-06-27 22:33:18 -04001120 uint64_t bytes_moved_vis_threshold;
Christian Königc3cca412015-12-15 14:41:33 +01001121 uint64_t bytes_moved;
John Brooks00f06b22017-06-27 22:33:18 -04001122 uint64_t bytes_moved_vis;
Christian König662bfa62016-09-01 12:13:18 +02001123 struct amdgpu_bo_list_entry *evictable;
Alex Deucher97b2e202015-04-20 16:51:00 -04001124
1125 /* user fence */
Christian König91acbeb2015-12-14 16:42:31 +01001126 struct amdgpu_bo_list_entry uf_entry;
Dave Airlie660e8552017-03-13 22:18:15 +00001127
1128 unsigned num_post_dep_syncobjs;
1129 struct drm_syncobj **post_dep_syncobjs;
Alex Deucher97b2e202015-04-20 16:51:00 -04001130};
1131
Monk Liu753ad492016-08-26 13:28:28 +08001132#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1133#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1134#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1135
Chunming Zhoubb977d32015-08-18 15:16:40 +08001136struct amdgpu_job {
1137 struct amd_sched_job base;
1138 struct amdgpu_device *adev;
Christian Königedf600d2016-05-03 15:54:54 +02001139 struct amdgpu_vm *vm;
Christian Königb07c60c2016-01-31 12:29:04 +01001140 struct amdgpu_ring *ring;
Christian Könige86f9ce2016-02-08 12:13:05 +01001141 struct amdgpu_sync sync;
Chunming Zhoua340c7b2017-05-18 15:19:03 +08001142 struct amdgpu_sync dep_sync;
Chunming Zhoudf83d1e2017-05-09 15:50:22 +08001143 struct amdgpu_sync sched_sync;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001144 struct amdgpu_ib *ibs;
Chris Wilsonf54d1862016-10-25 13:00:45 +01001145 struct dma_fence *fence; /* the hw fence */
Monk Liu753ad492016-08-26 13:28:28 +08001146 uint32_t preamble_status;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001147 uint32_t num_ibs;
Christian Könige2840222015-11-05 19:49:48 +01001148 void *owner;
Monk Liu3aecd242016-08-25 15:40:48 +08001149 uint64_t fence_ctx; /* the fence_context this job uses */
Chunming Zhoufd53be32016-07-01 17:59:01 +08001150 bool vm_needs_flush;
Christian Königd88bf582016-05-06 17:50:03 +02001151 unsigned vm_id;
1152 uint64_t vm_pd_addr;
1153 uint32_t gds_base, gds_size;
1154 uint32_t gws_base, gws_size;
1155 uint32_t oa_base, oa_size;
Christian König758ac172016-05-06 22:14:00 +02001156
1157 /* user fence handling */
Christian Königb5f5acb2016-06-29 13:26:41 +02001158 uint64_t uf_addr;
Christian König758ac172016-05-06 22:14:00 +02001159 uint64_t uf_sequence;
1160
Chunming Zhoubb977d32015-08-18 15:16:40 +08001161};
Junwei Zhanga6db8a32015-09-09 09:21:19 +08001162#define to_amdgpu_job(sched_job) \
1163 container_of((sched_job), struct amdgpu_job, base)
Chunming Zhoubb977d32015-08-18 15:16:40 +08001164
Christian König7270f832016-01-31 11:00:41 +01001165static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1166 uint32_t ib_idx, int idx)
Alex Deucher97b2e202015-04-20 16:51:00 -04001167{
Christian König50838c82016-02-03 13:44:52 +01001168 return p->job->ibs[ib_idx].ptr[idx];
Alex Deucher97b2e202015-04-20 16:51:00 -04001169}
1170
Christian König7270f832016-01-31 11:00:41 +01001171static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1172 uint32_t ib_idx, int idx,
1173 uint32_t value)
1174{
Christian König50838c82016-02-03 13:44:52 +01001175 p->job->ibs[ib_idx].ptr[idx] = value;
Christian König7270f832016-01-31 11:00:41 +01001176}
1177
Alex Deucher97b2e202015-04-20 16:51:00 -04001178/*
1179 * Writeback
1180 */
1181#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1182
1183struct amdgpu_wb {
1184 struct amdgpu_bo *wb_obj;
1185 volatile uint32_t *wb;
1186 uint64_t gpu_addr;
1187 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1188 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1189};
1190
1191int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1192void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
Ken Wang70142852016-03-18 15:08:49 +08001193int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
Monk Liu0915fdb2017-06-19 10:19:41 -04001194int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb);
Ken Wang70142852016-03-18 15:08:49 +08001195void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
Monk Liu0915fdb2017-06-19 10:19:41 -04001196void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb);
Alex Deucher97b2e202015-04-20 16:51:00 -04001197
Alex Deucherd0dd7f02015-11-11 19:45:06 -05001198void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1199
Alex Deucher97b2e202015-04-20 16:51:00 -04001200/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001201 * SDMA
1202 */
Alex Deucherc113ea12015-10-08 16:30:37 -04001203struct amdgpu_sdma_instance {
Alex Deucher97b2e202015-04-20 16:51:00 -04001204 /* SDMA firmware */
1205 const struct firmware *fw;
1206 uint32_t fw_version;
Jammy Zhoucfa21042015-08-04 10:50:47 +08001207 uint32_t feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001208
1209 struct amdgpu_ring ring;
Jammy Zhou18111de2015-08-31 14:06:39 +08001210 bool burst_nop;
Frank Min51668b02017-06-28 20:02:04 +08001211 uint32_t poll_mem_offs;
Alex Deucher97b2e202015-04-20 16:51:00 -04001212};
1213
Alex Deucherc113ea12015-10-08 16:30:37 -04001214struct amdgpu_sdma {
1215 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
Ken Wang30d15742016-01-19 14:05:23 +08001216#ifdef CONFIG_DRM_AMDGPU_SI
1217 //SI DMA has a difference trap irq number for the second engine
1218 struct amdgpu_irq_src trap_irq_1;
1219#endif
Alex Deucherc113ea12015-10-08 16:30:37 -04001220 struct amdgpu_irq_src trap_irq;
1221 struct amdgpu_irq_src illegal_inst_irq;
Christian Königedf600d2016-05-03 15:54:54 +02001222 int num_instances;
Chunming Zhoue702a682016-07-13 10:28:56 +08001223 uint32_t srbm_soft_reset;
Alex Deucherc113ea12015-10-08 16:30:37 -04001224};
1225
Alex Deucher97b2e202015-04-20 16:51:00 -04001226/*
1227 * Firmware
1228 */
Huang Ruie635ee02016-11-01 15:35:38 +08001229enum amdgpu_firmware_load_type {
1230 AMDGPU_FW_LOAD_DIRECT = 0,
1231 AMDGPU_FW_LOAD_SMU,
1232 AMDGPU_FW_LOAD_PSP,
1233};
1234
Alex Deucher97b2e202015-04-20 16:51:00 -04001235struct amdgpu_firmware {
1236 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
Huang Ruie635ee02016-11-01 15:35:38 +08001237 enum amdgpu_firmware_load_type load_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001238 struct amdgpu_bo *fw_buf;
1239 unsigned int fw_size;
Huang Rui2445b222017-03-03 16:20:35 -05001240 unsigned int max_ucodes;
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001241 /* firmwares are loaded by psp instead of smu from vega10 */
1242 const struct amdgpu_psp_funcs *funcs;
1243 struct amdgpu_bo *rbuf;
1244 struct mutex mutex;
Huang Ruiab4fe3e2017-06-05 22:11:59 +08001245
1246 /* gpu info firmware data pointer */
1247 const struct firmware *gpu_info_fw;
Alex Deucher97b2e202015-04-20 16:51:00 -04001248};
1249
1250/*
1251 * Benchmarking
1252 */
1253void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1254
1255
1256/*
1257 * Testing
1258 */
1259void amdgpu_test_moves(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001260
1261/*
1262 * MMU Notifier
1263 */
1264#if defined(CONFIG_MMU_NOTIFIER)
1265int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1266void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1267#else
Harry Wentland1d1106b2015-07-15 07:10:41 -04001268static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
Alex Deucher97b2e202015-04-20 16:51:00 -04001269{
1270 return -ENODEV;
1271}
Harry Wentland1d1106b2015-07-15 07:10:41 -04001272static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
Alex Deucher97b2e202015-04-20 16:51:00 -04001273#endif
1274
1275/*
1276 * Debugfs
1277 */
1278struct amdgpu_debugfs {
Nils Wallménius06ab6832016-05-02 12:46:15 -04001279 const struct drm_info_list *files;
Alex Deucher97b2e202015-04-20 16:51:00 -04001280 unsigned num_files;
1281};
1282
1283int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
Nils Wallménius06ab6832016-05-02 12:46:15 -04001284 const struct drm_info_list *files,
Alex Deucher97b2e202015-04-20 16:51:00 -04001285 unsigned nfiles);
1286int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1287
1288#if defined(CONFIG_DEBUG_FS)
1289int amdgpu_debugfs_init(struct drm_minor *minor);
Alex Deucher97b2e202015-04-20 16:51:00 -04001290#endif
1291
Huang Rui50ab2532016-06-12 15:51:09 +08001292int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1293
Alex Deucher97b2e202015-04-20 16:51:00 -04001294/*
1295 * amdgpu smumgr functions
1296 */
1297struct amdgpu_smumgr_funcs {
1298 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1299 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1300 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1301};
1302
1303/*
1304 * amdgpu smumgr
1305 */
1306struct amdgpu_smumgr {
1307 struct amdgpu_bo *toc_buf;
1308 struct amdgpu_bo *smu_buf;
1309 /* asic priv smu data */
1310 void *priv;
1311 spinlock_t smu_lock;
1312 /* smumgr functions */
1313 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1314 /* ucode loading complete flag */
1315 uint32_t fw_flags;
1316};
1317
1318/*
1319 * ASIC specific register table accessible by UMD
1320 */
1321struct amdgpu_allowed_register_entry {
1322 uint32_t reg_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -04001323 bool grbm_indexed;
1324};
1325
Alex Deucher97b2e202015-04-20 16:51:00 -04001326/*
1327 * ASIC specific functions.
1328 */
1329struct amdgpu_asic_funcs {
1330 bool (*read_disabled_bios)(struct amdgpu_device *adev);
Alex Deucher7946b872015-11-24 10:14:28 -05001331 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1332 u8 *bios, u32 length_bytes);
Alex Deucher97b2e202015-04-20 16:51:00 -04001333 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1334 u32 sh_num, u32 reg_offset, u32 *value);
1335 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1336 int (*reset)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001337 /* get the reference clock */
1338 u32 (*get_xclk)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001339 /* MM block clocks */
1340 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1341 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001342 /* static power management */
1343 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1344 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
Alex Deucherbbf282d2017-03-03 17:26:10 -05001345 /* get config memsize register */
1346 u32 (*get_config_memsize)(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001347};
1348
1349/*
1350 * IOCTL.
1351 */
1352int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1353 struct drm_file *filp);
1354int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1355 struct drm_file *filp);
1356
1357int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1358 struct drm_file *filp);
1359int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1360 struct drm_file *filp);
1361int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1362 struct drm_file *filp);
1363int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1364 struct drm_file *filp);
1365int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1366 struct drm_file *filp);
1367int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1368 struct drm_file *filp);
1369int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1370int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Junwei Zhangeef18a82016-11-04 16:16:10 -04001371int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1372 struct drm_file *filp);
Alex Deucher97b2e202015-04-20 16:51:00 -04001373
1374int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1375 struct drm_file *filp);
1376
1377/* VRAM scratch page for HDP bug, default vram page */
1378struct amdgpu_vram_scratch {
1379 struct amdgpu_bo *robj;
1380 volatile uint32_t *ptr;
1381 u64 gpu_addr;
1382};
1383
1384/*
1385 * ACPI
1386 */
1387struct amdgpu_atif_notification_cfg {
1388 bool enabled;
1389 int command_code;
1390};
1391
1392struct amdgpu_atif_notifications {
1393 bool display_switch;
1394 bool expansion_mode_change;
1395 bool thermal_state;
1396 bool forced_power_state;
1397 bool system_power_state;
1398 bool display_conf_change;
1399 bool px_gfx_switch;
1400 bool brightness_change;
1401 bool dgpu_display_event;
1402};
1403
1404struct amdgpu_atif_functions {
1405 bool system_params;
1406 bool sbios_requests;
1407 bool select_active_disp;
1408 bool lid_state;
1409 bool get_tv_standard;
1410 bool set_tv_standard;
1411 bool get_panel_expansion_mode;
1412 bool set_panel_expansion_mode;
1413 bool temperature_change;
1414 bool graphics_device_types;
1415};
1416
1417struct amdgpu_atif {
1418 struct amdgpu_atif_notifications notifications;
1419 struct amdgpu_atif_functions functions;
1420 struct amdgpu_atif_notification_cfg notification_cfg;
1421 struct amdgpu_encoder *encoder_for_bl;
1422};
1423
1424struct amdgpu_atcs_functions {
1425 bool get_ext_state;
1426 bool pcie_perf_req;
1427 bool pcie_dev_rdy;
1428 bool pcie_bus_width;
1429};
1430
1431struct amdgpu_atcs {
1432 struct amdgpu_atcs_functions functions;
1433};
1434
Alex Deucher97b2e202015-04-20 16:51:00 -04001435/*
Chunming Zhoud03846a2015-07-28 14:20:03 -04001436 * CGS
1437 */
Dave Airlie110e6f22016-04-12 13:25:48 +10001438struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1439void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001440
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001441/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001442 * Core structure, functions and helpers.
1443 */
1444typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1445typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1446
1447typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1448typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1449
Chunming Zhou0c49e0b2017-05-15 14:20:00 +08001450#define AMDGPU_RESET_MAGIC_NUM 64
Alex Deucher97b2e202015-04-20 16:51:00 -04001451struct amdgpu_device {
1452 struct device *dev;
1453 struct drm_device *ddev;
1454 struct pci_dev *pdev;
Alex Deucher97b2e202015-04-20 16:51:00 -04001455
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001456#ifdef CONFIG_DRM_AMD_ACP
1457 struct amdgpu_acp acp;
1458#endif
1459
Alex Deucher97b2e202015-04-20 16:51:00 -04001460 /* ASIC */
Jammy Zhou2f7d10b2015-07-22 11:29:01 +08001461 enum amd_asic_type asic_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001462 uint32_t family;
1463 uint32_t rev_id;
1464 uint32_t external_rev_id;
1465 unsigned long flags;
1466 int usec_timeout;
1467 const struct amdgpu_asic_funcs *asic_funcs;
1468 bool shutdown;
Alex Deucher97b2e202015-04-20 16:51:00 -04001469 bool need_dma32;
1470 bool accel_working;
Christian Königedf600d2016-05-03 15:54:54 +02001471 struct work_struct reset_work;
Alex Deucher97b2e202015-04-20 16:51:00 -04001472 struct notifier_block acpi_nb;
1473 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1474 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Christian Königedf600d2016-05-03 15:54:54 +02001475 unsigned debugfs_count;
Alex Deucher97b2e202015-04-20 16:51:00 -04001476#if defined(CONFIG_DEBUG_FS)
Tom St Denisadcec282016-04-15 13:08:44 -04001477 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001478#endif
1479 struct amdgpu_atif atif;
1480 struct amdgpu_atcs atcs;
1481 struct mutex srbm_mutex;
1482 /* GRBM index mutex. Protects concurrent access to GRBM index */
1483 struct mutex grbm_idx_mutex;
1484 struct dev_pm_domain vga_pm_domain;
1485 bool have_disp_power_ref;
1486
1487 /* BIOS */
Alex Deucher0cdd5002017-02-13 16:01:58 -05001488 bool is_atom_fw;
Alex Deucher97b2e202015-04-20 16:51:00 -04001489 uint8_t *bios;
Evan Quana9f5db92016-12-07 09:56:46 +08001490 uint32_t bios_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001491 struct amdgpu_bo *stollen_vga_memory;
Alex Deuchera5bde2f2016-09-23 16:23:41 -04001492 uint32_t bios_scratch_reg_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -04001493 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1494
1495 /* Register/doorbell mmio */
1496 resource_size_t rmmio_base;
1497 resource_size_t rmmio_size;
1498 void __iomem *rmmio;
1499 /* protects concurrent MM_INDEX/DATA based register access */
1500 spinlock_t mmio_idx_lock;
1501 /* protects concurrent SMC based register access */
1502 spinlock_t smc_idx_lock;
1503 amdgpu_rreg_t smc_rreg;
1504 amdgpu_wreg_t smc_wreg;
1505 /* protects concurrent PCIE register access */
1506 spinlock_t pcie_idx_lock;
1507 amdgpu_rreg_t pcie_rreg;
1508 amdgpu_wreg_t pcie_wreg;
Huang Rui36b9a952016-08-31 13:23:25 +08001509 amdgpu_rreg_t pciep_rreg;
1510 amdgpu_wreg_t pciep_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001511 /* protects concurrent UVD register access */
1512 spinlock_t uvd_ctx_idx_lock;
1513 amdgpu_rreg_t uvd_ctx_rreg;
1514 amdgpu_wreg_t uvd_ctx_wreg;
1515 /* protects concurrent DIDT register access */
1516 spinlock_t didt_idx_lock;
1517 amdgpu_rreg_t didt_rreg;
1518 amdgpu_wreg_t didt_wreg;
Rex Zhuccdbb202016-06-08 12:47:41 +08001519 /* protects concurrent gc_cac register access */
1520 spinlock_t gc_cac_idx_lock;
1521 amdgpu_rreg_t gc_cac_rreg;
1522 amdgpu_wreg_t gc_cac_wreg;
Evan Quan16abb5d2017-07-04 09:21:50 +08001523 /* protects concurrent se_cac register access */
1524 spinlock_t se_cac_idx_lock;
1525 amdgpu_rreg_t se_cac_rreg;
1526 amdgpu_wreg_t se_cac_wreg;
Alex Deucher97b2e202015-04-20 16:51:00 -04001527 /* protects concurrent ENDPOINT (audio) register access */
1528 spinlock_t audio_endpt_idx_lock;
1529 amdgpu_block_rreg_t audio_endpt_rreg;
1530 amdgpu_block_wreg_t audio_endpt_wreg;
1531 void __iomem *rio_mem;
1532 resource_size_t rio_mem_size;
1533 struct amdgpu_doorbell doorbell;
1534
1535 /* clock/pll info */
1536 struct amdgpu_clock clock;
1537
1538 /* MC */
1539 struct amdgpu_mc mc;
1540 struct amdgpu_gart gart;
1541 struct amdgpu_dummy_page dummy_page;
1542 struct amdgpu_vm_manager vm_manager;
Alex Xiee60f8db2017-03-09 11:36:26 -05001543 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001544
1545 /* memory management */
1546 struct amdgpu_mman mman;
Alex Deucher97b2e202015-04-20 16:51:00 -04001547 struct amdgpu_vram_scratch vram_scratch;
1548 struct amdgpu_wb wb;
1549 atomic64_t vram_usage;
1550 atomic64_t vram_vis_usage;
1551 atomic64_t gtt_usage;
1552 atomic64_t num_bytes_moved;
Christian Königdbd5ed62016-06-21 16:28:14 +02001553 atomic64_t num_evictions;
Marek Olšák68e2c5f2017-05-17 20:05:08 +02001554 atomic64_t num_vram_cpu_page_faults;
Marek Olšákd94aed52015-05-05 21:13:49 +02001555 atomic_t gpu_reset_counter;
Chunming Zhouf1892132017-05-15 16:48:27 +08001556 atomic_t vram_lost_counter;
Alex Deucher97b2e202015-04-20 16:51:00 -04001557
Marek Olšák95844d22016-08-17 23:49:27 +02001558 /* data for buffer migration throttling */
1559 struct {
1560 spinlock_t lock;
1561 s64 last_update_us;
1562 s64 accum_us; /* accumulated microseconds */
John Brooks00f06b22017-06-27 22:33:18 -04001563 s64 accum_us_vis; /* for visible VRAM */
Marek Olšák95844d22016-08-17 23:49:27 +02001564 u32 log2_max_MBps;
1565 } mm_stats;
1566
Alex Deucher97b2e202015-04-20 16:51:00 -04001567 /* display */
Emily Deng9accf2f2016-08-10 16:01:25 +08001568 bool enable_virtual_display;
Alex Deucher97b2e202015-04-20 16:51:00 -04001569 struct amdgpu_mode_info mode_info;
1570 struct work_struct hotplug_work;
1571 struct amdgpu_irq_src crtc_irq;
1572 struct amdgpu_irq_src pageflip_irq;
1573 struct amdgpu_irq_src hpd_irq;
1574
1575 /* rings */
Christian König76bf0db2016-06-01 15:10:02 +02001576 u64 fence_context;
Alex Deucher97b2e202015-04-20 16:51:00 -04001577 unsigned num_rings;
1578 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1579 bool ib_pool_ready;
1580 struct amdgpu_sa_manager ring_tmp_bo;
1581
1582 /* interrupts */
1583 struct amdgpu_irq irq;
1584
Alex Deucher1f7371b2015-12-02 17:46:21 -05001585 /* powerplay */
1586 struct amd_powerplay powerplay;
Jammy Zhoue61710c2015-11-10 18:31:08 -05001587 bool pp_enabled;
Eric Huangf3898ea2015-12-11 16:24:34 -05001588 bool pp_force_state_enabled;
Alex Deucher1f7371b2015-12-02 17:46:21 -05001589
Alex Deucher97b2e202015-04-20 16:51:00 -04001590 /* dpm */
1591 struct amdgpu_pm pm;
1592 u32 cg_flags;
1593 u32 pg_flags;
1594
1595 /* amdgpu smumgr */
1596 struct amdgpu_smumgr smu;
1597
1598 /* gfx */
1599 struct amdgpu_gfx gfx;
1600
1601 /* sdma */
Alex Deucherc113ea12015-10-08 16:30:37 -04001602 struct amdgpu_sdma sdma;
Alex Deucher97b2e202015-04-20 16:51:00 -04001603
Leo Liu95d09062016-12-21 13:21:52 -05001604 union {
1605 struct {
1606 /* uvd */
1607 struct amdgpu_uvd uvd;
Alex Deucher97b2e202015-04-20 16:51:00 -04001608
Leo Liu95d09062016-12-21 13:21:52 -05001609 /* vce */
1610 struct amdgpu_vce vce;
1611 };
1612
1613 /* vcn */
1614 struct amdgpu_vcn vcn;
1615 };
Alex Deucher97b2e202015-04-20 16:51:00 -04001616
1617 /* firmwares */
1618 struct amdgpu_firmware firmware;
1619
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001620 /* PSP */
1621 struct psp_context psp;
1622
Alex Deucher97b2e202015-04-20 16:51:00 -04001623 /* GDS */
1624 struct amdgpu_gds gds;
1625
Alex Deuchera1255102016-10-13 17:41:13 -04001626 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
Alex Deucher97b2e202015-04-20 16:51:00 -04001627 int num_ip_blocks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001628 struct mutex mn_lock;
1629 DECLARE_HASHTABLE(mn_hash, 7);
1630
1631 /* tracking pinned memory */
1632 u64 vram_pin_size;
Chunming Zhoue131b912016-04-05 10:48:48 +08001633 u64 invisible_pin_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001634 u64 gart_pin_size;
Oded Gabbay130e0372015-06-12 21:35:14 +03001635
1636 /* amdkfd interface */
1637 struct kfd_dev *kfd;
Chunming Zhou23ca0e42015-07-06 13:42:58 +08001638
Shirish S2dc80b02017-05-25 10:05:25 +05301639 /* delayed work_func for deferring clockgating during resume */
1640 struct delayed_work late_init_work;
1641
Xiangliang Yu5a5099c2017-01-09 18:06:57 -05001642 struct amdgpu_virt virt;
Chunming Zhou0c4e7fa2016-08-17 11:41:30 +08001643
1644 /* link all shadow bo */
1645 struct list_head shadow_list;
1646 struct mutex shadow_list_lock;
Chunming Zhou5c1354b2016-08-30 16:13:10 +08001647 /* link all gtt */
1648 spinlock_t gtt_list_lock;
1649 struct list_head gtt_list;
Andres Rodriguez795f2812017-03-06 16:27:55 -05001650 /* keep an lru list of rings by HW IP */
1651 struct list_head ring_lru_list;
1652 spinlock_t ring_lru_list_lock;
Chunming Zhou5c1354b2016-08-30 16:13:10 +08001653
Jim Quc836fec2017-02-10 15:59:59 +08001654 /* record hw reset is performed */
1655 bool has_hw_reset;
Chunming Zhou0c49e0b2017-05-15 14:20:00 +08001656 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
Jim Quc836fec2017-02-10 15:59:59 +08001657
Ken Wang47ed4e12017-07-04 13:11:52 +08001658 /* record last mm index being written through WREG32*/
1659 unsigned long last_mm_index;
Alex Deucher97b2e202015-04-20 16:51:00 -04001660};
1661
Christian Königa7d64de2016-09-15 14:58:48 +02001662static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1663{
1664 return container_of(bdev, struct amdgpu_device, mman.bdev);
1665}
1666
Alex Deucher97b2e202015-04-20 16:51:00 -04001667int amdgpu_device_init(struct amdgpu_device *adev,
1668 struct drm_device *ddev,
1669 struct pci_dev *pdev,
1670 uint32_t flags);
1671void amdgpu_device_fini(struct amdgpu_device *adev);
1672int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1673
1674uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
Monk Liu15d72fd2017-01-25 15:07:40 +08001675 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001676void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
Monk Liu15d72fd2017-01-25 15:07:40 +08001677 uint32_t acc_flags);
Alex Deucher97b2e202015-04-20 16:51:00 -04001678u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1679void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1680
1681u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1682void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
Ken Wang832be402016-03-18 15:23:08 +08001683u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1684void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
Alex Deucher97b2e202015-04-20 16:51:00 -04001685
1686/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001687 * Registers read & write functions.
1688 */
Monk Liu15d72fd2017-01-25 15:07:40 +08001689
1690#define AMDGPU_REGS_IDX (1<<0)
1691#define AMDGPU_REGS_NO_KIQ (1<<1)
1692
1693#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1694#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1695
1696#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1697#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1698#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1699#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1700#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
Alex Deucher97b2e202015-04-20 16:51:00 -04001701#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1702#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1703#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1704#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
Huang Rui36b9a952016-08-31 13:23:25 +08001705#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1706#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001707#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1708#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1709#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1710#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1711#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1712#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
Rex Zhuccdbb202016-06-08 12:47:41 +08001713#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1714#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
Evan Quan16abb5d2017-07-04 09:21:50 +08001715#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1716#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001717#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1718#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1719#define WREG32_P(reg, val, mask) \
1720 do { \
1721 uint32_t tmp_ = RREG32(reg); \
1722 tmp_ &= (mask); \
1723 tmp_ |= ((val) & ~(mask)); \
1724 WREG32(reg, tmp_); \
1725 } while (0)
1726#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1727#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1728#define WREG32_PLL_P(reg, val, mask) \
1729 do { \
1730 uint32_t tmp_ = RREG32_PLL(reg); \
1731 tmp_ &= (mask); \
1732 tmp_ |= ((val) & ~(mask)); \
1733 WREG32_PLL(reg, tmp_); \
1734 } while (0)
1735#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1736#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1737#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1738
1739#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1740#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
Ken Wang832be402016-03-18 15:23:08 +08001741#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1742#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
Alex Deucher97b2e202015-04-20 16:51:00 -04001743
1744#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1745#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1746
1747#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1748 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1749 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1750
1751#define REG_GET_FIELD(value, reg, field) \
1752 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1753
Tom St Denis61cb8ce2016-08-09 10:13:21 -04001754#define WREG32_FIELD(reg, field, val) \
1755 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1756
Tom St Denisccaf3572017-04-04 09:14:13 -04001757#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1758 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1759
Alex Deucher97b2e202015-04-20 16:51:00 -04001760/*
1761 * BIOS helpers.
1762 */
1763#define RBIOS8(i) (adev->bios[i])
1764#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1765#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1766
Alex Deucherc113ea12015-10-08 16:30:37 -04001767static inline struct amdgpu_sdma_instance *
1768amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001769{
1770 struct amdgpu_device *adev = ring->adev;
1771 int i;
1772
Alex Deucherc113ea12015-10-08 16:30:37 -04001773 for (i = 0; i < adev->sdma.num_instances; i++)
1774 if (&adev->sdma.instance[i].ring == ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001775 break;
1776
1777 if (i < AMDGPU_MAX_SDMA_INSTANCES)
Alex Deucherc113ea12015-10-08 16:30:37 -04001778 return &adev->sdma.instance[i];
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08001779 else
1780 return NULL;
1781}
1782
Alex Deucher97b2e202015-04-20 16:51:00 -04001783/*
1784 * ASICs macro.
1785 */
1786#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1787#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001788#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1789#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1790#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -04001791#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1792#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1793#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001794#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
Alex Deucher7946b872015-11-24 10:14:28 -05001795#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
Alex Deucher97b2e202015-04-20 16:51:00 -04001796#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
Alex Deucherbbf282d2017-03-03 17:26:10 -05001797#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001798#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1799#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
Christian Königb1166322017-05-12 15:39:39 +02001800#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
Alex Deucher97b2e202015-04-20 16:51:00 -04001801#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
Christian Königde9ea7b2016-08-12 11:33:30 +02001802#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
Alex Deucher97b2e202015-04-20 16:51:00 -04001803#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
Alex Xie54635452017-02-14 12:22:57 -05001804#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001805#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1806#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
Christian Königbbec97a2016-07-05 21:07:17 +02001807#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
Alex Deucher97b2e202015-04-20 16:51:00 -04001808#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1809#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1810#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
Christian Königd88bf582016-05-06 17:50:03 +02001811#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
Christian Königb8c7b392016-03-01 15:42:52 +01001812#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
Alex Deucher97b2e202015-04-20 16:51:00 -04001813#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
Chunming Zhou890ee232015-06-01 14:35:03 +08001814#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04001815#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
Christian Königd2edb072015-05-11 14:10:34 +02001816#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
Chunming Zhou11afbde2016-03-03 11:38:48 +08001817#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
Monk Liuc2167a62016-08-26 14:12:37 +08001818#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
Monk Liu753ad492016-08-26 13:28:28 +08001819#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
Xiangliang Yub6091c12017-01-10 12:53:52 +08001820#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1821#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
Monk Liu3b4d68e2017-05-01 18:09:22 +08001822#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
Christian König9e5d53092016-01-31 12:20:55 +01001823#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
Monk Liu03ccf482016-01-14 19:07:38 +08001824#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1825#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
Alex Deucher97b2e202015-04-20 16:51:00 -04001826#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1827#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1828#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04001829#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1830#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
Alex Deucher97b2e202015-04-20 16:51:00 -04001831#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1832#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1833#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1834#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1835#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1836#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
Alex Deuchercb9e59d2016-05-05 16:03:57 -04001837#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
Alex Deucher97b2e202015-04-20 16:51:00 -04001838#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1839#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1840#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
Chunming Zhouc7ae72c2015-08-25 17:23:45 +08001841#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
Chunming Zhou6e7a3842015-08-27 13:46:09 +08001842#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
Alex Deucherb95e31f2016-07-07 15:01:42 -04001843#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
Tom St Denis9559ef52016-06-28 10:26:48 -04001844#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
Alex Deucher97b2e202015-04-20 16:51:00 -04001845#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
Huang Rui0e5ca0d2017-03-03 18:37:23 -05001846#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
Alex Deucher97b2e202015-04-20 16:51:00 -04001847
1848/* Common functions */
1849int amdgpu_gpu_reset(struct amdgpu_device *adev);
Chunming Zhou3ad81f12016-08-05 17:30:17 +08001850bool amdgpu_need_backup(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001851void amdgpu_pci_config_reset(struct amdgpu_device *adev);
Jim Quc836fec2017-02-10 15:59:59 +08001852bool amdgpu_need_post(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001853void amdgpu_update_display_priority(struct amdgpu_device *adev);
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08001854
John Brooks00f06b22017-06-27 22:33:18 -04001855void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1856 u64 num_vis_bytes);
Christian König765e7fb2016-09-15 15:06:50 +02001857void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
Alex Deucher97b2e202015-04-20 16:51:00 -04001858bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
Christian König2f568db2016-02-23 12:36:59 +01001859int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
Alex Deucher97b2e202015-04-20 16:51:00 -04001860int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1861 uint32_t flags);
1862bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
Christian Königcc325d12016-02-08 11:08:35 +01001863struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
Christian Königd7006962016-02-08 10:57:22 +01001864bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1865 unsigned long end);
Christian König2f568db2016-02-23 12:36:59 +01001866bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1867 int *last_invalidated);
Alex Deucher97b2e202015-04-20 16:51:00 -04001868bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
Chunming Zhou6b777602016-09-21 16:19:19 +08001869uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
Alex Deucher97b2e202015-04-20 16:51:00 -04001870 struct ttm_mem_reg *mem);
1871void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
Christian König6f02a692017-07-07 11:56:59 +02001872void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
Alex Deucher97b2e202015-04-20 16:51:00 -04001873void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
Baoyou Xie9f31a0b02016-09-15 21:43:26 +08001874int amdgpu_ttm_init(struct amdgpu_device *adev);
1875void amdgpu_ttm_fini(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001876void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1877 const u32 *registers,
1878 const u32 array_size);
1879
1880bool amdgpu_device_is_px(struct drm_device *dev);
1881/* atpx handler */
1882#if defined(CONFIG_VGA_SWITCHEROO)
1883void amdgpu_register_atpx_handler(void);
1884void amdgpu_unregister_atpx_handler(void);
Alex Deuchera78fe132016-06-01 13:08:21 -04001885bool amdgpu_has_atpx_dgpu_power_cntl(void);
Alex Deucher2f5af822016-06-02 09:04:01 -04001886bool amdgpu_is_atpx_hybrid(void);
Alex Deucherefc83cf2016-09-14 14:01:41 -04001887bool amdgpu_atpx_dgpu_req_power_for_displays(void);
Alex Xie714f88e2017-04-05 11:07:13 -04001888bool amdgpu_has_atpx(void);
Alex Deucher97b2e202015-04-20 16:51:00 -04001889#else
1890static inline void amdgpu_register_atpx_handler(void) {}
1891static inline void amdgpu_unregister_atpx_handler(void) {}
Alex Deuchera78fe132016-06-01 13:08:21 -04001892static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
Alex Deucher2f5af822016-06-02 09:04:01 -04001893static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
Alex Deucherefc83cf2016-09-14 14:01:41 -04001894static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
Alex Xie714f88e2017-04-05 11:07:13 -04001895static inline bool amdgpu_has_atpx(void) { return false; }
Alex Deucher97b2e202015-04-20 16:51:00 -04001896#endif
1897
1898/*
1899 * KMS
1900 */
1901extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
Nils Wallméniusf498d9e2016-04-10 16:29:59 +02001902extern const int amdgpu_max_kms_ioctl;
Alex Deucher97b2e202015-04-20 16:51:00 -04001903
Chunming Zhouf1892132017-05-15 16:48:27 +08001904bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1905 struct amdgpu_fpriv *fpriv);
Alex Deucher97b2e202015-04-20 16:51:00 -04001906int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -02001907void amdgpu_driver_unload_kms(struct drm_device *dev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001908void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1909int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1910void amdgpu_driver_postclose_kms(struct drm_device *dev,
1911 struct drm_file *file_priv);
Alex Deucherfaefba92016-12-06 10:38:29 -05001912int amdgpu_suspend(struct amdgpu_device *adev);
Alex Deucher810ddc32016-08-23 13:25:49 -04001913int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1914int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
Thierry Reding88e72712015-09-24 18:35:31 +02001915u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1916int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1917void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
Alex Deucher97b2e202015-04-20 16:51:00 -04001918long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1919 unsigned long arg);
1920
1921/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001922 * functions used by amdgpu_encoder.c
1923 */
1924struct amdgpu_afmt_acr {
1925 u32 clock;
1926
1927 int n_32khz;
1928 int cts_32khz;
1929
1930 int n_44_1khz;
1931 int cts_44_1khz;
1932
1933 int n_48khz;
1934 int cts_48khz;
1935
1936};
1937
1938struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1939
1940/* amdgpu_acpi.c */
1941#if defined(CONFIG_ACPI)
1942int amdgpu_acpi_init(struct amdgpu_device *adev);
1943void amdgpu_acpi_fini(struct amdgpu_device *adev);
1944bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1945int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1946 u8 perf_req, bool advertise);
1947int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1948#else
1949static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1950static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1951#endif
1952
1953struct amdgpu_bo_va_mapping *
1954amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1955 uint64_t addr, struct amdgpu_bo **bo);
Christian Königc855e252016-09-05 17:00:57 +02001956int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
Alex Deucher97b2e202015-04-20 16:51:00 -04001957
1958#include "amdgpu_object.h"
Alex Deucher97b2e202015-04-20 16:51:00 -04001959#endif