Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / 482a8f3f53e9bc7a52ef54f6cd40bcf2c270e2f5 / . / arch / arm / boot / dts / spear320.dtsi
blob: 67d7ada7127556eb5b5264ae171145744f82b36d [file] [log] [blame]
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]1/*
2 * DTS file for SPEAr320 SoC
3 *
Viresh Kumar10d89352012-06-20 12:53:02 -0700[diff] [blame]4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
Viresh Kumare0373602012-03-29 08:30:19 +0530[diff] [blame]21 ranges = <0x40000000 0x40000000 0x80000000
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]22 0xd0000000 0xd0000000 0x30000000>;
23
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]24 pinmux: pinmux@b3000000 {
Viresh Kumare0373602012-03-29 08:30:19 +0530[diff] [blame]25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]27 #gpio-range-cells = <2>;
Viresh Kumare0373602012-03-29 08:30:19 +0530[diff] [blame]28 };
29
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]30 clcd@90000000 {
31 compatible = "arm,clcd-pl110", "arm,primecell";
32 reg = <0x90000000 0x1000>;
33 interrupts = <33>;
34 status = "disabled";
35 };
36
37 fsmc: flash@4c000000 {
38 compatible = "st,spear600-fsmc-nand";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 reg = <0x4c000000 0x1000 /* FSMC Register */
42 0x50000000 0x0010>; /* NAND Base */
43 reg-names = "fsmc_regs", "nand_data";
44 st,ale-off = <0x20000>;
45 st,cle-off = <0x10000>;
46 status = "disabled";
47 };
48
49 sdhci@70000000 {
50 compatible = "st,sdhci-spear";
51 reg = <0x70000000 0x100>;
52 interrupts = <29>;
53 status = "disabled";
54 };
55
56 spi1: spi@a5000000 {
57 compatible = "arm,pl022", "arm,primecell";
58 reg = <0xa5000000 0x1000>;
59 status = "disabled";
60 };
61
62 spi2: spi@a6000000 {
63 compatible = "arm,pl022", "arm,primecell";
64 reg = <0xa6000000 0x1000>;
65 status = "disabled";
66 };
67
68 apb {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "simple-bus";
72 ranges = <0xa0000000 0xa0000000 0x10000000
73 0xd0000000 0xd0000000 0x30000000>;
74
75 i2c1: i2c@a7000000 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 compatible = "snps,designware-i2c";
79 reg = <0xa7000000 0x1000>;
80 status = "disabled";
81 };
82
83 serial@a3000000 {
84 compatible = "arm,pl011", "arm,primecell";
85 reg = <0xa3000000 0x1000>;
86 status = "disabled";
87 };
88
89 serial@a4000000 {
90 compatible = "arm,pl011", "arm,primecell";
91 reg = <0xa4000000 0x1000>;
92 status = "disabled";
93 };
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]94
95 gpiopinctrl: gpio@b3000000 {
96 compatible = "st,spear-plgpio";
97 reg = <0xb3000000 0x1000>;
98 #interrupt-cells = <1>;
99 interrupt-controller;
100 gpio-controller;
101 #gpio-cells = <2>;
102 gpio-ranges = <&pinmux 0 102>;
103 status = "disabled";
104
105 st-plgpio,ngpio = <102>;
106 st-plgpio,enb-reg = <0x24>;
107 st-plgpio,wdata-reg = <0x34>;
108 st-plgpio,dir-reg = <0x44>;
109 st-plgpio,ie-reg = <0x64>;
110 st-plgpio,rdata-reg = <0x54>;
111 st-plgpio,mis-reg = <0x84>;
112 st-plgpio,eit-reg = <0x94>;
113 };
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]114 };
115 };
116};