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Greg Rose92915f72010-01-09 02:24:10 +00001/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
Greg Rose5c47a2b2012-01-06 02:53:30 +00004 Copyright(c) 1999 - 2012 Intel Corporation.
Greg Rose92915f72010-01-09 02:24:10 +00005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_H_
29#define _IXGBEVF_H_
30
31#include <linux/types.h>
Jiri Pirkodadcd652011-07-21 03:25:09 +000032#include <linux/bitops.h>
Greg Rose92915f72010-01-09 02:24:10 +000033#include <linux/timer.h>
34#include <linux/io.h>
35#include <linux/netdevice.h>
Jiri Pirkodadcd652011-07-21 03:25:09 +000036#include <linux/if_vlan.h>
Eric Dumazet4197aa72011-06-22 05:01:35 +000037#include <linux/u64_stats_sync.h>
Greg Rose92915f72010-01-09 02:24:10 +000038
39#include "vf.h"
40
Jacob Kellerc777cdf2013-09-21 06:24:20 +000041#ifdef CONFIG_NET_RX_BUSY_POLL
42#include <net/busy_poll.h>
Jacob Keller3b5dca22013-09-21 06:24:25 +000043#define BP_EXTENDED_STATS
Jacob Kellerc777cdf2013-09-21 06:24:20 +000044#endif
45
Greg Rose92915f72010-01-09 02:24:10 +000046/* wrapper around a pointer to a socket buffer,
47 * so a DMA handle can be stored along with the buffer */
48struct ixgbevf_tx_buffer {
49 struct sk_buff *skb;
50 dma_addr_t dma;
51 unsigned long time_stamp;
Alexander Duycke757e3e2013-01-31 07:43:22 +000052 union ixgbe_adv_tx_desc *next_to_watch;
Greg Rose92915f72010-01-09 02:24:10 +000053 u16 length;
Greg Rose92915f72010-01-09 02:24:10 +000054 u16 mapped_as_page;
55};
56
57struct ixgbevf_rx_buffer {
58 struct sk_buff *skb;
59 dma_addr_t dma;
Greg Rose92915f72010-01-09 02:24:10 +000060};
61
62struct ixgbevf_ring {
Alexander Duyck6b43c442012-05-11 08:32:45 +000063 struct ixgbevf_ring *next;
Alexander Duyckfb401952012-05-11 08:33:16 +000064 struct net_device *netdev;
65 struct device *dev;
Greg Rose92915f72010-01-09 02:24:10 +000066 void *desc; /* descriptor ring memory */
67 dma_addr_t dma; /* phys. address of descriptor ring */
68 unsigned int size; /* length in bytes */
69 unsigned int count; /* amount of descriptors */
70 unsigned int next_to_use;
71 unsigned int next_to_clean;
72
73 int queue_index; /* needed for multiqueue queue management */
74 union {
75 struct ixgbevf_tx_buffer *tx_buffer_info;
76 struct ixgbevf_rx_buffer *rx_buffer_info;
77 };
78
Eric Dumazet4197aa72011-06-22 05:01:35 +000079 u64 total_bytes;
80 u64 total_packets;
81 struct u64_stats_sync syncp;
Greg Rose55fb2772012-11-06 05:53:32 +000082 u64 hw_csum_rx_error;
83 u64 hw_csum_rx_good;
Jacob Keller3b5dca22013-09-21 06:24:25 +000084#ifdef BP_EXTENDED_STATS
85 u64 bp_yields;
86 u64 bp_misses;
87 u64 bp_cleaned;
88#endif
Eric Dumazet4197aa72011-06-22 05:01:35 +000089
Greg Rose92915f72010-01-09 02:24:10 +000090 u16 head;
91 u16 tail;
92
Greg Rose92915f72010-01-09 02:24:10 +000093 u16 reg_idx; /* holds the special value that gets the hardware register
94 * offset associated with this ring, which is different
95 * for DCB and RSS modes */
96
Greg Rose92915f72010-01-09 02:24:10 +000097 u16 rx_buf_len;
98};
99
Greg Rose92915f72010-01-09 02:24:10 +0000100/* How many Rx Buffers do we bundle into one write to the hardware ? */
101#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
102
Alexander Duyck56e94092012-07-20 08:10:03 +0000103#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
104#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
Greg Rose92915f72010-01-09 02:24:10 +0000105
106#define IXGBEVF_DEFAULT_TXD 1024
107#define IXGBEVF_DEFAULT_RXD 512
108#define IXGBEVF_MAX_TXD 4096
109#define IXGBEVF_MIN_TXD 64
110#define IXGBEVF_MAX_RXD 4096
111#define IXGBEVF_MIN_RXD 64
112
113/* Supported Rx Buffer Sizes */
Greg Rose92915f72010-01-09 02:24:10 +0000114#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
Greg Rose85624ca2012-11-13 04:03:19 +0000115#define IXGBEVF_RXBUFFER_2K 2048
116#define IXGBEVF_RXBUFFER_4K 4096
117#define IXGBEVF_RXBUFFER_8K 8192
118#define IXGBEVF_RXBUFFER_10K 10240
Greg Rose92915f72010-01-09 02:24:10 +0000119
120#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
121
122#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
123
124#define IXGBE_TX_FLAGS_CSUM (u32)(1)
125#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
126#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
127#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
128#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
129#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
130#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
131#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
132#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
133
Alexander Duyck6b43c442012-05-11 08:32:45 +0000134struct ixgbevf_ring_container {
135 struct ixgbevf_ring *ring; /* pointer to linked list of rings */
Alexander Duyck5f3600e2012-05-11 08:32:55 +0000136 unsigned int total_bytes; /* total bytes processed this int */
137 unsigned int total_packets; /* total packets processed this int */
Alexander Duyck6b43c442012-05-11 08:32:45 +0000138 u8 count; /* total number of rings in vector */
139 u8 itr; /* current ITR setting for ring */
140};
141
142/* iterator for handling rings in ring container */
143#define ixgbevf_for_each_ring(pos, head) \
144 for (pos = (head).ring; pos != NULL; pos = pos->next)
145
Greg Rose92915f72010-01-09 02:24:10 +0000146/* MAX_MSIX_Q_VECTORS of these are allocated,
147 * but we only use one per queue-specific vector.
148 */
149struct ixgbevf_q_vector {
150 struct ixgbevf_adapter *adapter;
Alexander Duyck5f3600e2012-05-11 08:32:55 +0000151 u16 v_idx; /* index of q_vector within array, also used for
152 * finding the bit in EICR and friends that
153 * represents the vector for this ring */
154 u16 itr; /* Interrupt throttle rate written to EITR */
Greg Rose92915f72010-01-09 02:24:10 +0000155 struct napi_struct napi;
Alexander Duyck6b43c442012-05-11 08:32:45 +0000156 struct ixgbevf_ring_container rx, tx;
Alexander Duyckfa71ae22012-05-11 08:32:50 +0000157 char name[IFNAMSIZ + 9];
Jacob Kellerc777cdf2013-09-21 06:24:20 +0000158#ifdef CONFIG_NET_RX_BUSY_POLL
159 unsigned int state;
160#define IXGBEVF_QV_STATE_IDLE 0
161#define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */
162#define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */
163#define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */
164#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
165#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
166#define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
167#define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
168#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | IXGBEVF_QV_STATE_POLL_YIELD)
169#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | IXGBEVF_QV_STATE_POLL_YIELD)
170 spinlock_t lock;
171#endif /* CONFIG_NET_RX_BUSY_POLL */
Greg Rose92915f72010-01-09 02:24:10 +0000172};
Jacob Kellerc777cdf2013-09-21 06:24:20 +0000173#ifdef CONFIG_NET_RX_BUSY_POLL
174static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
175{
176
177 spin_lock_init(&q_vector->lock);
178 q_vector->state = IXGBEVF_QV_STATE_IDLE;
179}
180
181/* called from the device poll routine to get ownership of a q_vector */
182static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
183{
184 int rc = true;
185 spin_lock_bh(&q_vector->lock);
186 if (q_vector->state & IXGBEVF_QV_LOCKED) {
187 WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
188 q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD;
189 rc = false;
Jacob Keller3b5dca22013-09-21 06:24:25 +0000190#ifdef BP_EXTENDED_STATS
191 q_vector->tx.ring->bp_yields++;
192#endif
Jacob Kellerc777cdf2013-09-21 06:24:20 +0000193 } else {
194 /* we don't care if someone yielded */
195 q_vector->state = IXGBEVF_QV_STATE_NAPI;
196 }
197 spin_unlock_bh(&q_vector->lock);
198 return rc;
199}
200
201/* returns true is someone tried to get the qv while napi had it */
202static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
203{
204 int rc = false;
205 spin_lock_bh(&q_vector->lock);
206 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL |
207 IXGBEVF_QV_STATE_NAPI_YIELD));
208
209 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
210 rc = true;
211 /* reset state to idle, unless QV is disabled */
212 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
213 spin_unlock_bh(&q_vector->lock);
214 return rc;
215}
216
217/* called from ixgbevf_low_latency_poll() */
218static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
219{
220 int rc = true;
221 spin_lock_bh(&q_vector->lock);
222 if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
223 q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD;
224 rc = false;
Jacob Keller3b5dca22013-09-21 06:24:25 +0000225#ifdef BP_EXTENDED_STATS
226 q_vector->rx.ring->bp_yields++;
227#endif
Jacob Kellerc777cdf2013-09-21 06:24:20 +0000228 } else {
229 /* preserve yield marks */
230 q_vector->state |= IXGBEVF_QV_STATE_POLL;
231 }
232 spin_unlock_bh(&q_vector->lock);
233 return rc;
234}
235
236/* returns true if someone tried to get the qv while it was locked */
237static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
238{
239 int rc = false;
240 spin_lock_bh(&q_vector->lock);
241 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));
242
243 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
244 rc = true;
245 /* reset state to idle, unless QV is disabled */
246 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
247 spin_unlock_bh(&q_vector->lock);
248 return rc;
249}
250
251/* true if a socket is polling, even if it did not get the lock */
252static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
253{
254 WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
255 return q_vector->state & IXGBEVF_QV_USER_PEND;
256}
257
258/* false if QV is currently owned */
259static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
260{
261 int rc = true;
262 spin_lock_bh(&q_vector->lock);
263 if (q_vector->state & IXGBEVF_QV_OWNED)
264 rc = false;
265 spin_unlock_bh(&q_vector->lock);
266 return rc;
267}
268
269#endif /* CONFIG_NET_RX_BUSY_POLL */
Greg Rose92915f72010-01-09 02:24:10 +0000270
Alexander Duyck5f3600e2012-05-11 08:32:55 +0000271/*
272 * microsecond values for various ITR rates shifted by 2 to fit itr register
273 * with the first 3 bits reserved 0
274 */
275#define IXGBE_MIN_RSC_ITR 24
276#define IXGBE_100K_ITR 40
277#define IXGBE_20K_ITR 200
278#define IXGBE_10K_ITR 400
279#define IXGBE_8K_ITR 500
280
Greg Rose92915f72010-01-09 02:24:10 +0000281/* Helper macros to switch between ints/sec and what the register uses.
282 * And yes, it's the same math going both ways. The lowest value
283 * supported by all of the ixgbe hardware is 8.
284 */
285#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
286 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
287#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
288
289#define IXGBE_DESC_UNUSED(R) \
290 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
291 (R)->next_to_clean - (R)->next_to_use - 1)
292
Alexander Duyck908421f2012-05-11 08:33:00 +0000293#define IXGBEVF_RX_DESC(R, i) \
294 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
295#define IXGBEVF_TX_DESC(R, i) \
296 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
297#define IXGBEVF_TX_CTXTDESC(R, i) \
298 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
Greg Rose92915f72010-01-09 02:24:10 +0000299
Alexander Duyckc88887e2012-08-22 02:04:37 +0000300#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
Greg Rose92915f72010-01-09 02:24:10 +0000301
302#define OTHER_VECTOR 1
303#define NON_Q_VECTORS (OTHER_VECTOR)
304
305#define MAX_MSIX_Q_VECTORS 2
Greg Rose92915f72010-01-09 02:24:10 +0000306
Alexander Duyckfa71ae22012-05-11 08:32:50 +0000307#define MIN_MSIX_Q_VECTORS 1
Greg Rose92915f72010-01-09 02:24:10 +0000308#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
309
310/* board specific private data structure */
311struct ixgbevf_adapter {
312 struct timer_list watchdog_timer;
Jiri Pirkodadcd652011-07-21 03:25:09 +0000313 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
Greg Rose92915f72010-01-09 02:24:10 +0000314 u16 bd_number;
315 struct work_struct reset_task;
316 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
Greg Rose92915f72010-01-09 02:24:10 +0000317
318 /* Interrupt Throttle Rate */
Alexander Duyck5f3600e2012-05-11 08:32:55 +0000319 u16 rx_itr_setting;
320 u16 tx_itr_setting;
321
322 /* interrupt masks */
323 u32 eims_enable_mask;
324 u32 eims_other;
Greg Rose92915f72010-01-09 02:24:10 +0000325
326 /* TX */
327 struct ixgbevf_ring *tx_ring; /* One per active queue */
328 int num_tx_queues;
329 u64 restart_queue;
330 u64 hw_csum_tx_good;
331 u64 lsc_int;
332 u64 hw_tso_ctxt;
333 u64 hw_tso6_ctxt;
334 u32 tx_timeout_count;
Greg Rose92915f72010-01-09 02:24:10 +0000335
336 /* RX */
337 struct ixgbevf_ring *rx_ring; /* One per active queue */
338 int num_rx_queues;
Greg Rose92915f72010-01-09 02:24:10 +0000339 u64 hw_csum_rx_error;
340 u64 hw_rx_no_dma_resources;
341 u64 hw_csum_rx_good;
342 u64 non_eop_descs;
343 int num_msix_vectors;
Greg Rose92915f72010-01-09 02:24:10 +0000344 struct msix_entry *msix_entries;
345
Greg Rose92915f72010-01-09 02:24:10 +0000346 u32 alloc_rx_page_failed;
347 u32 alloc_rx_buff_failed;
348
349 /* Some features need tri-state capability,
350 * thus the additional *_CAPABLE flags.
351 */
352 u32 flags;
Alexander Duyck525a9402012-05-11 08:32:29 +0000353#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1)
Greg Rose366c1092012-11-13 04:03:18 +0000354#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 1)
Alexander Duyck77d5dfc2012-05-11 08:32:19 +0000355
Greg Rose92915f72010-01-09 02:24:10 +0000356 /* OS defined structs */
357 struct net_device *netdev;
358 struct pci_dev *pdev;
Greg Rose92915f72010-01-09 02:24:10 +0000359
360 /* structs defined in ixgbe_vf.h */
361 struct ixgbe_hw hw;
362 u16 msg_enable;
363 struct ixgbevf_hw_stats stats;
Greg Rose92915f72010-01-09 02:24:10 +0000364 /* Interrupt Throttle Rate */
365 u32 eitr_param;
366
367 unsigned long state;
Greg Rose92915f72010-01-09 02:24:10 +0000368 u64 tx_busy;
369 unsigned int tx_ring_count;
370 unsigned int rx_ring_count;
371
Jacob Keller3b5dca22013-09-21 06:24:25 +0000372#ifdef BP_EXTENDED_STATS
373 u64 bp_rx_yields;
374 u64 bp_rx_cleaned;
375 u64 bp_rx_missed;
376
377 u64 bp_tx_yields;
378 u64 bp_tx_cleaned;
379 u64 bp_tx_missed;
380#endif
381
Greg Rose92915f72010-01-09 02:24:10 +0000382 u32 link_speed;
383 bool link_up;
Greg Rose92915f72010-01-09 02:24:10 +0000384
385 struct work_struct watchdog_task;
Alexander Duyck1c55ed72012-05-11 08:33:06 +0000386
387 spinlock_t mbx_lock;
Greg Rose92915f72010-01-09 02:24:10 +0000388};
389
390enum ixbgevf_state_t {
391 __IXGBEVF_TESTING,
392 __IXGBEVF_RESETTING,
393 __IXGBEVF_DOWN
394};
395
Alexander Duyck5c60f812012-09-01 05:12:38 +0000396struct ixgbevf_cb {
397 struct sk_buff *prev;
398};
399#define IXGBE_CB(skb) ((struct ixgbevf_cb *)(skb)->cb)
400
Greg Rose92915f72010-01-09 02:24:10 +0000401enum ixgbevf_boards {
402 board_82599_vf,
Greg Rose2316aa22010-12-02 07:12:26 +0000403 board_X540_vf,
Greg Rose92915f72010-01-09 02:24:10 +0000404};
405
Stephen Hemminger3d8fe982012-01-18 22:13:34 +0000406extern const struct ixgbevf_info ixgbevf_82599_vf_info;
407extern const struct ixgbevf_info ixgbevf_X540_vf_info;
Stephen Hemmingerb5417bf2012-01-18 22:13:33 +0000408extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
Greg Rose92915f72010-01-09 02:24:10 +0000409
410/* needed by ethtool.c */
Stephen Hemminger3d8fe982012-01-18 22:13:34 +0000411extern const char ixgbevf_driver_name[];
Greg Rose92915f72010-01-09 02:24:10 +0000412extern const char ixgbevf_driver_version[];
413
Joe Perches5ccc9212013-09-23 11:37:59 -0700414void ixgbevf_up(struct ixgbevf_adapter *adapter);
415void ixgbevf_down(struct ixgbevf_adapter *adapter);
416void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
417void ixgbevf_reset(struct ixgbevf_adapter *adapter);
418void ixgbevf_set_ethtool_ops(struct net_device *netdev);
419int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *, struct ixgbevf_ring *);
420int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *, struct ixgbevf_ring *);
421void ixgbevf_free_rx_resources(struct ixgbevf_adapter *, struct ixgbevf_ring *);
422void ixgbevf_free_tx_resources(struct ixgbevf_adapter *, struct ixgbevf_ring *);
423void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
424int ethtool_ioctl(struct ifreq *ifr);
Greg Rose92915f72010-01-09 02:24:10 +0000425
Jacob Keller38496232013-10-22 06:19:18 +0000426extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
427
Joe Perches5ccc9212013-09-23 11:37:59 -0700428void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
429void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
Greg Rose92915f72010-01-09 02:24:10 +0000430
431#ifdef DEBUG
Joe Perches5ccc9212013-09-23 11:37:59 -0700432char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw);
Greg Rose92915f72010-01-09 02:24:10 +0000433#define hw_dbg(hw, format, arg...) \
434 printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
435#else
436#define hw_dbg(hw, format, arg...) do {} while (0)
437#endif
438
439#endif /* _IXGBEVF_H_ */