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Alan Tull6a8c3be2015-10-07 16:36:28 +01001/*
2 * FPGA Framework
3 *
Alan Tull5cf0c7f2017-11-15 14:20:12 -06004 * Copyright (C) 2013-2016 Altera Corporation
5 * Copyright (C) 2017 Intel Corporation
Alan Tull6a8c3be2015-10-07 16:36:28 +01006 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
Alan Tull6a8c3be2015-10-07 16:36:28 +010019#ifndef _LINUX_FPGA_MGR_H
20#define _LINUX_FPGA_MGR_H
21
Alan Tull5cf0c7f2017-11-15 14:20:12 -060022#include <linux/mutex.h>
23#include <linux/platform_device.h>
24
Alan Tull6a8c3be2015-10-07 16:36:28 +010025struct fpga_manager;
Jason Gunthorpebaa6d392017-02-01 12:48:44 -070026struct sg_table;
Alan Tull6a8c3be2015-10-07 16:36:28 +010027
28/**
29 * enum fpga_mgr_states - fpga framework states
30 * @FPGA_MGR_STATE_UNKNOWN: can't determine state
31 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
32 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
33 * @FPGA_MGR_STATE_RESET: FPGA in reset state
34 * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
35 * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
36 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
37 * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
38 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
39 * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
40 * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps
41 * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
42 * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating
43 */
44enum fpga_mgr_states {
45 /* default FPGA states */
46 FPGA_MGR_STATE_UNKNOWN,
47 FPGA_MGR_STATE_POWER_OFF,
48 FPGA_MGR_STATE_POWER_UP,
49 FPGA_MGR_STATE_RESET,
50
51 /* getting an image for loading */
52 FPGA_MGR_STATE_FIRMWARE_REQ,
53 FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
54
55 /* write sequence: init, write, complete */
56 FPGA_MGR_STATE_WRITE_INIT,
57 FPGA_MGR_STATE_WRITE_INIT_ERR,
58 FPGA_MGR_STATE_WRITE,
59 FPGA_MGR_STATE_WRITE_ERR,
60 FPGA_MGR_STATE_WRITE_COMPLETE,
61 FPGA_MGR_STATE_WRITE_COMPLETE_ERR,
62
63 /* fpga is programmed and operating */
64 FPGA_MGR_STATE_OPERATING,
65};
66
67/*
68 * FPGA Manager flags
69 * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
Alan Tull0fa20cd2016-11-01 14:14:29 -050070 * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
Anatolij Gustschin68f6be62017-06-14 10:36:27 -050071 * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
Anatolij Gustschinb37fa562017-06-14 10:36:34 -050072 * FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed
Alan Tull6a8c3be2015-10-07 16:36:28 +010073 */
74#define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
Alan Tull0fa20cd2016-11-01 14:14:29 -050075#define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
Moritz Fischer0f4f0c82017-02-27 09:19:00 -060076#define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2)
Anatolij Gustschin68f6be62017-06-14 10:36:27 -050077#define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3)
Anatolij Gustschinb37fa562017-06-14 10:36:34 -050078#define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4)
Alan Tull6a8c3be2015-10-07 16:36:28 +010079
80/**
Alan Tull1df28652016-11-01 14:14:26 -050081 * struct fpga_image_info - information specific to a FPGA image
82 * @flags: boolean flags as defined above
83 * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
84 * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
Alan Tull42d5ec92017-03-23 19:34:27 -050085 * @config_complete_timeout_us: maximum time for FPGA to switch to operating
86 * status in the write_complete op.
Alan Tull5cf0c7f2017-11-15 14:20:12 -060087 * @firmware_name: name of FPGA image firmware file
88 * @sgt: scatter/gather table containing FPGA image
89 * @buf: contiguous buffer containing FPGA image
90 * @count: size of buf
91 * @dev: device that owns this
Alan Tull61c32102017-11-15 14:20:19 -060092 * @overlay: Device Tree overlay
Alan Tull1df28652016-11-01 14:14:26 -050093 */
94struct fpga_image_info {
95 u32 flags;
96 u32 enable_timeout_us;
97 u32 disable_timeout_us;
Alan Tull42d5ec92017-03-23 19:34:27 -050098 u32 config_complete_timeout_us;
Alan Tull5cf0c7f2017-11-15 14:20:12 -060099 char *firmware_name;
100 struct sg_table *sgt;
101 const char *buf;
102 size_t count;
103 struct device *dev;
Alan Tull61c32102017-11-15 14:20:19 -0600104#ifdef CONFIG_OF
105 struct device_node *overlay;
106#endif
Alan Tull1df28652016-11-01 14:14:26 -0500107};
108
109/**
Alan Tull6a8c3be2015-10-07 16:36:28 +0100110 * struct fpga_manager_ops - ops for low level fpga manager drivers
Jason Gunthorpe1d7f1582016-11-22 18:22:09 +0000111 * @initial_header_size: Maximum number of bytes that should be passed into write_init
Alan Tull6a8c3be2015-10-07 16:36:28 +0100112 * @state: returns an enum value of the FPGA's state
113 * @write_init: prepare the FPGA to receive confuration data
114 * @write: write count bytes of configuration data to the FPGA
Jason Gunthorpebaa6d392017-02-01 12:48:44 -0700115 * @write_sg: write the scatter list of configuration data to the FPGA
Alan Tull6a8c3be2015-10-07 16:36:28 +0100116 * @write_complete: set FPGA to operating state after writing is done
117 * @fpga_remove: optional: Set FPGA into a specific state during driver remove
Alan Tull845089b2017-11-15 14:20:28 -0600118 * @groups: optional attribute groups.
Alan Tull6a8c3be2015-10-07 16:36:28 +0100119 *
120 * fpga_manager_ops are the low level functions implemented by a specific
121 * fpga manager driver. The optional ones are tested for NULL before being
122 * called, so leaving them out is fine.
123 */
124struct fpga_manager_ops {
Jason Gunthorpe1d7f1582016-11-22 18:22:09 +0000125 size_t initial_header_size;
Alan Tull6a8c3be2015-10-07 16:36:28 +0100126 enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
Alan Tull1df28652016-11-01 14:14:26 -0500127 int (*write_init)(struct fpga_manager *mgr,
128 struct fpga_image_info *info,
Alan Tull6a8c3be2015-10-07 16:36:28 +0100129 const char *buf, size_t count);
130 int (*write)(struct fpga_manager *mgr, const char *buf, size_t count);
Jason Gunthorpebaa6d392017-02-01 12:48:44 -0700131 int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
Alan Tull1df28652016-11-01 14:14:26 -0500132 int (*write_complete)(struct fpga_manager *mgr,
133 struct fpga_image_info *info);
Alan Tull6a8c3be2015-10-07 16:36:28 +0100134 void (*fpga_remove)(struct fpga_manager *mgr);
Alan Tull845089b2017-11-15 14:20:28 -0600135 const struct attribute_group **groups;
Alan Tull6a8c3be2015-10-07 16:36:28 +0100136};
137
138/**
139 * struct fpga_manager - fpga manager structure
140 * @name: name of low level fpga manager
141 * @dev: fpga manager device
142 * @ref_mutex: only allows one reference to fpga manager
143 * @state: state of fpga manager
144 * @mops: pointer to struct of fpga manager ops
145 * @priv: low level driver private date
146 */
147struct fpga_manager {
148 const char *name;
149 struct device dev;
150 struct mutex ref_mutex;
151 enum fpga_mgr_states state;
152 const struct fpga_manager_ops *mops;
153 void *priv;
154};
155
156#define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
157
Alan Tull5cf0c7f2017-11-15 14:20:12 -0600158struct fpga_image_info *fpga_image_info_alloc(struct device *dev);
Alan Tull6a8c3be2015-10-07 16:36:28 +0100159
Alan Tull5cf0c7f2017-11-15 14:20:12 -0600160void fpga_image_info_free(struct fpga_image_info *info);
161
162int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info);
Alan Tull6a8c3be2015-10-07 16:36:28 +0100163
Alan Tullebf877a52017-11-15 14:20:13 -0600164int fpga_mgr_lock(struct fpga_manager *mgr);
165void fpga_mgr_unlock(struct fpga_manager *mgr);
166
Alan Tull6a8c3be2015-10-07 16:36:28 +0100167struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
168
Alan Tull9dce0282016-11-01 14:14:23 -0500169struct fpga_manager *fpga_mgr_get(struct device *dev);
170
Alan Tull6a8c3be2015-10-07 16:36:28 +0100171void fpga_mgr_put(struct fpga_manager *mgr);
172
173int fpga_mgr_register(struct device *dev, const char *name,
174 const struct fpga_manager_ops *mops, void *priv);
175
176void fpga_mgr_unregister(struct device *dev);
177
178#endif /*_LINUX_FPGA_MGR_H */