Fenghua Yu | 113c609 | 2016-10-22 06:19:54 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_INTEL_RDT_COMMON_H |
| 2 | #define _ASM_X86_INTEL_RDT_COMMON_H |
| 3 | |
| 4 | #define MSR_IA32_PQR_ASSOC 0x0c8f |
| 5 | |
Fenghua Yu | 6b28156 | 2016-10-22 06:19:56 -0700 | [diff] [blame] | 6 | /** |
| 7 | * struct intel_pqr_state - State cache for the PQR MSR |
| 8 | * @rmid: The cached Resource Monitoring ID |
| 9 | * @closid: The cached Class Of Service ID |
| 10 | * @rmid_usecnt: The usage counter for rmid |
| 11 | * |
| 12 | * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the |
| 13 | * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always |
| 14 | * contains both parts, so we need to cache them. |
| 15 | * |
| 16 | * The cache also helps to avoid pointless updates if the value does |
| 17 | * not change. |
| 18 | */ |
| 19 | struct intel_pqr_state { |
| 20 | u32 rmid; |
| 21 | u32 closid; |
| 22 | int rmid_usecnt; |
| 23 | }; |
| 24 | |
| 25 | DECLARE_PER_CPU(struct intel_pqr_state, pqr_state); |
| 26 | |
Fenghua Yu | 113c609 | 2016-10-22 06:19:54 -0700 | [diff] [blame] | 27 | #endif /* _ASM_X86_INTEL_RDT_COMMON_H */ |