msm: clock-9615: Modify PLL9 (SC_PLL0) usage
Previously PLL9 was being configured to run at 440MHz
and was also being switched to FSM mode by the 9615
clock driver. The bootchain now configures this PLL
in non-FSM mode and - at runtime - programs the PLL
to run at 440 or 550MHz.
At runtime, detect the rate of PLL9 in the clock
driver and fixup the rate in the pll clock structure
accordingly. Also fixup acpuclock tables to reflect
the rate of the PLL at runtime.
Change-Id: Ib304ce22d1e92affba9f6ea044764160dfcfc484
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
2 files changed