tree ba28b26c6a4e254e303b7f8af0de9b827e6d6250
parent 15839b4774c618117122074c630a49983f515318
author Liu Jiang <jiang.liu@huawei.com> 1331647629 +0800
committer Tony Luck <tony.luck@intel.com> 1331757347 -0700

[IA64] Fix ISA IRQ trigger model and polarity setting

When handling Interrupt Source Override in MADT table, the default
ISA IRQ trigger model and polarity should be edge-rising.
Current IA64 implmentation doesn't follow the specification and
set default ISA IRQ trigger model as level-low. With that wrong
configuration and when system runs out of interrupt vectors,
it will cause vector sharing among edge triggered ISA IRQ and
level triggered PCI IRQ, then interrupt storm. So change the code
to follow the specification.

Signed-off-by: Liu Jiang <jiang.liu@huawei.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>