| commit | 075c733e19ce7530b53b78151cc4d303c8f64548 | [log] [tgz] |
|---|---|---|
| author | Ralf Baechle <ralf@linux-mips.org> | Thu Jul 05 08:14:21 2007 +0100 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Fri Jul 06 16:17:11 2007 +0100 |
| tree | c4f3e9a373b924794c97f5964cd55b121918ab41 | |
| parent | 9349075a15a876f8e82f433ec84f99d19d3e77f9 [diff] |
[MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR. The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra opposes it being called that) where invalid instructions in the same I-cache line worth of instructions being fetched may case spurious exceptions. The workaround for this was only enabled for E9000 cores; enable it also for all RM7000-based platforms. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>