Merge "msm: camera2: Add driver for cpp module"
diff --git a/Documentation/devicetree/bindings/arm/msm/bcl.txt b/Documentation/devicetree/bindings/arm/msm/bcl.txt
new file mode 100644
index 0000000..e11a817
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/bcl.txt
@@ -0,0 +1,15 @@
+* Battery Current Limit
+
+This Battery Current Limit device, provides an interface to detect and notify
+interested applications when the SOC is drawing current in excess of the limits
+specified.
+
+The device tree parameters for bcl are:
+
+Required parameters:
+- compatible: Must be "qcom,bcl"
+
+Example:
+ qcom,bcl {
+ compatible = "qcom,bcl";
+ };
diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index b1f6717..8f602b6 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -21,8 +21,6 @@
images and self-authentication is not desired;
<1> if the hardware requires self-authenticating images.
- qcom,is-loadable: if PIL is required to load the modem image
-- qcom,gpio-err-fatal: GPIO used by the modem to indicate error fatal to the apps.
-- qcom,gpio-force-stop: GPIO used by the apps to force the modem to shutdown.
Optional properties:
- vdd_pll-supply: Reference to the regulator that supplies the PLL's rail.
@@ -46,10 +44,4 @@
qcom,is-loadable;
qcom,firmware-name = "mba";
qcom,pil-self-auth = <1>;
-
- /* GPIO inputs from mss */
- gpio_err_fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
-
- /* GPIO output to mss */
- gpio_force_stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
};
diff --git a/Documentation/devicetree/bindings/power/qpnp-charger.txt b/Documentation/devicetree/bindings/power/qpnp-charger.txt
index 03b01ee..a868b75 100644
--- a/Documentation/devicetree/bindings/power/qpnp-charger.txt
+++ b/Documentation/devicetree/bindings/power/qpnp-charger.txt
@@ -34,6 +34,8 @@
system thermal mitigation level.
Parent node optional properties:
+- qcom,chg-maxinput-usb-ma: Maximum input current USB.
+- qcom,chg-maxinput-dc-ma: Maximum input current DC.
- qcom,chg-charging-disabled: Set this property to disable charging
by default. This can then be overriden
writing the the module parameter
diff --git a/arch/arm/boot/dts/msm8974-smp2p.dtsi b/arch/arm/boot/dts/msm8974-smp2p.dtsi
index 60f63a8..511f91f 100644
--- a/arch/arm/boot/dts/msm8974-smp2p.dtsi
+++ b/arch/arm/boot/dts/msm8974-smp2p.dtsi
@@ -103,29 +103,6 @@
gpios = <&smp2pgpio_smp2p_1_out 0 0>;
};
- /* SMP2P SSR Driver for inbound entry from modem. */
- smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in {
- compatible = "qcom,smp2pgpio";
- qcom,entry-name = "slave-kernel";
- qcom,remote-pid = <1>;
- qcom,is-inbound;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- /* SMP2P SSR Driver for outbound entry to modem */
- smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out {
- compatible = "qcom,smp2pgpio";
- qcom,entry-name = "master-kernel";
- qcom,remote-pid = <1>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
/* SMP2P Test Driver for adsp inbound */
smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in {
compatible = "qcom,smp2pgpio";
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 1ef376f..3be174f 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -883,12 +883,6 @@
qcom,is-loadable;
qcom,firmware-name = "mba";
qcom,pil-self-auth = <1>;
-
- /* GPIO input from mss */
- qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
-
- /* GPIO output to mss */
- qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
};
qcom,pronto@fb21b000 {
@@ -1261,6 +1255,10 @@
qcom,irq-no-suspend;
};
};
+
+ qcom,bcl {
+ compatible = "qcom,bcl";
+ };
};
&gdsc_venus {
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index 2f2e0b3..6780761 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -308,6 +308,7 @@
CONFIG_SENSORS_QPNP_ADC_CURRENT=y
CONFIG_THERMAL=y
CONFIG_THERMAL_TSENS8974=y
+CONFIG_THERMAL_MONITOR=y
CONFIG_THERMAL_QPNP=y
CONFIG_THERMAL_QPNP_ADC_TM=y
CONFIG_WCD9320_CODEC=y
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 6ba11b2..d8f5425 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -252,7 +252,15 @@
{ 0, { 0 } }
};
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+static struct pvs_table pvs_v1[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+ [0][0] = { acpu_freq_tbl_pvs0, sizeof(acpu_freq_tbl_pvs0) },
+ [0][1] = { acpu_freq_tbl_pvs1, sizeof(acpu_freq_tbl_pvs1) },
+ [0][2] = { acpu_freq_tbl_pvs2, sizeof(acpu_freq_tbl_pvs2) },
+ [0][3] = { acpu_freq_tbl_pvs3, sizeof(acpu_freq_tbl_pvs3) },
+ [0][4] = { acpu_freq_tbl_pvs4, sizeof(acpu_freq_tbl_pvs4) },
+};
+
+static struct pvs_table pvs_v2[NUM_SPEED_BINS][NUM_PVS] __initdata = {
[0][0] = { acpu_freq_tbl_pvs0, sizeof(acpu_freq_tbl_pvs0) },
[0][1] = { acpu_freq_tbl_pvs1, sizeof(acpu_freq_tbl_pvs1) },
[0][2] = { acpu_freq_tbl_pvs2, sizeof(acpu_freq_tbl_pvs2) },
@@ -269,7 +277,7 @@
.scalable = scalable,
.scalable_size = sizeof(scalable),
.hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
+ .pvs_tables = pvs_v2,
.l2_freq_tbl = l2_freq_tbl,
.l2_freq_tbl_size = sizeof(l2_freq_tbl),
.bus_scale = &bus_scale_data,
@@ -278,7 +286,7 @@
.stby_khz = 300000,
};
-static void __init apply_l2_workaround(void)
+static void __init apply_v1_l2_workaround(void)
{
static struct l2_level resticted_l2_tbl[] __initdata = {
[0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 1050000, 0 },
@@ -290,7 +298,7 @@
for (s = 0; s < NUM_SPEED_BINS; s++)
for (p = 0; p < NUM_PVS; p++)
- for (l = pvs_tables[s][p].table; l && l->speed.khz; l++)
+ for (l = pvs_v1[s][p].table; l && l->speed.khz; l++)
l->l2_level = l->l2_level > 5 ? 1 : 0;
acpuclk_8974_params.l2_freq_tbl = resticted_l2_tbl;
@@ -305,9 +313,11 @@
* and 1497.6MHz (non-inclusive), or when vdd_mx is less than 1.05V.
* Restrict L2 operation to safe performance points on these devices.
*/
- if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 2 &&
- SOCINFO_VERSION_MINOR(socinfo_get_version()) < 2)
- apply_l2_workaround();
+ if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) {
+ acpuclk_8974_params.pvs_tables = pvs_v1;
+ if (SOCINFO_VERSION_MINOR(socinfo_get_version()) < 2)
+ apply_v1_l2_workaround();
+ }
return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
}
diff --git a/arch/arm/mach-msm/cpuidle.c b/arch/arm/mach-msm/cpuidle.c
index 1e3f8a0..77c91b8 100644
--- a/arch/arm/mach-msm/cpuidle.c
+++ b/arch/arm/mach-msm/cpuidle.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -77,7 +77,9 @@
struct cpuidle_state_usage *st_usage = NULL;
cpu_pm_enter();
- pm_mode = msm_pm_idle_enter(dev, drv, index);
+
+ pm_mode = msm_pm_idle_prepare(dev, drv, index);
+ dev->last_residency = msm_pm_idle_enter(pm_mode);
for (i = 0; i < dev->state_count; i++) {
st_usage = &dev->states_usage[i];
if ((enum msm_pm_sleep_mode) cpuidle_get_statedata(st_usage)
diff --git a/arch/arm/mach-msm/include/mach/ocmem.h b/arch/arm/mach-msm/include/mach/ocmem.h
index cd70457..92ae6b6 100644
--- a/arch/arm/mach-msm/include/mach/ocmem.h
+++ b/arch/arm/mach-msm/include/mach/ocmem.h
@@ -136,6 +136,9 @@
int ocmem_unmap(int client_id, struct ocmem_buf *buffer,
struct ocmem_map_list *list);
+int ocmem_drop(int client_id, struct ocmem_buf *buffer,
+ struct ocmem_map_list *list);
+
int ocmem_dump(int client_id, struct ocmem_buf *buffer,
unsigned long dst_phys_addr);
diff --git a/arch/arm/mach-msm/include/mach/ocmem_priv.h b/arch/arm/mach-msm/include/mach/ocmem_priv.h
index a4adfb8..abb5653 100644
--- a/arch/arm/mach-msm/include/mach/ocmem_priv.h
+++ b/arch/arm/mach-msm/include/mach/ocmem_priv.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -29,6 +29,16 @@
#define TO_OCMEM 0x0
#define TO_DDR 0x1
+#define OCMEM_SVC_ID 15
+#define OCMEM_LOCK_CMD_ID 0x1
+#define OCMEM_UNLOCK_CMD_ID 0x2
+#define OCMEM_ENABLE_DUMP_CMD_ID 0x3
+#define OCMEM_DISABLE_DUMP_CMD_ID 0x4
+
+#define OCMEM_SECURE_SVC_ID 12
+#define OCMEM_SECURE_CFG_ID 0x2
+#define OCMEM_SECURE_DEV_ID 0x5
+
struct ocmem_zone;
struct ocmem_zone_ops {
@@ -158,6 +168,8 @@
/* Request Power State */
unsigned power_state;
struct ocmem_eviction_data *edata;
+ /* Request that triggered eviction */
+ struct ocmem_req *e_handle;
};
struct ocmem_handle {
@@ -187,6 +199,10 @@
int ocmem_notifier_init(void);
int check_notifier(int);
const char *get_name(int);
+int get_tz_id(int);
+int ocmem_enable_sec_program(int);
+int ocmem_enable_dump(enum ocmem_client, unsigned long, unsigned long);
+int ocmem_disable_dump(enum ocmem_client, unsigned long, unsigned long);
int check_id(int);
int dispatch_notification(int, enum ocmem_notif_type, struct ocmem_buf *);
@@ -197,6 +213,7 @@
unsigned long, bool, bool);
int process_free(int, struct ocmem_handle *);
int process_xfer(int, struct ocmem_handle *, struct ocmem_map_list *, int);
+int process_drop(int, struct ocmem_handle *, struct ocmem_map_list *);
int process_evict(int);
int process_restore(int);
int process_shrink(int, struct ocmem_handle *, unsigned long);
diff --git a/arch/arm/mach-msm/krait-regulator.c b/arch/arm/mach-msm/krait-regulator.c
index 01be641..52aa43a 100644
--- a/arch/arm/mach-msm/krait-regulator.c
+++ b/arch/arm/mach-msm/krait-regulator.c
@@ -894,8 +894,6 @@
/* setup the bandgap that configures the reference to the LDO */
writel_relaxed(0x00000190, kvreg->mdd_base + MDD_CONFIG_CTL);
- /* Enable MDD */
- writel_relaxed(0x00000002, kvreg->mdd_base + MDD_MODE);
mb();
}
diff --git a/arch/arm/mach-msm/lpm_levels.c b/arch/arm/mach-msm/lpm_levels.c
index 8571bda..dec62f0 100644
--- a/arch/arm/mach-msm/lpm_levels.c
+++ b/arch/arm/mach-msm/lpm_levels.c
@@ -57,6 +57,8 @@
bool from_idle, bool notify_rpm)
{
int ret = 0;
+ int debug_mask;
+ struct msm_rpmrs_limits *l = (struct msm_rpmrs_limits *)limits;
struct msm_lpm_sleep_data sleep_data;
sleep_data.limits = limits;
@@ -64,34 +66,28 @@
atomic_notifier_call_chain(&__get_cpu_var(lpm_notify_head),
MSM_LPM_STATE_ENTER, &sleep_data);
- if (notify_rpm) {
- int debug_mask;
- struct msm_rpmrs_limits *l = (struct msm_rpmrs_limits *)limits;
-
- ret = msm_rpm_enter_sleep();
- if (ret) {
- pr_warn("%s(): RPM failed to enter sleep err:%d\n",
- __func__, ret);
- goto bail;
- }
- if (from_idle)
- debug_mask = msm_lpm_lvl_dbg_msk &
- MSM_LPM_LVL_DBG_IDLE_LIMITS;
- else
- debug_mask = msm_lpm_lvl_dbg_msk &
- MSM_LPM_LVL_DBG_SUSPEND_LIMITS;
-
- if (debug_mask)
- pr_info("%s(): pxo:%d l2:%d mem:0x%x(0x%x) dig:0x%x(0x%x)\n",
- __func__, l->pxo, l->l2_cache,
- l->vdd_mem_lower_bound,
- l->vdd_mem_upper_bound,
- l->vdd_dig_lower_bound,
- l->vdd_dig_upper_bound);
-
- ret = msm_lpmrs_enter_sleep(sclk_count, l, from_idle,
- notify_rpm);
+ ret = msm_rpm_enter_sleep();
+ if (ret) {
+ pr_warn("%s(): RPM failed to enter sleep err:%d\n",
+ __func__, ret);
+ goto bail;
}
+ if (from_idle)
+ debug_mask = msm_lpm_lvl_dbg_msk &
+ MSM_LPM_LVL_DBG_IDLE_LIMITS;
+ else
+ debug_mask = msm_lpm_lvl_dbg_msk &
+ MSM_LPM_LVL_DBG_SUSPEND_LIMITS;
+
+ if (debug_mask)
+ pr_info("%s(): pxo:%d l2:%d mem:0x%x(0x%x) dig:0x%x(0x%x)\n",
+ __func__, l->pxo, l->l2_cache,
+ l->vdd_mem_lower_bound,
+ l->vdd_mem_upper_bound,
+ l->vdd_dig_lower_bound,
+ l->vdd_dig_upper_bound);
+
+ ret = msm_lpmrs_enter_sleep(sclk_count, l, from_idle, notify_rpm);
bail:
return ret;
}
diff --git a/arch/arm/mach-msm/no-pm.c b/arch/arm/mach-msm/no-pm.c
index a8d4fdb..0db6e68 100644
--- a/arch/arm/mach-msm/no-pm.c
+++ b/arch/arm/mach-msm/no-pm.c
@@ -37,11 +37,15 @@
void msm_pm_set_irq_extns(struct msm_pm_irq_calls *irq_calls) {}
-enum msm_pm_sleep_mode msm_pm_idle_enter(struct cpuidle_device *dev,
+int msm_pm_idle_prepare(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
return -ENOSYS;
}
-void msm_pm_enable_retention(bool enable) {}
+int msm_pm_idle_enter(enum msm_pm_sleep_mode sleep_mode)
+{
+ return -ENOSYS;
+}
+void msm_pm_enable_retention(bool enable) {}
diff --git a/arch/arm/mach-msm/ocmem.c b/arch/arm/mach-msm/ocmem.c
index 1729742..4685f02 100644
--- a/arch/arm/mach-msm/ocmem.c
+++ b/arch/arm/mach-msm/ocmem.c
@@ -693,7 +693,7 @@
}
/* Enable the ocmem graphics mpU as a workaround */
-/* This will be programmed by TZ after TZ support is integrated */
+#ifdef CONFIG_MSM_OCMEM_NONSECURE
static int ocmem_init_gfx_mpu(struct platform_device *pdev)
{
int rc;
@@ -714,6 +714,12 @@
ocmem_disable_core_clock();
return 0;
}
+#else
+static int ocmem_init_gfx_mpu(struct platform_device *pdev)
+{
+ return 0;
+}
+#endif /* CONFIG_MSM_OCMEM_NONSECURE */
static int __devinit ocmem_debugfs_init(struct platform_device *pdev)
{
@@ -783,6 +789,11 @@
platform_set_drvdata(pdev, ocmem_pdata);
+ /* Parameter to be updated based on TZ */
+ /* Allow the OCMEM CSR to be programmed */
+ if (ocmem_enable_sec_program(OCMEM_SECURE_DEV_ID))
+ return -EBUSY;
+
if (ocmem_debugfs_init(pdev))
return -EBUSY;
diff --git a/arch/arm/mach-msm/ocmem_api.c b/arch/arm/mach-msm/ocmem_api.c
index ef3cbae..16dd8b8 100644
--- a/arch/arm/mach-msm/ocmem_api.c
+++ b/arch/arm/mach-msm/ocmem_api.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -52,9 +52,10 @@
ret = process_free(id, handle);
mutex_unlock(&handle->handle_mutex);
- if (ret)
- return -EINVAL;
-
+ if (ret) {
+ pr_err("ocmem: Free failed for client %s\n", get_name(id));
+ return ret;
+ }
free_handle(handle);
return 0;
}
@@ -400,6 +401,40 @@
}
EXPORT_SYMBOL(ocmem_unmap);
+int ocmem_drop(int client_id, struct ocmem_buf *buffer,
+ struct ocmem_map_list *list)
+{
+ int ret = 0;
+ struct ocmem_handle *handle = NULL;
+
+ if (!check_id(client_id)) {
+ pr_err("ocmem: Invalid client id: %d\n", client_id);
+ return -EINVAL;
+ }
+
+ if (!zone_active(client_id)) {
+ pr_err("ocmem: Client id: %s (id: %d) not allowed to use OCMEM\n",
+ get_name(client_id), client_id);
+ return -EINVAL;
+ }
+
+ if (!buffer) {
+ pr_err("ocmem: Invalid buffer\n");
+ return -EINVAL;
+ }
+
+ if (pre_validate_chunk_list(list) != 0)
+ return -EINVAL;
+
+ handle = buffer_to_handle(buffer);
+ mutex_lock(&handle->handle_mutex);
+ ret = process_drop(client_id, handle, list);
+ mutex_unlock(&handle->handle_mutex);
+ return ret;
+}
+EXPORT_SYMBOL(ocmem_drop);
+
+
int ocmem_dump(int client_id, struct ocmem_buf *buffer,
unsigned long dst_phys_addr)
{
diff --git a/arch/arm/mach-msm/ocmem_core.c b/arch/arm/mach-msm/ocmem_core.c
index a011576..4ea1de9 100644
--- a/arch/arm/mach-msm/ocmem_core.c
+++ b/arch/arm/mach-msm/ocmem_core.c
@@ -17,6 +17,7 @@
#include <mach/ocmem_priv.h>
#include <mach/rpm-smd.h>
+#include <mach/scm.h>
static unsigned num_regions;
static unsigned num_macros;
@@ -514,6 +515,23 @@
ocmem_clear(offset, len);
return 0;
}
+
+int ocmem_enable_sec_program(int sec_id)
+{
+ return 0;
+}
+
+int ocmem_enable_dump(enum ocmem_client id, unsigned long offset,
+ unsigned long len)
+{
+ return 0;
+}
+
+int ocmem_disable_dump(enum ocmem_client id, unsigned long offset,
+ unsigned long len)
+{
+ return 0;
+}
#else
static int ocmem_gfx_mpu_set(unsigned long offset, unsigned long len)
{
@@ -532,19 +550,117 @@
static int do_lock(enum ocmem_client id, unsigned long offset,
unsigned long len, enum region_mode mode)
{
- return 0;
+ int rc;
+ struct ocmem_tz_lock {
+ u32 id;
+ u32 offset;
+ u32 size;
+ } request;
+
+ request.id = get_tz_id(id);
+ request.offset = offset;
+ request.size = len;
+
+ rc = scm_call(OCMEM_SVC_ID, OCMEM_LOCK_CMD_ID, &request,
+ sizeof(request), NULL, 0);
+ if (rc)
+ pr_err("ocmem: Failed to lock region %s[%lx -- %lx] ret = %d\n",
+ get_name(id), offset, offset + len - 1, rc);
+ return rc;
}
static int do_unlock(enum ocmem_client id, unsigned long offset,
unsigned long len)
{
- return 0;
+ int rc;
+ struct ocmem_tz_unlock {
+ u32 id;
+ u32 offset;
+ u32 size;
+ } request;
+
+ request.id = get_tz_id(id);
+ request.offset = offset;
+ request.size = len;
+
+ rc = scm_call(OCMEM_SVC_ID, OCMEM_UNLOCK_CMD_ID, &request,
+ sizeof(request), NULL, 0);
+ if (rc)
+ pr_err("ocmem: Failed to unlock region %s[%lx -- %lx] ret = %d\n",
+ get_name(id), offset, offset + len - 1, rc);
+ return rc;
+}
+
+int ocmem_enable_dump(enum ocmem_client id, unsigned long offset,
+ unsigned long len)
+{
+ int rc;
+ struct ocmem_tz_en_dump {
+ u32 id;
+ u32 offset;
+ u32 size;
+ } request;
+
+ request.id = get_tz_id(id);
+ request.offset = offset;
+ request.size = len;
+
+ rc = scm_call(OCMEM_SVC_ID, OCMEM_ENABLE_DUMP_CMD_ID, &request,
+ sizeof(request), NULL, 0);
+ if (rc)
+ pr_err("ocmem: Failed to enable dump %s[%lx -- %lx] ret = %d\n",
+ get_name(id), offset, offset + len - 1, rc);
+ return rc;
+}
+
+int ocmem_disable_dump(enum ocmem_client id, unsigned long offset,
+ unsigned long len)
+{
+ int rc;
+ struct ocmem_tz_dis_dump {
+ u32 id;
+ u32 offset;
+ u32 size;
+ } request;
+
+ request.id = get_tz_id(id);
+ request.offset = offset;
+ request.size = len;
+
+ rc = scm_call(OCMEM_SVC_ID, OCMEM_DISABLE_DUMP_CMD_ID, &request,
+ sizeof(request), NULL, 0);
+ if (rc)
+ pr_err("ocmem: Failed to disable dump %s[%lx -- %lx] ret = %d\n",
+ get_name(id), offset, offset + len - 1, rc);
+ return rc;
+}
+
+int ocmem_enable_sec_program(int sec_id)
+{
+ int rc, scm_ret = 0;
+ struct msm_scm_sec_cfg {
+ unsigned int id;
+ unsigned int spare;
+ } cfg;
+
+ cfg.id = sec_id;
+
+ rc = scm_call(OCMEM_SECURE_SVC_ID, OCMEM_SECURE_CFG_ID, &cfg,
+ sizeof(cfg), &scm_ret, sizeof(scm_ret));
+
+ if (rc || scm_ret) {
+ pr_err("ocmem: Failed to enable secure programming\n");
+ return rc ? rc : -EINVAL;
+ }
+
+ return rc;
}
#endif /* CONFIG_MSM_OCMEM_NONSECURE */
int ocmem_lock(enum ocmem_client id, unsigned long offset, unsigned long len,
enum region_mode mode)
{
+ int rc = 0;
if (len < OCMEM_MIN_ALLOC) {
pr_err("ocmem: Invalid len %lx for lock\n", len);
@@ -561,27 +677,38 @@
commit_region_modes();
- do_lock(id, offset, len, mode);
+ rc = do_lock(id, offset, len, mode);
+ if (rc)
+ goto lock_fail;
mutex_unlock(®ion_ctrl_lock);
return 0;
-
+lock_fail:
+ switch_region_mode(offset, len, MODE_DEFAULT);
switch_region_fail:
+ ocmem_gfx_mpu_remove();
mutex_unlock(®ion_ctrl_lock);
return -EINVAL;
}
int ocmem_unlock(enum ocmem_client id, unsigned long offset, unsigned long len)
{
+ int rc = 0;
+
if (id == OCMEM_GRAPHICS)
ocmem_gfx_mpu_remove();
mutex_lock(®ion_ctrl_lock);
- do_unlock(id, offset, len);
+ rc = do_unlock(id, offset, len);
+ if (rc)
+ goto unlock_fail;
switch_region_mode(offset, len , MODE_DEFAULT);
commit_region_modes();
mutex_unlock(®ion_ctrl_lock);
return 0;
+unlock_fail:
+ mutex_unlock(®ion_ctrl_lock);
+ return -EINVAL;
}
#if defined(CONFIG_MSM_OCMEM_POWER_DISABLE)
diff --git a/arch/arm/mach-msm/ocmem_rdm.c b/arch/arm/mach-msm/ocmem_rdm.c
index c0603d6..4190aea 100644
--- a/arch/arm/mach-msm/ocmem_rdm.c
+++ b/arch/arm/mach-msm/ocmem_rdm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -296,10 +296,6 @@
init_completion(&dm_clear_event);
init_completion(&dm_transfer_event);
- /* Clear DM Mask */
- ocmem_write(DM_MASK_RESET, dm_base + DM_INTR_MASK);
- /* enable dm interrupts */
- ocmem_write(DM_INTR_RESET, dm_base + DM_INTR_CLR);
ocmem_disable_core_clock();
return 0;
}
diff --git a/arch/arm/mach-msm/ocmem_sched.c b/arch/arm/mach-msm/ocmem_sched.c
index 08f93e2..868fd1a 100644
--- a/arch/arm/mach-msm/ocmem_sched.c
+++ b/arch/arm/mach-msm/ocmem_sched.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -25,16 +25,19 @@
#include <mach/ocmem_priv.h>
enum request_states {
- R_FREE = 0x0, /* request is not allocated */
- R_PENDING, /* request has a pending operation */
- R_ALLOCATED, /* request has been allocated */
- R_MUST_GROW, /* request must grow as a part of pending operation */
- R_MUST_SHRINK, /* request must shrink as a part of pending operation */
- R_MUST_MAP, /* request must be mapped before being used */
- R_MUST_UNMAP, /* request must be unmapped when not being used */
- R_MAPPED, /* request is mapped and actively used by client */
- R_UNMAPPED, /* request is not mapped, so it's not in active use */
- R_EVICTED, /* request is evicted and must be restored */
+ R_FREE = 0x0, /* request is not allocated */
+ R_PENDING, /* request has a pending operation */
+ R_ALLOCATED, /* request has been allocated */
+ R_ENQUEUED, /* request has been enqueued for future retry */
+ R_MUST_GROW, /* request must grow as a part of pending operation */
+ R_MUST_SHRINK, /* request must shrink */
+ R_WF_SHRINK, /* shrink must be ack'ed by a client */
+ R_SHRUNK, /* request was shrunk */
+ R_MUST_MAP, /* request must be mapped before being used */
+ R_MUST_UNMAP, /* request must be unmapped when not being used */
+ R_MAPPED, /* request is mapped and actively used by client */
+ R_UNMAPPED, /* request is not mapped, so it's not in active use */
+ R_EVICTED, /* request is evicted and must be restored */
};
#define SET_STATE(x, val) (set_bit((val), &(x)->state))
@@ -109,6 +112,16 @@
OCMEM_SYSNOC = 3,
};
+enum ocmem_tz_client {
+ TZ_UNUSED = 0x0,
+ TZ_GRAPHICS,
+ TZ_VIDEO,
+ TZ_LP_AUDIO,
+ TZ_SENSORS,
+ TZ_OTHER_OS,
+ TZ_DEBUG,
+};
+
/**
* Primary OCMEM Arbitration Table
**/
@@ -117,20 +130,30 @@
int priority;
int mode;
int hw_interconnect;
+ int tz_id;
} ocmem_client_table[OCMEM_CLIENT_MAX] = {
- {OCMEM_GRAPHICS, PRIO_GFX, OCMEM_PERFORMANCE, OCMEM_PORT},
- {OCMEM_VIDEO, PRIO_VIDEO, OCMEM_PERFORMANCE, OCMEM_OCMEMNOC},
- {OCMEM_CAMERA, NO_PRIO, OCMEM_PERFORMANCE, OCMEM_OCMEMNOC},
- {OCMEM_HP_AUDIO, PRIO_HP_AUDIO, OCMEM_PASSIVE, OCMEM_BLOCKED},
- {OCMEM_VOICE, PRIO_VOICE, OCMEM_PASSIVE, OCMEM_BLOCKED},
- {OCMEM_LP_AUDIO, PRIO_LP_AUDIO, OCMEM_LOW_POWER, OCMEM_SYSNOC},
- {OCMEM_SENSORS, PRIO_SENSORS, OCMEM_LOW_POWER, OCMEM_SYSNOC},
- {OCMEM_OTHER_OS, PRIO_OTHER_OS, OCMEM_LOW_POWER, OCMEM_SYSNOC},
+ {OCMEM_GRAPHICS, PRIO_GFX, OCMEM_PERFORMANCE, OCMEM_PORT,
+ TZ_GRAPHICS},
+ {OCMEM_VIDEO, PRIO_VIDEO, OCMEM_PERFORMANCE, OCMEM_OCMEMNOC,
+ TZ_VIDEO},
+ {OCMEM_CAMERA, NO_PRIO, OCMEM_PERFORMANCE, OCMEM_OCMEMNOC,
+ TZ_UNUSED},
+ {OCMEM_HP_AUDIO, PRIO_HP_AUDIO, OCMEM_PASSIVE, OCMEM_BLOCKED,
+ TZ_UNUSED},
+ {OCMEM_VOICE, PRIO_VOICE, OCMEM_PASSIVE, OCMEM_BLOCKED,
+ TZ_UNUSED},
+ {OCMEM_LP_AUDIO, PRIO_LP_AUDIO, OCMEM_LOW_POWER, OCMEM_SYSNOC,
+ TZ_LP_AUDIO},
+ {OCMEM_SENSORS, PRIO_SENSORS, OCMEM_LOW_POWER, OCMEM_SYSNOC,
+ TZ_SENSORS},
+ {OCMEM_OTHER_OS, PRIO_OTHER_OS, OCMEM_LOW_POWER, OCMEM_SYSNOC,
+ TZ_OTHER_OS},
};
static struct rb_root sched_tree;
static struct mutex sched_mutex;
static struct mutex allocation_mutex;
+static struct mutex free_mutex;
/* A region represents a continuous interval in OCMEM address space */
struct ocmem_region {
@@ -225,6 +248,14 @@
WIDE_MODE : THIN_MODE;
}
+inline int get_tz_id(int id)
+{
+ if (!check_id(id))
+ return TZ_UNUSED;
+ else
+ return ocmem_client_table[id].tz_id;
+}
+
/* Returns the address that can be used by a device core to access OCMEM */
static unsigned long device_address(int id, unsigned long addr)
{
@@ -489,12 +520,21 @@
return TEST_STATE(req, R_MAPPED);
}
+static inline int is_pending_shrink(struct ocmem_req *req)
+{
+ return TEST_STATE(req, R_MUST_SHRINK) ||
+ TEST_STATE(req, R_WF_SHRINK);
+}
+
/* Must be called with sched_mutex held */
static int __sched_unmap(struct ocmem_req *req)
{
struct ocmem_req *matched_req = NULL;
struct ocmem_region *matched_region = NULL;
+ if (!TEST_STATE(req, R_MAPPED))
+ goto invalid_op_error;
+
matched_region = find_region_match(req->req_start, req->req_end);
matched_req = find_req_match(req->req_id, matched_region);
@@ -1024,8 +1064,8 @@
retry = false;
- pr_debug("ocmem: do_allocate: %s request size %lx\n",
- get_name(owner), sz);
+ pr_debug("ocmem: do_allocate: %s request %p size %lx\n",
+ get_name(owner), req, sz);
retry_next_step:
@@ -1146,14 +1186,34 @@
return OP_FAIL;
}
+/* Remove the request from eviction lists */
+static void cancel_restore(struct ocmem_req *e_handle,
+ struct ocmem_req *req)
+{
+ struct ocmem_eviction_data *edata = e_handle->edata;
+
+ if (!edata || !req)
+ return;
+
+ if (list_empty(&edata->req_list))
+ return;
+
+ list_del_init(&req->eviction_list);
+ req->e_handle = NULL;
+
+ return;
+}
+
static int sched_enqueue(struct ocmem_req *priv)
{
struct ocmem_req *next = NULL;
mutex_lock(&sched_queue_mutex);
+ SET_STATE(priv, R_ENQUEUED);
list_add_tail(&priv->sched_list, &sched_queue[priv->owner]);
pr_debug("enqueued req %p\n", priv);
list_for_each_entry(next, &sched_queue[priv->owner], sched_list) {
- pr_debug("pending requests for client %p\n", next);
+ pr_debug("pending request %p for client %s\n", next,
+ get_name(next->owner));
}
mutex_unlock(&sched_queue_mutex);
return 0;
@@ -1178,13 +1238,13 @@
list_for_each_entry_safe(req, next, &sched_queue[id], sched_list)
{
if (req == victim_req) {
- pr_debug("ocmem: Cancelling pending request %p\n",
- req);
- list_del(&req->sched_list);
- goto dequeue_done;
+ pr_debug("ocmem: Cancelling pending request %p for %s\n",
+ req, get_name(req->owner));
+ list_del_init(&victim_req->sched_list);
+ CLEAR_STATE(victim_req, R_ENQUEUED);
+ break;
}
}
-
dequeue_done:
mutex_unlock(&sched_queue_mutex);
return;
@@ -1206,7 +1266,8 @@
pr_debug("ocmem: Fetched pending request %p\n",
req);
list_del(&req->sched_list);
- break;
+ CLEAR_STATE(req, R_ENQUEUED);
+ break;
}
}
}
@@ -1400,31 +1461,67 @@
unsigned long offset = 0;
int rc = 0;
+ mutex_lock(&free_mutex);
+
if (is_blocked(id)) {
pr_err("Client %d cannot request free\n", id);
- return -EINVAL;
+ goto free_invalid;
}
req = handle_to_req(handle);
buffer = handle_to_buffer(handle);
- if (!req)
- return -EINVAL;
+ if (!req) {
+ pr_err("ocmem: No valid request to free\n");
+ goto free_invalid;
+ }
if (req->req_start != core_address(id, buffer->addr)) {
pr_err("Invalid buffer handle passed for free\n");
- return -EINVAL;
+ goto free_invalid;
}
- mutex_lock(&sched_mutex);
- sched_dequeue(req);
- mutex_unlock(&sched_mutex);
+ if (req->edata != NULL) {
+ pr_err("ocmem: Request %p(%2lx) yet to process eviction %p\n",
+ req, req->state, req->edata);
+ goto free_invalid;
+ }
- if (TEST_STATE(req, R_MAPPED)) {
- /* unmap the interval and clear the memory */
- rc = process_unmap(req, req->req_start, req->req_end);
- if (rc < 0)
- return -EINVAL;
+ if (is_pending_shrink(req)) {
+ pr_err("ocmem: Request %p(%2lx) yet to process eviction\n",
+ req, req->state);
+ goto pending_shrink;
+ }
+
+ /* Remove the request from any restore lists */
+ if (req->e_handle)
+ cancel_restore(req->e_handle, req);
+
+ /* Remove the request from any pending opreations */
+ if (TEST_STATE(req, R_ENQUEUED)) {
+ mutex_lock(&sched_mutex);
+ sched_dequeue(req);
+ mutex_unlock(&sched_mutex);
+ }
+
+ if (!TEST_STATE(req, R_FREE)) {
+
+ if (TEST_STATE(req, R_MAPPED)) {
+ /* unmap the interval and clear the memory */
+ rc = process_unmap(req, req->req_start, req->req_end);
+
+ if (rc < 0) {
+ pr_err("ocmem: Failed to unmap %p\n", req);
+ goto free_fail;
+ }
+
+ rc = do_free(req);
+ if (rc < 0) {
+ pr_err("ocmem: Failed to free %p\n", req);
+ goto free_fail;
+ }
+ } else
+ pr_debug("request %p was already shrunk to 0\n", req);
}
/* Turn off the memory */
@@ -1436,7 +1533,7 @@
if (rc < 0) {
pr_err("Failed to switch OFF memory macros\n");
- return -EINVAL;
+ goto free_fail;
}
}
@@ -1454,7 +1551,15 @@
handle->req = NULL;
ocmem_schedule_pending();
+ mutex_unlock(&free_mutex);
return 0;
+free_fail:
+free_invalid:
+ mutex_unlock(&free_mutex);
+ return -EINVAL;
+pending_shrink:
+ mutex_unlock(&free_mutex);
+ return -EAGAIN;
}
static void ocmem_rdm_worker(struct work_struct *work)
@@ -1504,6 +1609,42 @@
return 0;
}
+int process_drop(int id, struct ocmem_handle *handle,
+ struct ocmem_map_list *list)
+{
+ struct ocmem_req *req = NULL;
+ struct ocmem_buf *buffer = NULL;
+ int rc = 0;
+
+ if (is_blocked(id)) {
+ pr_err("Client %d cannot request drop\n", id);
+ return -EINVAL;
+ }
+
+ if (is_tcm(id))
+ pr_err("Client %d cannot request drop\n", id);
+
+ req = handle_to_req(handle);
+ buffer = handle_to_buffer(handle);
+
+ if (!req)
+ return -EINVAL;
+
+ if (req->req_start != core_address(id, buffer->addr)) {
+ pr_err("Invalid buffer handle passed for drop\n");
+ return -EINVAL;
+ }
+
+ if (TEST_STATE(req, R_MAPPED)) {
+ rc = process_unmap(req, req->req_start, req->req_end);
+ if (rc < 0)
+ return -EINVAL;
+ } else
+ return -EINVAL;
+
+ return 0;
+}
+
int process_xfer_out(int id, struct ocmem_handle *handle,
struct ocmem_map_list *list)
{
@@ -1552,7 +1693,6 @@
goto transfer_in_error;
}
-
inc_ocmem_stat(zone_of(req), NR_TRANSFERS_TO_OCMEM);
rc = queue_transfer(req, handle, list, TO_OCMEM);
@@ -1585,16 +1725,23 @@
if (!req)
return -EINVAL;
+ mutex_lock(&free_mutex);
+
if (req->req_start != core_address(id, buffer->addr)) {
pr_err("Invalid buffer handle passed for shrink\n");
- return -EINVAL;
+ goto shrink_fail;
}
- edata = req->edata;
+ if (!req->e_handle) {
+ pr_err("Unable to find evicting request\n");
+ goto shrink_fail;
+ }
+
+ edata = req->e_handle->edata;
if (!edata) {
pr_err("Unable to find eviction data\n");
- return -EINVAL;
+ goto shrink_fail;
}
pr_debug("Found edata %p in request %p\n", edata, req);
@@ -1603,29 +1750,37 @@
if (size == 0) {
pr_debug("req %p being shrunk to zero\n", req);
- if (is_mapped(req))
+ if (is_mapped(req)) {
rc = process_unmap(req, req->req_start, req->req_end);
if (rc < 0)
- return -EINVAL;
+ goto shrink_fail;
+ }
rc = do_free(req);
if (rc < 0)
- return -EINVAL;
+ goto shrink_fail;
+ SET_STATE(req, R_FREE);
} else {
rc = do_shrink(req, size);
if (rc < 0)
- return -EINVAL;
+ goto shrink_fail;
}
- req->edata = NULL;
CLEAR_STATE(req, R_ALLOCATED);
- SET_STATE(req, R_FREE);
+ CLEAR_STATE(req, R_WF_SHRINK);
+ SET_STATE(req, R_SHRUNK);
if (atomic_dec_and_test(&edata->pending)) {
pr_debug("ocmem: All conflicting allocations were shrunk\n");
complete(&edata->completion);
}
+ mutex_unlock(&free_mutex);
return 0;
+shrink_fail:
+ pr_err("ocmem: Failed to shrink request %p of %s\n",
+ req, get_name(req->owner));
+ mutex_unlock(&free_mutex);
+ return -EINVAL;
}
int process_xfer(int id, struct ocmem_handle *handle,
@@ -1730,11 +1885,12 @@
if (needs_eviction) {
pr_debug("adding %p in region %p to eviction list\n",
e_req, tmp_region);
+ SET_STATE(e_req, R_MUST_SHRINK);
list_add_tail(
&e_req->eviction_list,
&edata->req_list);
atomic_inc(&edata->pending);
- e_req->edata = edata;
+ e_req->e_handle = req;
}
}
} else {
@@ -1744,9 +1900,7 @@
pr_debug("%d requests will be evicted\n", atomic_read(&edata->pending));
- if (!atomic_read(&edata->pending))
- return -EINVAL;
- return 0;
+ return atomic_read(&edata->pending);
}
static void trigger_eviction(struct ocmem_eviction_data *edata)
@@ -1768,8 +1922,10 @@
pr_debug("ocmem: Evicting request %p\n", req);
buffer.addr = req->req_start;
buffer.len = 0x0;
+ CLEAR_STATE(req, R_MUST_SHRINK);
dispatch_notification(req->owner, OCMEM_ALLOC_SHRINK,
&buffer);
+ SET_STATE(req, R_WF_SHRINK);
}
}
return;
@@ -1791,7 +1947,7 @@
rc = __evict_common(edata, NULL);
- if (rc < 0)
+ if (rc == 0)
goto skip_eviction;
trigger_eviction(edata);
@@ -1825,9 +1981,10 @@
edata->passive = false;
+ mutex_lock(&free_mutex);
rc = __evict_common(edata, req);
- if (rc < 0)
+ if (rc == 0)
goto skip_eviction;
trigger_eviction(edata);
@@ -1835,6 +1992,8 @@
pr_debug("ocmem: attaching eviction %p to request %p", edata, req);
req->edata = edata;
+ mutex_unlock(&free_mutex);
+
wait_for_completion(&edata->completion);
pr_debug("ocmem: eviction completed successfully\n");
@@ -1843,28 +2002,30 @@
skip_eviction:
pr_err("ocmem: Unable to run eviction\n");
free_eviction(edata);
- return -EINVAL;
+ req->edata = NULL;
+ mutex_unlock(&free_mutex);
+ return 0;
}
static int __restore_common(struct ocmem_eviction_data *edata)
{
struct ocmem_req *req = NULL;
- struct ocmem_req *next = NULL;
if (!edata)
return -EINVAL;
- list_for_each_entry_safe(req, next, &edata->req_list, eviction_list)
- {
- if (req) {
- pr_debug("ocmem: restoring evicted request %p\n",
- req);
- list_del(&req->eviction_list);
- req->op = SCHED_ALLOCATE;
- sched_enqueue(req);
- inc_ocmem_stat(zone_of(req), NR_RESTORES);
- }
+ while (!list_empty(&edata->req_list)) {
+ req = list_first_entry(&edata->req_list, struct ocmem_req,
+ eviction_list);
+ list_del_init(&req->eviction_list);
+ pr_debug("ocmem: restoring evicted request %p\n",
+ req);
+ req->edata = NULL;
+ req->e_handle = NULL;
+ req->op = SCHED_ALLOCATE;
+ inc_ocmem_stat(zone_of(req), NR_RESTORES);
+ sched_enqueue(req);
}
pr_debug("Scheduled all evicted regions\n");
@@ -1883,12 +2044,15 @@
if (!req->edata)
return 0;
+ mutex_lock(&free_mutex);
rc = __restore_common(req->edata);
+ mutex_unlock(&free_mutex);
if (rc < 0)
return -EINVAL;
free_eviction(req->edata);
+ req->edata = NULL;
return 0;
}
@@ -1900,7 +2064,9 @@
if (!edata)
return -EINVAL;
+ mutex_lock(&free_mutex);
rc = __restore_common(edata);
+ mutex_unlock(&free_mutex);
if (rc < 0) {
pr_err("Failed to restore evicted requests\n");
@@ -1986,6 +2152,7 @@
void __iomem *req_vaddr;
unsigned long offset = 0x0;
+ int rc = 0;
down_write(&req->rw_sem);
@@ -1996,12 +2163,23 @@
if (!req_vaddr)
goto err_do_dump;
+ rc = ocmem_enable_dump(req->owner, offset, req->req_sz);
+
+ if (rc < 0)
+ goto err_do_dump;
+
pr_debug("Dumping client %s buffer ocmem p: %lx (v: %p) to ddr %lx\n",
get_name(req->owner), req->req_start,
req_vaddr, addr);
memcpy((void *)addr, req_vaddr, req->req_sz);
+ rc = ocmem_disable_dump(req->owner, offset, req->req_sz);
+
+ if (rc < 0)
+ pr_err("Failed to secure request %p of %s after dump\n",
+ req, get_name(req->owner));
+
up_write(&req->rw_sem);
return 0;
err_do_dump:
@@ -2252,6 +2430,7 @@
sched_tree = RB_ROOT;
pdata = platform_get_drvdata(pdev);
mutex_init(&allocation_mutex);
+ mutex_init(&free_mutex);
mutex_init(&sched_mutex);
mutex_init(&sched_queue_mutex);
ocmem_vaddr = pdata->vbase;
diff --git a/arch/arm/mach-msm/pil-q6v5-mss.c b/arch/arm/mach-msm/pil-q6v5-mss.c
index e85831a..c1d4ab4 100644
--- a/arch/arm/mach-msm/pil-q6v5-mss.c
+++ b/arch/arm/mach-msm/pil-q6v5-mss.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -24,7 +24,6 @@
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <linux/interrupt.h>
-#include <linux/of_gpio.h>
#include <mach/subsystem_restart.h>
#include <mach/clk.h>
@@ -88,8 +87,6 @@
bool crash_shutdown;
bool ignore_errors;
int is_loadable;
- int err_fatal_irq;
- int force_stop_gpio;
};
static int pbl_mba_boot_timeout_ms = 100;
@@ -445,17 +442,18 @@
subsystem_restart_dev(drv->subsys);
}
-static irqreturn_t modem_err_fatal_intr_handler(int irq, void *dev_id)
+static void smsm_state_cb(void *data, uint32_t old_state, uint32_t new_state)
{
- struct mba_data *drv = dev_id;
+ struct mba_data *drv = data;
- /* Ignore if we're the one that set the force stop GPIO */
+ /* Ignore if we're the one that set SMSM_RESET */
if (drv->crash_shutdown)
- return IRQ_HANDLED;
+ return;
- pr_err("Fatal error on the modem.\n");
- restart_modem(drv);
- return IRQ_HANDLED;
+ if (new_state & SMSM_RESET) {
+ pr_err("Probable fatal error on the modem.\n");
+ restart_modem(drv);
+ }
}
static int modem_shutdown(const struct subsys_desc *subsys)
@@ -495,7 +493,7 @@
{
struct mba_data *drv = subsys_to_drv(subsys);
drv->crash_shutdown = true;
- gpio_set_value(drv->force_stop_gpio, 1);
+ smsm_reset_modem(SMSM_RESET);
}
static struct ramdump_segment smem_segments[] = {
@@ -632,11 +630,10 @@
goto err_irq;
}
- ret = devm_request_irq(&pdev->dev, drv->err_fatal_irq,
- modem_err_fatal_intr_handler,
- IRQF_TRIGGER_RISING, "pil-mss", drv);
+ ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
+ smsm_state_cb, drv);
if (ret < 0) {
- dev_err(&pdev->dev, "Unable to register SMP2P err fatal handler!\n");
+ dev_err(&pdev->dev, "Unable to register SMSM callback!\n");
goto err_irq;
}
@@ -646,11 +643,14 @@
ret = PTR_ERR(drv->adsp_state_notifier);
dev_err(&pdev->dev, "%s: Registration with the SSR notification driver failed (%d)",
__func__, ret);
- goto err_irq;
+ goto err_smsm;
}
return 0;
+err_smsm:
+ smsm_state_cb_deregister(SMSM_MODEM_STATE, SMSM_RESET, smsm_state_cb,
+ drv);
err_irq:
destroy_ramdump_device(drv->smem_ramdump_dev);
err_ramdump_smem:
@@ -759,7 +759,7 @@
static int __devinit pil_mss_driver_probe(struct platform_device *pdev)
{
struct mba_data *drv;
- int ret, err_fatal_gpio;
+ int ret;
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
@@ -774,22 +774,6 @@
return ret;
}
- /* Get the IRQ from the GPIO for registering inbound handler */
- err_fatal_gpio = of_get_named_gpio(pdev->dev.of_node,
- "qcom,gpio-err-fatal", 0);
- if (err_fatal_gpio < 0)
- return err_fatal_gpio;
-
- drv->err_fatal_irq = gpio_to_irq(err_fatal_gpio);
- if (drv->err_fatal_irq < 0)
- return drv->err_fatal_irq;
-
- /* Get the GPIO pin for writing the outbound bits: add more as needed */
- drv->force_stop_gpio = of_get_named_gpio(pdev->dev.of_node,
- "qcom,gpio-force-stop", 0);
- if (drv->force_stop_gpio < 0)
- return drv->force_stop_gpio;
-
return pil_subsys_init(drv, pdev);
}
@@ -799,6 +783,8 @@
subsys_notif_unregister_notifier(drv->adsp_state_notifier,
&adsp_state_notifier_block);
+ smsm_state_cb_deregister(SMSM_MODEM_STATE, SMSM_RESET,
+ smsm_state_cb, drv);
subsys_unregister(drv->subsys);
destroy_ramdump_device(drv->smem_ramdump_dev);
destroy_ramdump_device(drv->ramdump_dev);
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
index f7f2fef..0b08238 100644
--- a/arch/arm/mach-msm/pm-8x60.c
+++ b/arch/arm/mach-msm/pm-8x60.c
@@ -479,6 +479,8 @@
}
}
+static void *msm_pm_idle_rs_limits;
+
static void msm_pm_swfi(void)
{
msm_pm_config_hw_before_swfi();
@@ -763,9 +765,8 @@
}
}
-static int msm_pm_idle_prepare(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index,
- void **msm_pm_idle_rs_limits)
+int msm_pm_idle_prepare(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
{
int i;
unsigned int power_usage = -1;
@@ -792,6 +793,7 @@
struct cpuidle_state_usage *st_usage = &dev->states_usage[i];
enum msm_pm_sleep_mode mode;
bool allow;
+ void *rs_limits = NULL;
uint32_t power;
int idx;
@@ -838,20 +840,17 @@
/* fall through */
if (pm_sleep_ops.lowest_limits)
- *msm_pm_idle_rs_limits =
- pm_sleep_ops.lowest_limits(
- true, mode,
- &time_param, &power);
+ rs_limits = pm_sleep_ops.lowest_limits(true,
+ mode, &time_param, &power);
if (MSM_PM_DEBUG_IDLE & msm_pm_debug_mask)
pr_info("CPU%u: %s: %s, latency %uus, "
"sleep %uus, limit %p\n",
dev->cpu, __func__, state->desc,
time_param.latency_us,
- time_param.sleep_us,
- *msm_pm_idle_rs_limits);
+ time_param.sleep_us, rs_limits);
- if (!*msm_pm_idle_rs_limits)
+ if (!rs_limits)
allow = false;
break;
@@ -871,6 +870,8 @@
ret = mode;
}
+ if (MSM_PM_SLEEP_MODE_POWER_COLLAPSE == mode)
+ msm_pm_idle_rs_limits = rs_limits;
}
}
@@ -884,27 +885,11 @@
return ret;
}
-enum msm_pm_sleep_mode msm_pm_idle_enter(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
+int msm_pm_idle_enter(enum msm_pm_sleep_mode sleep_mode)
{
int64_t time;
+ int exit_stat;
bool collapsed = 1;
- int exit_stat = -1;
- enum msm_pm_sleep_mode sleep_mode;
- void *msm_pm_idle_rs_limits = NULL;
- int sleep_delay = 1;
- int ret = -ENODEV;
- int64_t timer_expiration = 0;
- int notify_rpm = false;
- bool timer_halted = false;
-
- sleep_mode = msm_pm_idle_prepare(dev, drv, index,
- &msm_pm_idle_rs_limits);
-
- if (!msm_pm_idle_rs_limits) {
- sleep_mode = MSM_PM_SLEEP_MODE_NOT_SELECTED;
- goto cpuidle_enter_bail;
- }
if (MSM_PM_DEBUG_IDLE & msm_pm_debug_mask)
pr_info("CPU%u: %s: mode %d\n",
@@ -912,80 +897,76 @@
time = ktime_to_ns(ktime_get());
- if (sleep_mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE) {
- notify_rpm = true;
+ switch (sleep_mode) {
+ case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
+ msm_pm_swfi();
+ exit_stat = MSM_PM_STAT_IDLE_WFI;
+ break;
+
+ case MSM_PM_SLEEP_MODE_RETENTION:
+ msm_pm_retention();
+ exit_stat = MSM_PM_STAT_RETENTION;
+ break;
+
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
+ collapsed = msm_pm_power_collapse_standalone(true);
+ exit_stat = MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE;
+ break;
+
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE: {
+ int64_t timer_expiration = 0;
+ bool timer_halted = false;
+ uint32_t sleep_delay;
+ int ret = -ENODEV;
+ int notify_rpm =
+ (sleep_mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE);
timer_expiration = msm_pm_timer_enter_idle();
sleep_delay = (uint32_t) msm_pm_convert_and_cap_time(
timer_expiration, MSM_PM_SLEEP_TICK_LIMIT);
if (sleep_delay == 0) /* 0 would mean infinite time */
sleep_delay = 1;
- }
- if (pm_sleep_ops.enter_sleep)
- ret = pm_sleep_ops.enter_sleep(sleep_delay,
- msm_pm_idle_rs_limits,
- true, notify_rpm);
- if (!ret) {
+ if (MSM_PM_DEBUG_IDLE_CLK & msm_pm_debug_mask)
+ clock_debug_print_enabled();
- switch (sleep_mode) {
- case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
- msm_pm_swfi();
- exit_stat = MSM_PM_STAT_IDLE_WFI;
- break;
-
- case MSM_PM_SLEEP_MODE_RETENTION:
- msm_pm_retention();
- exit_stat = MSM_PM_STAT_RETENTION;
- break;
-
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
- collapsed = msm_pm_power_collapse_standalone(true);
- exit_stat = MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE;
- break;
-
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
- if (MSM_PM_DEBUG_IDLE_CLK & msm_pm_debug_mask)
- clock_debug_print_enabled();
-
+ if (pm_sleep_ops.enter_sleep)
+ ret = pm_sleep_ops.enter_sleep(sleep_delay,
+ msm_pm_idle_rs_limits,
+ true, notify_rpm);
+ if (!ret) {
collapsed = msm_pm_power_collapse(true);
timer_halted = true;
- exit_stat = MSM_PM_STAT_IDLE_POWER_COLLAPSE;
- msm_pm_timer_exit_idle(timer_halted);
- break;
-
- case MSM_PM_SLEEP_MODE_NOT_SELECTED:
- goto cpuidle_enter_bail;
- break;
-
- default:
- __WARN();
- goto cpuidle_enter_bail;
- break;
+ if (pm_sleep_ops.exit_sleep)
+ pm_sleep_ops.exit_sleep(msm_pm_idle_rs_limits,
+ true, notify_rpm, collapsed);
}
- if (pm_sleep_ops.exit_sleep)
- pm_sleep_ops.exit_sleep(msm_pm_idle_rs_limits,
- true, notify_rpm, collapsed);
-
- time = ktime_to_ns(ktime_get()) - time;
- msm_pm_ftrace_lpm_exit(smp_processor_id(), sleep_mode,
- collapsed);
- if (exit_stat >= 0)
- msm_pm_add_stat(exit_stat, time);
- do_div(time, 1000);
- dev->last_residency = (int) time;
- return sleep_mode;
-
- } else if (sleep_mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE) {
msm_pm_timer_exit_idle(timer_halted);
- sleep_mode = MSM_PM_SLEEP_MODE_NOT_SELECTED;
- } else
- sleep_mode = MSM_PM_SLEEP_MODE_NOT_SELECTED;
+ exit_stat = MSM_PM_STAT_IDLE_POWER_COLLAPSE;
+ break;
+ }
+
+ case MSM_PM_SLEEP_MODE_NOT_SELECTED:
+ goto cpuidle_enter_bail;
+ break;
+
+ default:
+ __WARN();
+ goto cpuidle_enter_bail;
+ break;
+ }
+
+ time = ktime_to_ns(ktime_get()) - time;
+ msm_pm_add_stat(exit_stat, time);
+ msm_pm_ftrace_lpm_exit(smp_processor_id(), sleep_mode,
+ collapsed);
+
+ do_div(time, 1000);
+ return (int) time;
cpuidle_enter_bail:
- dev->last_residency = 0;
- return sleep_mode;
+ return 0;
}
void msm_pm_cpu_enter_lowpower(unsigned int cpu)
diff --git a/arch/arm/mach-msm/pm.h b/arch/arm/mach-msm/pm.h
index 43bb7de..399194a 100644
--- a/arch/arm/mach-msm/pm.h
+++ b/arch/arm/mach-msm/pm.h
@@ -108,9 +108,10 @@
};
void msm_pm_set_platform_data(struct msm_pm_platform_data *data, int count);
-enum msm_pm_sleep_mode msm_pm_idle_enter(struct cpuidle_device *dev,
+int msm_pm_idle_prepare(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
void msm_pm_set_irq_extns(struct msm_pm_irq_calls *irq_calls);
+int msm_pm_idle_enter(enum msm_pm_sleep_mode sleep_mode);
void msm_pm_cpu_enter_lowpower(unsigned int cpu);
void __init msm_pm_set_tz_retention_flag(unsigned int flag);
void msm_pm_enable_retention(bool enable);
diff --git a/arch/arm/mach-msm/qdsp5/audio_mvs.c b/arch/arm/mach-msm/qdsp5/audio_mvs.c
index 7d2766d..d1aba82 100644
--- a/arch/arm/mach-msm/qdsp5/audio_mvs.c
+++ b/arch/arm/mach-msm/qdsp5/audio_mvs.c
@@ -1734,6 +1734,7 @@
{
MM_DBG("\n");
+ wake_lock_destroy(&audio_mvs_info.suspend_lock);
misc_deregister(&audio_mvs_misc);
}
diff --git a/drivers/gpu/ion/ion_cma_secure_heap.c b/drivers/gpu/ion/ion_cma_secure_heap.c
index 0a14979..2c0e5ae 100644
--- a/drivers/gpu/ion/ion_cma_secure_heap.c
+++ b/drivers/gpu/ion/ion_cma_secure_heap.c
@@ -262,8 +262,9 @@
extra_iova_addr = data->iova_addr + buffer->size;
if (extra) {
- ret = msm_iommu_map_extra(domain, extra_iova_addr, extra, SZ_4K,
- prot);
+ unsigned long phys_addr = sg_phys(table->sgl);
+ ret = msm_iommu_map_extra(domain, extra_iova_addr, phys_addr,
+ extra, SZ_4K, prot);
if (ret)
goto out2;
}
diff --git a/drivers/hwmon/qpnp-adc-current.c b/drivers/hwmon/qpnp-adc-current.c
index 11f351c..3fdc68f 100644
--- a/drivers/hwmon/qpnp-adc-current.c
+++ b/drivers/hwmon/qpnp-adc-current.c
@@ -125,6 +125,7 @@
#define QPNP_BIT_SHIFT_8 8
#define QPNP_RSENSE_MSB_SIGN_CHECK 0x80
#define QPNP_ADC_COMPLETION_TIMEOUT HZ
+#define QPNP_IADC_ERR_CHK_RATELIMIT 3
struct qpnp_iadc_drv {
struct qpnp_adc_drv *adc;
@@ -134,6 +135,9 @@
bool iadc_initialized;
int64_t die_temp_calib_offset;
struct delayed_work iadc_work;
+ struct mutex iadc_vadc_lock;
+ bool iadc_mode_sel;
+ uint32_t iadc_err_cnt;
struct sensor_device_attribute sens_attr[0];
};
@@ -292,7 +296,7 @@
}
static int32_t qpnp_iadc_configure(enum qpnp_iadc_channels channel,
- uint16_t *raw_code)
+ uint16_t *raw_code, uint32_t mode_sel)
{
struct qpnp_iadc_drv *iadc = qpnp_iadc;
u8 qpnp_iadc_mode_reg = 0, qpnp_iadc_ch_sel_reg = 0;
@@ -303,7 +307,11 @@
qpnp_iadc_dig_param_reg |= iadc->adc->amux_prop->decimation <<
QPNP_IADC_DEC_RATIO_SEL;
- qpnp_iadc_mode_reg |= QPNP_ADC_TRIM_EN;
+ if (iadc->iadc_mode_sel)
+ qpnp_iadc_mode_reg |= (QPNP_ADC_TRIM_EN | QPNP_VADC_SYNCH_EN);
+ else
+ qpnp_iadc_mode_reg |= QPNP_ADC_TRIM_EN;
+
qpnp_iadc_conv_req = QPNP_IADC_CONV_REQ;
rc = qpnp_iadc_write_reg(QPNP_IADC_MODE_CTL, qpnp_iadc_mode_reg);
@@ -403,8 +411,10 @@
uint8_t rslt_lsb, rslt_msb;
int32_t rc = 0;
uint16_t raw_data;
+ uint32_t mode_sel = 0;
- rc = qpnp_iadc_configure(GAIN_CALIBRATION_17P857MV, &raw_data);
+ rc = qpnp_iadc_configure(GAIN_CALIBRATION_17P857MV,
+ &raw_data, mode_sel);
if (rc < 0) {
pr_err("qpnp adc result read failed with %d\n", rc);
goto fail;
@@ -412,8 +422,8 @@
iadc->adc->calib.gain_raw = raw_data;
- rc = qpnp_iadc_configure(OFFSET_CALIBRATION_SHORT_CADC_LEADS,
- &raw_data);
+ rc = qpnp_iadc_configure(OFFSET_CALIBRATION_CSP2_CSN2,
+ &raw_data, mode_sel);
if (rc < 0) {
pr_err("qpnp adc result read failed with %d\n", rc);
goto fail;
@@ -470,12 +480,15 @@
mutex_lock(&iadc->adc->adc_lock);
rc = qpnp_iadc_calibrate_for_trim();
- if (rc)
+ if (rc) {
pr_err("periodic IADC calibration failed\n");
+ iadc->iadc_err_cnt++;
+ }
mutex_unlock(&iadc->adc->adc_lock);
- schedule_delayed_work(&iadc->iadc_work,
+ if (iadc->iadc_err_cnt < QPNP_IADC_ERR_CHK_RATELIMIT)
+ schedule_delayed_work(&iadc->iadc_work,
round_jiffies_relative(msecs_to_jiffies
(QPNP_IADC_CALIB_SECONDS)));
@@ -568,22 +581,24 @@
struct qpnp_iadc_result *result)
{
struct qpnp_iadc_drv *iadc = qpnp_iadc;
- int32_t rc, rsense_n_ohms, sign = 0, num;
+ int32_t rc, rsense_n_ohms, sign = 0, num, mode_sel = 0;
int64_t result_current;
uint16_t raw_data;
if (!iadc || !iadc->iadc_initialized)
return -EPROBE_DEFER;
- rc = qpnp_check_pmic_temp();
- if (rc) {
- pr_err("Error checking pmic therm temp\n");
- return rc;
+ if (!iadc->iadc_mode_sel) {
+ rc = qpnp_check_pmic_temp();
+ if (rc) {
+ pr_err("Error checking pmic therm temp\n");
+ return rc;
+ }
}
mutex_lock(&iadc->adc->adc_lock);
- rc = qpnp_iadc_configure(channel, &raw_data);
+ rc = qpnp_iadc_configure(channel, &raw_data, mode_sel);
if (rc < 0) {
pr_err("qpnp adc result read failed with %d\n", rc);
goto fail;
@@ -644,6 +659,50 @@
}
EXPORT_SYMBOL(qpnp_iadc_get_gain_and_offset);
+int32_t qpnp_iadc_vadc_sync_read(
+ enum qpnp_iadc_channels i_channel, struct qpnp_iadc_result *i_result,
+ enum qpnp_vadc_channels v_channel, struct qpnp_vadc_result *v_result)
+{
+ struct qpnp_iadc_drv *iadc = qpnp_iadc;
+ int rc = 0;
+
+ if (!iadc || !iadc->iadc_initialized)
+ return -EPROBE_DEFER;
+
+ mutex_lock(&iadc->iadc_vadc_lock);
+
+ rc = qpnp_check_pmic_temp();
+ if (rc) {
+ pr_err("PMIC die temp check failed\n");
+ goto fail;
+ }
+
+ iadc->iadc_mode_sel = true;
+
+ rc = qpnp_vadc_iadc_sync_request(v_channel);
+ if (rc) {
+ pr_err("Configuring VADC failed\n");
+ goto fail;
+ }
+
+ rc = qpnp_iadc_read(i_channel, i_result);
+ if (rc)
+ pr_err("Configuring IADC failed\n");
+ /* Intentional fall through to release VADC */
+
+ rc = qpnp_vadc_iadc_sync_complete_request(v_channel,
+ v_result);
+ if (rc)
+ pr_err("Releasing VADC failed\n");
+fail:
+ iadc->iadc_mode_sel = false;
+
+ mutex_unlock(&iadc->iadc_vadc_lock);
+
+ return rc;
+}
+EXPORT_SYMBOL(qpnp_iadc_vadc_sync_read);
+
static ssize_t qpnp_iadc_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
@@ -786,6 +845,8 @@
schedule_delayed_work(&iadc->iadc_work,
round_jiffies_relative(msecs_to_jiffies
(QPNP_IADC_CALIB_SECONDS)));
+ mutex_init(&iadc->iadc_vadc_lock);
+ iadc->iadc_err_cnt = 0;
iadc->iadc_initialized = true;
return 0;
@@ -801,6 +862,7 @@
struct device_node *child;
int i = 0;
+ mutex_destroy(&iadc->iadc_vadc_lock);
for_each_child_of_node(node, child) {
device_remove_file(&spmi->dev,
&iadc->sens_attr[i].dev_attr);
diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c
index 3df19d7..edbde44 100644
--- a/drivers/hwmon/qpnp-adc-voltage.c
+++ b/drivers/hwmon/qpnp-adc-voltage.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -98,6 +98,7 @@
bool vadc_init_calib;
bool vadc_initialized;
int max_channels_available;
+ bool vadc_iadc_sync_lock;
struct sensor_device_attribute sens_attr[0];
};
@@ -304,11 +305,14 @@
if (rc)
return rc;
- /* Request conversion */
- rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_REQ, QPNP_VADC_CONV_REQ_SET);
- if (rc < 0) {
- pr_err("Request conversion failed\n");
- return rc;
+ if (!vadc->vadc_iadc_sync_lock) {
+ /* Request conversion */
+ rc = qpnp_vadc_write_reg(QPNP_VADC_CONV_REQ,
+ QPNP_VADC_CONV_REQ_SET);
+ if (rc < 0) {
+ pr_err("Request conversion failed\n");
+ return rc;
+ }
}
return 0;
@@ -734,6 +738,121 @@
}
EXPORT_SYMBOL_GPL(qpnp_vadc_read);
+static void qpnp_vadc_lock(void)
+{
+ struct qpnp_vadc_drv *vadc = qpnp_vadc;
+
+ mutex_lock(&vadc->adc->adc_lock);
+}
+
+static void qpnp_vadc_unlock(void)
+{
+ struct qpnp_vadc_drv *vadc = qpnp_vadc;
+
+ mutex_unlock(&vadc->adc->adc_lock);
+}
+
+int32_t qpnp_vadc_iadc_sync_request(enum qpnp_vadc_channels channel)
+{
+ struct qpnp_vadc_drv *vadc = qpnp_vadc;
+ int rc = 0, dt_index = 0;
+
+ if (!vadc || !vadc->vadc_initialized)
+ return -EPROBE_DEFER;
+
+ qpnp_vadc_lock();
+
+ if (!vadc->vadc_init_calib) {
+ rc = qpnp_vadc_version_check();
+ if (rc)
+ goto fail;
+
+ rc = qpnp_vadc_calib_device();
+ if (rc) {
+ pr_err("Calibration failed\n");
+ goto fail;
+ } else
+ vadc->vadc_init_calib = true;
+ }
+
+ vadc->adc->amux_prop->amux_channel = channel;
+
+ while ((vadc->adc->adc_channels[dt_index].channel_num
+ != channel) && (dt_index < vadc->max_channels_available))
+ dt_index++;
+
+ if (dt_index >= vadc->max_channels_available) {
+ pr_err("not a valid VADC channel\n");
+ rc = -EINVAL;
+ goto fail;
+ }
+
+ vadc->adc->amux_prop->decimation =
+ vadc->adc->adc_channels[dt_index].adc_decimation;
+ vadc->adc->amux_prop->hw_settle_time =
+ vadc->adc->adc_channels[dt_index].hw_settle_time;
+ vadc->adc->amux_prop->fast_avg_setup =
+ vadc->adc->adc_channels[dt_index].fast_avg_setup;
+ vadc->adc->amux_prop->mode_sel = (ADC_OP_NORMAL_MODE
+ << QPNP_VADC_OP_MODE_SHIFT);
+ vadc->vadc_iadc_sync_lock = true;
+
+ rc = qpnp_vadc_configure(vadc->adc->amux_prop);
+ if (rc) {
+ pr_err("qpnp vadc configure failed with %d\n", rc);
+ goto fail;
+ }
+
+ return rc;
+fail:
+ vadc->vadc_iadc_sync_lock = false;
+ qpnp_vadc_unlock();
+ return rc;
+}
+EXPORT_SYMBOL(qpnp_vadc_iadc_sync_request);
+
+int32_t qpnp_vadc_iadc_sync_complete_request(enum qpnp_vadc_channels channel,
+ struct qpnp_vadc_result *result)
+{
+ struct qpnp_vadc_drv *vadc = qpnp_vadc;
+ int rc = 0, scale_type, amux_prescaling, dt_index = 0;
+
+ vadc->adc->amux_prop->amux_channel = channel;
+
+ while ((vadc->adc->adc_channels[dt_index].channel_num
+ != channel) && (dt_index < vadc->max_channels_available))
+ dt_index++;
+
+ rc = qpnp_vadc_read_conversion_result(&result->adc_code);
+ if (rc) {
+ pr_err("qpnp vadc read adc code failed with %d\n", rc);
+ goto fail;
+ }
+
+ amux_prescaling =
+ vadc->adc->adc_channels[dt_index].chan_path_prescaling;
+
+ vadc->adc->amux_prop->chan_prop->offset_gain_numerator =
+ qpnp_vadc_amux_scaling_ratio[amux_prescaling].num;
+ vadc->adc->amux_prop->chan_prop->offset_gain_denominator =
+ qpnp_vadc_amux_scaling_ratio[amux_prescaling].den;
+
+ scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn;
+ if (scale_type >= SCALE_NONE) {
+ rc = -EBADF;
+ goto fail;
+ }
+
+ vadc_scale_fn[scale_type].chan(result->adc_code,
+ vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result);
+
+fail:
+ vadc->vadc_iadc_sync_lock = false;
+ qpnp_vadc_unlock();
+ return rc;
+}
+EXPORT_SYMBOL(qpnp_vadc_iadc_sync_complete_request);
+
static ssize_t qpnp_adc_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
@@ -857,6 +976,7 @@
vadc->vadc_init_calib = false;
vadc->max_channels_available = count_adc_channel_list;
vadc->vadc_initialized = true;
+ vadc->vadc_iadc_sync_lock = false;
return 0;
fail:
diff --git a/drivers/media/platform/msm/vidc/hfi_packetization.c b/drivers/media/platform/msm/vidc/hfi_packetization.c
index 44e23ed..1cabc3e 100644
--- a/drivers/media/platform/msm/vidc/hfi_packetization.c
+++ b/drivers/media/platform/msm/vidc/hfi_packetization.c
@@ -39,6 +39,24 @@
return rc;
}
+int create_pkt_cmd_sys_idle_indicator(
+ struct hfi_cmd_sys_set_property_packet *pkt,
+ u32 enable)
+{
+ struct hfi_enable *hfi;
+ if (!pkt)
+ return -EINVAL;
+
+ pkt->size = sizeof(struct hfi_cmd_sys_set_property_packet) +
+ sizeof(struct hfi_enable) + sizeof(u32);
+ pkt->packet_type = HFI_CMD_SYS_SET_PROPERTY;
+ pkt->num_properties = 1;
+ pkt->rg_property_data[0] = HFI_PROPERTY_SYS_IDLE_INDICATOR;
+ hfi = (struct hfi_enable *) &pkt->rg_property_data[1];
+ hfi->enable = enable;
+ return 0;
+}
+
int create_pkt_set_cmd_sys_resource(
struct hfi_cmd_sys_set_resource_packet *pkt,
struct vidc_resource_hdr *resource_hdr,
diff --git a/drivers/media/platform/msm/vidc/hfi_packetization.h b/drivers/media/platform/msm/vidc/hfi_packetization.h
index b2c6e08..8c61a40 100644
--- a/drivers/media/platform/msm/vidc/hfi_packetization.h
+++ b/drivers/media/platform/msm/vidc/hfi_packetization.h
@@ -22,6 +22,10 @@
u32 arch_type);
int create_pkt_cmd_sys_pc_prep(struct hfi_cmd_sys_pc_prep_packet *pkt);
+int create_pkt_cmd_sys_idle_indicator(
+ struct hfi_cmd_sys_set_property_packet *pkt,
+ u32 enable);
+
int create_pkt_set_cmd_sys_resource(
struct hfi_cmd_sys_set_resource_packet *pkt,
struct vidc_resource_hdr *resource_hdr,
diff --git a/drivers/media/platform/msm/vidc/hfi_response_handler.c b/drivers/media/platform/msm/vidc/hfi_response_handler.c
index f6a9949..709eafc 100644
--- a/drivers/media/platform/msm/vidc/hfi_response_handler.c
+++ b/drivers/media/platform/msm/vidc/hfi_response_handler.c
@@ -823,19 +823,21 @@
callback(SESSION_GET_SEQ_HDR_DONE, &data_done);
}
-void hfi_process_msg_packet(
+u32 hfi_process_msg_packet(
msm_vidc_callback callback, u32 device_id,
struct vidc_hal_msg_pkt_hdr *msg_hdr)
{
+ u32 rc = 0;
if (!callback || !msg_hdr || msg_hdr->size <
VIDC_IFACEQ_MIN_PKT_SIZE) {
dprintk(VIDC_ERR, "hal_process_msg_packet:bad"
"packet/packet size: %d", msg_hdr->size);
- return;
+ rc = -EINVAL;
+ return rc;
}
dprintk(VIDC_INFO, "Received: 0x%x in ", msg_hdr->packet);
-
+ rc = (u32) msg_hdr->packet;
switch (msg_hdr->packet) {
case HFI_MSG_EVENT_NOTIFY:
hfi_process_event_notify(callback, device_id,
@@ -846,6 +848,8 @@
(struct hfi_msg_sys_init_done_packet *)
msg_hdr);
break;
+ case HFI_MSG_SYS_IDLE:
+ break;
case HFI_MSG_SYS_SESSION_INIT_DONE:
hfi_process_session_init_done(callback, device_id,
(struct hfi_msg_sys_session_init_done_packet *)
@@ -915,4 +919,5 @@
dprintk(VIDC_ERR, "UNKNOWN_MSG_TYPE : %d", msg_hdr->packet);
break;
}
+ return rc;
}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c
index 3c012e7..9f5f5af 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c
@@ -987,7 +987,7 @@
rc = call_hfi_op(hdev, unset_ocmem, hdev->hfi_device_data);
if (rc) {
- dprintk(VIDC_ERR, "Failed to set OCMEM on driver\n");
+ dprintk(VIDC_INFO, "Failed to unset OCMEM on driver\n");
goto release_ocmem_failed;
}
rc = wait_for_completion_timeout(
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_debug.c b/drivers/media/platform/msm/vidc/msm_vidc_debug.c
index b713d8b..65542bc 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_debug.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_debug.c
@@ -18,6 +18,7 @@
int msm_vidc_debug = 0x3;
int msm_fw_debug = 0x18;
int msm_fw_debug_mode = 0x1;
+int msm_fw_low_power_mode = 0x1;
struct debug_buffer {
char ptr[MAX_DBG_BUF_SIZE];
@@ -159,6 +160,11 @@
dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
goto failed_create_dir;
}
+ if (!debugfs_create_u32("fw_low_power_mode", S_IRUGO | S_IWUSR,
+ parent, &msm_fw_low_power_mode)) {
+ dprintk(VIDC_ERR, "debugfs_create_file: fail\n");
+ goto failed_create_dir;
+ }
failed_create_dir:
return dir;
}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_debug.h b/drivers/media/platform/msm/vidc/msm_vidc_debug.h
index 07568ef..fb06af6 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_debug.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_debug.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -44,6 +44,7 @@
extern int msm_vidc_debug;
extern int msm_fw_debug;
extern int msm_fw_debug_mode;
+extern int msm_fw_low_power_mode;
#define dprintk(__level, __fmt, arg...) \
do { \
diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c
index 7deef37..9fe360e 100644
--- a/drivers/media/platform/msm/vidc/venus_hfi.c
+++ b/drivers/media/platform/msm/vidc/venus_hfi.c
@@ -814,6 +814,93 @@
rmb();
return rc;
}
+static inline void venus_hfi_clk_gating_on(struct venus_hfi_device *device,
+ enum vidc_clocks clk_level)
+{
+ int i;
+ struct venus_core_clock *cl;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid params: %p\n", device);
+ return;
+ }
+ if (device->clocks_enabled == 0) {
+ dprintk(VIDC_DBG, "VCODEC clocks are already disabled");
+ goto already_disabled;
+ }
+ for (i = 0; i < clk_level; i++) {
+ cl = &device->resources.clock[i];
+ clk_disable_unprepare(cl->clk);
+ }
+already_disabled:
+ device->clocks_enabled = 0;
+}
+static inline int venus_hfi_clk_gating_off(struct venus_hfi_device *device,
+ enum vidc_clocks clk_level)
+{
+ int i;
+ struct venus_core_clock *cl;
+ int rc = 0;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid params: %p\n", device);
+ return -EINVAL;
+ }
+ if (device->clocks_enabled == 1) {
+ dprintk(VIDC_DBG, "VCODEC clocks are already enabled");
+ goto already_enabled;
+ }
+ for (i = 0; i < clk_level; i++) {
+ cl = &device->resources.clock[i];
+ rc = clk_prepare_enable(cl->clk);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to enable clocks\n");
+ goto fail_clk_enable;
+ } else {
+ dprintk(VIDC_DBG, "Clock: %s enabled\n", cl->name);
+ }
+ }
+already_enabled:
+ device->clocks_enabled = 1;
+ return rc;
+fail_clk_enable:
+ for (; i >= 0; i--) {
+ cl = &device->resources.clock[i];
+ clk_disable_unprepare(cl->clk);
+ }
+ return rc;
+}
+
+static unsigned long venus_hfi_get_clock_rate(struct venus_core_clock *clock,
+ int num_mbs_per_sec)
+{
+ int num_rows = clock->count;
+ struct load_freq_table *table = clock->load_freq_tbl;
+ unsigned long ret = table[num_rows-1].freq;
+ int i;
+ for (i = 0; i < num_rows; i++) {
+ if (num_mbs_per_sec > table[i].load)
+ break;
+ ret = table[i].freq;
+ }
+ dprintk(VIDC_PROF, "Required clock rate = %lu\n", ret);
+ return ret;
+}
+
+static int venus_hfi_scale_clocks(void *dev, int load)
+{
+ int rc = 0;
+ struct venus_hfi_device *device = dev;
+ device->load = load;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid args: %p\n", device);
+ return -EINVAL;
+ }
+ rc = clk_set_rate(device->resources.clock[VCODEC_CLK].clk,
+ venus_hfi_get_clock_rate(&device->resources.clock[VCODEC_CLK],
+ load));
+ if (rc)
+ dprintk(VIDC_ERR, "Failed to set clock rate: %d\n", rc);
+ return rc;
+}
static int venus_hfi_iface_cmdq_write(struct venus_hfi_device *device,
void *pkt)
@@ -821,7 +908,6 @@
u32 rx_req_is_set = 0;
struct vidc_iface_q_info *q_info;
int result = -EPERM;
-
if (!device || !pkt) {
dprintk(VIDC_ERR, "Invalid Params");
return -EINVAL;
@@ -833,7 +919,16 @@
dprintk(VIDC_ERR, "cannot write to shared Q's");
goto err_q_write;
}
-
+ result = venus_hfi_clk_gating_off(device, VCODEC_CLK);
+ if (result) {
+ dprintk(VIDC_ERR, "VCODEC clock enable failed\n");
+ goto err_q_write;
+ }
+ result = venus_hfi_scale_clocks(device, device->load);
+ if (result) {
+ dprintk(VIDC_ERR, "VCODEC clock scaling failed\n");
+ goto err_q_write;
+ }
if (!venus_hfi_write_queue(q_info, (u8 *)pkt, &rx_req_is_set)) {
if (rx_req_is_set)
venus_hfi_write_register(
@@ -1218,6 +1313,18 @@
return -ENOTEMPTY;
return 0;
}
+static int venus_hfi_sys_set_idle_message(struct venus_hfi_device *device,
+ int enable)
+{
+ u8 packet[VIDC_IFACEQ_VAR_SMALL_PKT_SIZE];
+ struct hfi_cmd_sys_set_property_packet *pkt =
+ (struct hfi_cmd_sys_set_property_packet *) &packet;
+ create_pkt_cmd_sys_idle_indicator(pkt, enable);
+ if (venus_hfi_iface_cmdq_write(device, pkt))
+ return -ENOTEMPTY;
+ return 0;
+}
+
static int venus_hfi_core_init(void *device)
{
@@ -1660,6 +1767,8 @@
goto err_session_init_fail;
if (venus_hfi_sys_set_debug(dev, msm_fw_debug))
dprintk(VIDC_ERR, "Setting fw_debug msg ON failed");
+ if (venus_hfi_sys_set_idle_message(dev, msm_fw_low_power_mode))
+ dprintk(VIDC_ERR, "Setting idle response ON failed");
return (void *) new_session;
err_session_init_fail:
@@ -2049,10 +2158,50 @@
device->callback(SYS_WATCHDOG_TIMEOUT, &cmd_done);
}
+static int venus_hfi_is_cmd_pending(struct venus_hfi_device *dev)
+{
+ struct hfi_queue_header *queue;
+ struct vidc_iface_q_info *q_info;
+ u32 write_ptr, read_ptr;
+ u32 rc = 0;
+ q_info = &dev->iface_queues[VIDC_IFACEQ_CMDQ_IDX];
+ if (!q_info)
+ dprintk(VIDC_ERR, "cannot read shared Q's");
+ queue = (struct hfi_queue_header *) q_info->q_hdr;
+ if (!queue) {
+ dprintk(VIDC_ERR, "queue not present");
+ return -ENOENT;
+ }
+ write_ptr = (u32)queue->qhdr_write_idx;
+ read_ptr = (u32)queue->qhdr_read_idx;
+ rc = read_ptr - write_ptr;
+ return rc;
+}
+
+static int venus_hfi_try_clk_gating(struct venus_hfi_device *device)
+{
+ int rc = 0;
+ u32 ctrl_status = 0;
+ if (!device) {
+ dprintk(VIDC_ERR, "invalid device");
+ return -ENODEV;
+ }
+ mutex_lock(&device->write_lock);
+ rc = venus_hfi_is_cmd_pending(device);
+ ctrl_status = venus_hfi_read_register(
+ device->hal_data->register_base_addr,
+ VIDC_CPU_CS_SCIACMDARG0);
+ if (((ctrl_status & VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK)
+ != 0) && !rc)
+ venus_hfi_clk_gating_on(device, VCODEC_CLK);
+ mutex_unlock(&device->write_lock);
+ return rc;
+}
+
static void venus_hfi_response_handler(struct venus_hfi_device *device)
{
u8 packet[VIDC_IFACEQ_MED_PKT_SIZE];
-
+ u32 rc = 0;
dprintk(VIDC_INFO, "#####venus_hfi_response_handler#####\n");
if (device) {
if ((device->intr_status &
@@ -2063,9 +2212,12 @@
}
while (!venus_hfi_iface_msgq_read(device, packet)) {
- hfi_process_msg_packet(device->callback,
+ rc = hfi_process_msg_packet(device->callback,
device->device_id,
(struct vidc_hal_msg_pkt_hdr *) packet);
+ if (rc == HFI_MSG_SYS_IDLE)
+ rc = venus_hfi_try_clk_gating(device);
+
}
while (!venus_hfi_iface_dbgq_read(device, packet)) {
struct hfi_msg_sys_debug_packet *pkt =
@@ -2233,50 +2385,45 @@
for (i = 0; i < VCODEC_MAX_CLKS; i++)
clk_put(device->resources.clock[i].clk);
}
-
-static unsigned long venus_hfi_get_clock_rate(struct venus_core_clock *clock,
- int num_mbs_per_sec)
+static inline void venus_hfi_disable_clks(struct venus_hfi_device *device)
{
- int num_rows = clock->count;
- struct load_freq_table *table = clock->load_freq_tbl;
- unsigned long ret = table[num_rows-1].freq;
int i;
- for (i = 0; i < num_rows; i++) {
- if (num_mbs_per_sec > table[i].load)
- break;
- ret = table[i].freq;
- }
- dprintk(VIDC_PROF, "Required clock rate = %lu\n", ret);
- return ret;
-}
-
-static int venus_hfi_scale_clocks(void *dev, int load)
-{
- int rc = 0;
- struct venus_hfi_device *device = dev;
+ struct venus_core_clock *cl;
if (!device) {
- dprintk(VIDC_ERR, "Invalid args: %p\n", device);
- return -EINVAL;
+ dprintk(VIDC_ERR, "Invalid params: %p\n", device);
+ return;
+ }
+ if (device->clocks_enabled) {
+ cl = &device->resources.clock[VCODEC_CLK];
+ clk_disable_unprepare(cl->clk);
}
- rc = clk_set_rate(device->resources.clock[VCODEC_CLK].clk,
- venus_hfi_get_clock_rate(&device->resources.clock[VCODEC_CLK],
- load));
- if (rc)
- dprintk(VIDC_ERR, "Failed to set clock rate: %d\n", rc);
- return rc;
+ for (i = VCODEC_CLK; i < VCODEC_MAX_CLKS; i++) {
+ cl = &device->resources.clock[i];
+ clk_disable_unprepare(cl->clk);
+ }
+ device->clocks_enabled = 0;
}
-
static inline int venus_hfi_enable_clks(struct venus_hfi_device *device)
{
- int i;
+ int i = 0;
struct venus_core_clock *cl;
int rc = 0;
if (!device) {
dprintk(VIDC_ERR, "Invalid params: %p\n", device);
return -EINVAL;
}
- for (i = 0; i < VCODEC_MAX_CLKS; i++) {
+ if (!device->clocks_enabled) {
+ cl = &device->resources.clock[VCODEC_CLK];
+ rc = clk_prepare_enable(cl->clk);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to enable clocks\n");
+ goto fail_clk_enable;
+ } else {
+ dprintk(VIDC_DBG, "Clock: %s enabled\n", cl->name);
+ }
+ }
+ for (i = VCODEC_CLK; i < VCODEC_MAX_CLKS; i++) {
cl = &device->resources.clock[i];
rc = clk_prepare_enable(cl->clk);
if (rc) {
@@ -2286,6 +2433,7 @@
dprintk(VIDC_DBG, "Clock: %s enabled\n", cl->name);
}
}
+ device->clocks_enabled = 1;
return rc;
fail_clk_enable:
for (; i >= 0; i--) {
@@ -2294,21 +2442,6 @@
}
return rc;
}
-
-static inline void venus_hfi_disable_clks(struct venus_hfi_device *device)
-{
- int i;
- struct venus_core_clock *cl;
- if (!device) {
- dprintk(VIDC_ERR, "Invalid params: %p\n", device);
- return;
- }
- for (i = 0; i < VCODEC_MAX_CLKS; i++) {
- cl = &device->resources.clock[i];
- clk_disable_unprepare(cl->clk);
- }
-}
-
static int venus_hfi_register_iommu_domains(struct venus_hfi_device *device,
struct msm_vidc_platform_resources *res)
{
@@ -2553,17 +2686,25 @@
struct vidc_resource_hdr rhdr;
struct venus_hfi_device *device = dev;
int rc = 0;
- if (!device || !device->resources.ocmem.buf) {
+ if (!device) {
dprintk(VIDC_ERR, "%s Invalid params, device:%p\n",
__func__, device);
- return -EINVAL;
+ rc = -EINVAL;
+ goto ocmem_unset_failed;
}
+ if (!device->resources.ocmem.buf) {
+ dprintk(VIDC_INFO, "%s Trying to free OCMEM which is not set",
+ __func__);
+ rc = -EINVAL;
+ goto ocmem_unset_failed;
+ }
+
rhdr.resource_id = VIDC_RESOURCE_OCMEM;
rhdr.resource_handle = (u32) &device->resources.ocmem;
rc = venus_hfi_core_release_resource(device, &rhdr);
if (rc)
- dprintk(VIDC_ERR, "Failed to set OCMEM on driver\n");
-
+ dprintk(VIDC_ERR, "Failed to unset OCMEM on driver\n");
+ocmem_unset_failed:
return rc;
}
diff --git a/drivers/media/platform/msm/vidc/venus_hfi.h b/drivers/media/platform/msm/vidc/venus_hfi.h
index 58314dd..2ffb9d4 100644
--- a/drivers/media/platform/msm/vidc/venus_hfi.h
+++ b/drivers/media/platform/msm/vidc/venus_hfi.h
@@ -175,6 +175,8 @@
struct list_head sess_head;
u32 intr_status;
u32 device_id;
+ u32 load;
+ u32 clocks_enabled;
struct mutex read_lock;
struct mutex write_lock;
msm_vidc_callback callback;
diff --git a/drivers/media/platform/msm/vidc/vidc_hfi.h b/drivers/media/platform/msm/vidc/vidc_hfi.h
index f565d3b..75594b3 100644
--- a/drivers/media/platform/msm/vidc/vidc_hfi.h
+++ b/drivers/media/platform/msm/vidc/vidc_hfi.h
@@ -830,7 +830,7 @@
extern struct hal_device_data hal_ctxt;
-void hfi_process_msg_packet(msm_vidc_callback callback,
+u32 hfi_process_msg_packet(msm_vidc_callback callback,
u32 device_id, struct vidc_hal_msg_pkt_hdr *msg_hdr);
#endif
diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_io.h b/drivers/media/platform/msm/vidc/vidc_hfi_io.h
index 2bc8e6a..eeffe35 100644
--- a/drivers/media/platform/msm/vidc/vidc_hfi_io.h
+++ b/drivers/media/platform/msm/vidc/vidc_hfi_io.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -49,6 +49,7 @@
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_SHFT 0x1
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_BMSK 0x1
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_SHFT 0x0
+#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK 0x40000000
/* HFI_QTBL_INFO */
#define VIDC_CPU_CS_SCIACMDARG1 (VIDC_CPU_CS_BASE_OFFS + 0x50)
diff --git a/drivers/power/battery_current_limit.c b/drivers/power/battery_current_limit.c
index d1750ec..ecda153 100644
--- a/drivers/power/battery_current_limit.c
+++ b/drivers/power/battery_current_limit.c
@@ -507,12 +507,18 @@
return 0;
}
+static struct of_device_id bcl_match_table[] = {
+ {.compatible = "qcom,bcl"},
+ {},
+};
+
static struct platform_driver bcl_driver = {
.probe = bcl_probe,
.remove = __devexit_p(bcl_remove),
.driver = {
.name = BCL_DEV_NAME,
.owner = THIS_MODULE,
+ .of_match_table = bcl_match_table,
},
};
diff --git a/drivers/power/qpnp-charger.c b/drivers/power/qpnp-charger.c
index 3eaf262..e2ba042 100644
--- a/drivers/power/qpnp-charger.c
+++ b/drivers/power/qpnp-charger.c
@@ -70,7 +70,7 @@
#define CHGR_CHG_WDOG_PET 0x64
#define CHGR_CHG_WDOG_EN 0x65
#define CHGR_IR_DROP_COMPEN 0x67
-#define CHGR_USB_IUSB_MAX 0x44
+#define CHGR_I_MAX_REG 0x44
#define CHGR_USB_USB_SUSP 0x47
#define CHGR_USB_USB_OTG_CTL 0x48
#define CHGR_USB_ENUM_T_STOP 0x4E
@@ -172,6 +172,8 @@
* @resume_voltage_mv: voltage at which the battery resumes charging
* @term_current: the charging based term current
* @safe_current: battery safety current setting
+ * @maxinput_usb_ma: Maximum Input current USB
+ * @maxinput_dc_ma: Maximum Input current DC
* @revision: PMIC revision
* @thermal_levels amount of thermal mitigation levels
* @thermal_mitigation thermal mitigation level values
@@ -210,6 +212,8 @@
unsigned int min_voltage_mv;
unsigned int resume_voltage_mv;
unsigned int term_current;
+ unsigned int maxinput_usb_ma;
+ unsigned int maxinput_dc_ma;
unsigned int safe_current;
unsigned int revision;
unsigned int thermal_levels;
@@ -348,36 +352,73 @@
return (dcin_valid_rt_sts & DCIN_VALID_IRQ) ? 1 : 0;
}
-#define QPNP_CHG_IUSB_MAX_MIN_100 100
-#define QPNP_CHG_IUSB_MAX_MIN_150 150
-#define QPNP_CHG_IUSB_MAX_MIN_MA 200
-#define QPNP_CHG_IUSB_MAX_MAX_MA 2500
-#define QPNP_CHG_IUSB_MAX_STEP_MA 100
+#define QPNP_CHG_I_MAX_MIN_100 100
+#define QPNP_CHG_I_MAX_MIN_150 150
+#define QPNP_CHG_I_MAX_MIN_MA 200
+#define QPNP_CHG_I_MAX_MAX_MA 2500
+#define QPNP_CHG_I_MAXSTEP_MA 100
+static int
+qpnp_chg_idcmax_set(struct qpnp_chg_chip *chip, int mA)
+{
+ int rc = 0;
+ u8 dc = 0;
+
+ if (mA < QPNP_CHG_I_MAX_MIN_100
+ || mA > QPNP_CHG_I_MAX_MAX_MA) {
+ pr_err("bad mA=%d asked to set\n", mA);
+ return -EINVAL;
+ }
+
+ if (mA == QPNP_CHG_I_MAX_MIN_100) {
+ dc = 0x00;
+ pr_debug("current=%d setting %02x\n", mA, dc);
+ return qpnp_chg_write(chip, &dc,
+ chip->dc_chgpth_base + CHGR_I_MAX_REG, 1);
+ } else if (mA == QPNP_CHG_I_MAX_MIN_150) {
+ dc = 0x01;
+ pr_debug("current=%d setting %02x\n", mA, dc);
+ return qpnp_chg_write(chip, &dc,
+ chip->dc_chgpth_base + CHGR_I_MAX_REG, 1);
+ }
+
+ dc = mA / QPNP_CHG_I_MAXSTEP_MA;
+
+ pr_debug("current=%d setting 0x%x\n", mA, dc);
+ rc = qpnp_chg_write(chip, &dc,
+ chip->dc_chgpth_base + CHGR_I_MAX_REG, 1);
+
+ return rc;
+}
+
static int
qpnp_chg_iusbmax_set(struct qpnp_chg_chip *chip, int mA)
{
int rc = 0;
u8 usb_reg = 0, temp = 8;
- if (mA == QPNP_CHG_IUSB_MAX_MIN_100) {
- usb_reg = 0x00;
- pr_debug("current=%d setting %02x\n", mA, usb_reg);
- return qpnp_chg_write(chip, &usb_reg,
- chip->usb_chgpth_base + CHGR_USB_IUSB_MAX, 1);
- } else if (mA == QPNP_CHG_IUSB_MAX_MIN_150) {
- usb_reg = 0x01;
- pr_debug("current=%d setting %02x\n", mA, usb_reg);
- return qpnp_chg_write(chip, &usb_reg,
- chip->usb_chgpth_base + CHGR_USB_IUSB_MAX, 1);
- }
-
- if (mA < QPNP_CHG_IUSB_MAX_MIN_MA
- || mA > QPNP_CHG_IUSB_MAX_MAX_MA) {
+ if (mA < QPNP_CHG_I_MAX_MIN_100
+ || mA > QPNP_CHG_I_MAX_MAX_MA) {
pr_err("bad mA=%d asked to set\n", mA);
return -EINVAL;
}
- usb_reg = mA / QPNP_CHG_IUSB_MAX_STEP_MA;
+ if (mA == QPNP_CHG_I_MAX_MIN_100) {
+ usb_reg = 0x00;
+ pr_debug("current=%d setting %02x\n", mA, usb_reg);
+ return qpnp_chg_write(chip, &usb_reg,
+ chip->usb_chgpth_base + CHGR_I_MAX_REG, 1);
+ } else if (mA == QPNP_CHG_I_MAX_MIN_150) {
+ usb_reg = 0x01;
+ pr_debug("current=%d setting %02x\n", mA, usb_reg);
+ return qpnp_chg_write(chip, &usb_reg,
+ chip->usb_chgpth_base + CHGR_I_MAX_REG, 1);
+ }
+
+ /* Impose input current limit */
+ if (chip->maxinput_usb_ma)
+ mA = (chip->maxinput_usb_ma) <= mA ? chip->maxinput_usb_ma : mA;
+
+ usb_reg = mA / QPNP_CHG_I_MAXSTEP_MA;
if (chip->flags & CHG_FLAGS_VCP_WA) {
temp = 0xA5;
@@ -390,7 +431,7 @@
pr_debug("current=%d setting 0x%x\n", mA, usb_reg);
rc = qpnp_chg_write(chip, &usb_reg,
- chip->usb_chgpth_base + CHGR_USB_IUSB_MAX, 1);
+ chip->usb_chgpth_base + CHGR_I_MAX_REG, 1);
if (chip->flags & CHG_FLAGS_VCP_WA) {
temp = 0xA5;
@@ -875,12 +916,12 @@
chip->usb_psy->get_property(chip->usb_psy,
POWER_SUPPLY_PROP_CURRENT_MAX, &ret);
qpnp_chg_iusbmax_set(chip, ret.intval / 1000);
- if ((ret.intval / 1000) <= QPNP_CHG_IUSB_MAX_MIN_MA)
+ if ((ret.intval / 1000) <= QPNP_CHG_I_MAX_MIN_MA)
qpnp_chg_usb_suspend_enable(chip, 1);
else
qpnp_chg_usb_suspend_enable(chip, 0);
} else {
- qpnp_chg_iusbmax_set(chip, QPNP_CHG_IUSB_MAX_MIN_100);
+ qpnp_chg_iusbmax_set(chip, QPNP_CHG_I_MAX_MIN_100);
qpnp_chg_usb_suspend_enable(chip, 0);
}
@@ -1429,6 +1470,33 @@
goto fail_chg_enable;
}
+ /* Get the ibatsafe property */
+ rc = of_property_read_u32(spmi->dev.of_node,
+ "qcom,chg-vbatdet-mv",
+ &chip->resume_voltage_mv);
+ if (rc) {
+ pr_err("Error reading vbatdet property %d\n", rc);
+ goto fail_chg_enable;
+ }
+
+ /* Get the maxinput-dc-ma property */
+ rc = of_property_read_u32(spmi->dev.of_node,
+ "qcom,chg-maxinput-dc-ma",
+ &chip->maxinput_dc_ma);
+ if (rc && rc != -EINVAL) {
+ pr_err("Error reading maxinput-dc-ma property %d\n", rc);
+ goto fail_chg_enable;
+ }
+
+ /* Get the maxinput-usb-ma property */
+ rc = of_property_read_u32(spmi->dev.of_node,
+ "qcom,chg-maxinput-usb-ma",
+ &chip->maxinput_usb_ma);
+ if (rc && rc != -EINVAL) {
+ pr_err("Error reading maxinput-usb-ma property %d\n", rc);
+ goto fail_chg_enable;
+ }
+
/* Get the charging-disabled property */
chip->charging_disabled = of_property_read_bool(spmi->dev.of_node,
"qcom,chg-charging-disabled");
@@ -1596,6 +1664,14 @@
power_supply_set_present(chip->usb_psy,
qpnp_chg_is_usb_chg_plugged_in(chip));
+ if (chip->maxinput_dc_ma) {
+ rc = qpnp_chg_idcmax_set(chip, chip->maxinput_dc_ma);
+ if (rc) {
+ pr_err("Error setting idcmax property %d\n", rc);
+ goto fail_chg_enable;
+ }
+ }
+
qpnp_chg_charge_en(chip, !chip->charging_disabled);
qpnp_chg_force_run_on_batt(chip, chip->charging_disabled);
diff --git a/drivers/thermal/msm_thermal.c b/drivers/thermal/msm_thermal.c
index 0e3daeb..5aca48d 100644
--- a/drivers/thermal/msm_thermal.c
+++ b/drivers/thermal/msm_thermal.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -81,7 +81,7 @@
{
static int limit_init;
struct tsens_device tsens_dev;
- unsigned long temp = 0;
+ long temp = 0;
uint32_t max_freq = limited_max_freq;
int cpu = 0;
int ret = 0;
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index 0011a1a..beba33f 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -165,6 +165,7 @@
struct clk *iface_clk;
struct clk *sleep_clk;
struct clk *hsphy_sleep_clk;
+ struct clk *utmi_clk;
struct regulator *hsusb_3p3;
struct regulator *hsusb_1p8;
struct regulator *hsusb_vddcx;
@@ -1636,9 +1637,12 @@
clk_disable_unprepare(mdwc->core_clk);
clk_disable_unprepare(mdwc->iface_clk);
- /* USB PHY no more requires TCXO */
- if (!host_bus_suspend)
+ if (!host_bus_suspend) {
+ clk_disable_unprepare(mdwc->utmi_clk);
+
+ /* USB PHY no more requires TCXO */
clk_disable_unprepare(mdwc->xo_clk);
+ }
if (mdwc->bus_perf_client) {
ret = msm_bus_scale_client_update_request(
@@ -1705,8 +1709,12 @@
dwc3_ssusb_ldo_enable(1);
dwc3_ssusb_config_vddcx(1);
- if (!host_bus_suspend)
+
+ if (!host_bus_suspend) {
dwc3_hsusb_config_vddcx(1);
+ clk_prepare_enable(mdwc->utmi_clk);
+ }
+
clk_prepare_enable(mdwc->ref_clk);
usleep_range(1000, 1200);
@@ -2235,15 +2243,22 @@
}
clk_prepare_enable(msm->hsphy_sleep_clk);
+ msm->utmi_clk = devm_clk_get(&pdev->dev, "utmi_clk");
+ if (IS_ERR(msm->utmi_clk)) {
+ dev_err(&pdev->dev, "failed to get utmi_clk\n");
+ ret = PTR_ERR(msm->utmi_clk);
+ goto disable_sleep_a_clk;
+ }
+ clk_prepare_enable(msm->utmi_clk);
+
msm->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
if (IS_ERR(msm->ref_clk)) {
dev_err(&pdev->dev, "failed to get ref_clk\n");
ret = PTR_ERR(msm->ref_clk);
- goto disable_sleep_a_clk;
+ goto disable_utmi_clk;
}
clk_prepare_enable(msm->ref_clk);
-
of_get_property(node, "qcom,vdd-voltage-level", &len);
if (len == sizeof(tmp)) {
of_property_read_u32_array(node, "qcom,vdd-voltage-level",
@@ -2526,6 +2541,8 @@
dwc3_ssusb_config_vddcx(0);
disable_ref_clk:
clk_disable_unprepare(msm->ref_clk);
+disable_utmi_clk:
+ clk_disable_unprepare(msm->utmi_clk);
disable_sleep_a_clk:
clk_disable_unprepare(msm->hsphy_sleep_clk);
disable_sleep_clk:
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 2db9eea..0664376 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1205,7 +1205,10 @@
int ret;
+ spin_lock_irqsave(&dwc->lock, flags);
+
if (!dep->endpoint.desc) {
+ spin_unlock_irqrestore(&dwc->lock, flags);
dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
request, ep->name);
return -ESHUTDOWN;
@@ -1217,7 +1220,6 @@
WARN(!dep->direction && (request->length % ep->desc->wMaxPacketSize),
"trying to queue unaligned request (%d)\n", request->length);
- spin_lock_irqsave(&dwc->lock, flags);
ret = __dwc3_gadget_ep_queue(dep, req);
spin_unlock_irqrestore(&dwc->lock, flags);
diff --git a/drivers/usb/gadget/f_mbim.c b/drivers/usb/gadget/f_mbim.c
index daa981f..935a540 100644
--- a/drivers/usb/gadget/f_mbim.c
+++ b/drivers/usb/gadget/f_mbim.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -66,6 +66,7 @@
NCM_NOTIFY_NONE,
NCM_NOTIFY_CONNECT,
NCM_NOTIFY_SPEED,
+ NCM_NOTIFY_RESPONSE_AVAILABLE,
};
struct f_mbim {
@@ -571,6 +572,7 @@
return;
}
+ req->length = sizeof *event;
event = req->buf;
event->bmRequestType = USB_DIR_IN | USB_TYPE_CLASS
| USB_RECIP_INTERFACE;
@@ -581,7 +583,7 @@
spin_unlock_irqrestore(&dev->lock, flags);
ret = usb_ep_queue(dev->not_port.notify,
- dev->not_port.notify_req, GFP_ATOMIC);
+ req, GFP_ATOMIC);
if (ret) {
atomic_dec(&dev->not_port.notify_count);
pr_err("ep enqueue error %d\n", ret);
@@ -610,6 +612,13 @@
return 0;
}
+ if (dev->not_port.notify_state != NCM_NOTIFY_RESPONSE_AVAILABLE) {
+ pr_err("dev:%p state=%d, recover!!\n", dev,
+ dev->not_port.notify_state);
+ mbim_free_ctrl_pkt(cpkt);
+ return 0;
+ }
+
spin_lock_irqsave(&dev->lock, flags);
list_add_tail(&cpkt->list, &dev->cpkt_resp_q);
spin_unlock_irqrestore(&dev->lock, flags);
@@ -750,10 +759,18 @@
switch (mbim->not_port.notify_state) {
case NCM_NOTIFY_NONE:
+ if (atomic_read(&mbim->not_port.notify_count) > 0)
+ pr_err("Pending notifications in NCM_NOTIFY_NONE\n");
+ else
+ pr_debug("No pending notifications\n");
+
+ return;
+
+ case NCM_NOTIFY_RESPONSE_AVAILABLE:
pr_debug("Notification %02x sent\n", event->bNotificationType);
if (atomic_read(&mbim->not_port.notify_count) <= 0) {
- pr_debug("notify_none: done");
+ pr_debug("notify_response_avaliable: done");
return;
}
@@ -778,7 +795,7 @@
pr_info("notify connect %s\n",
mbim->is_open ? "true" : "false");
- mbim->not_port.notify_state = NCM_NOTIFY_NONE;
+ mbim->not_port.notify_state = NCM_NOTIFY_RESPONSE_AVAILABLE;
break;
case NCM_NOTIFY_SPEED:
@@ -830,7 +847,7 @@
*/
pr_debug("dev:%p\n", mbim);
- mbim->not_port.notify_state = NCM_NOTIFY_SPEED;
+ mbim->not_port.notify_state = NCM_NOTIFY_RESPONSE_AVAILABLE;
mbim_do_notify(mbim);
}
@@ -1365,6 +1382,8 @@
pr_info("SET DEVICE OFFLINE");
atomic_set(&mbim->online, 0);
+ mbim->not_port.notify_state = NCM_NOTIFY_NONE;
+
mbim_clear_queues(mbim);
mbim_reset_function_queue(mbim);
@@ -1674,7 +1693,7 @@
}
while (list_empty(&dev->cpkt_req_q)) {
- pr_err("Requests list is empty. Wait.\n");
+ pr_debug("Requests list is empty. Wait.\n");
ret = wait_event_interruptible(dev->read_wq,
!list_empty(&dev->cpkt_req_q));
if (ret < 0) {
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index fc4d1b6..3ec158b 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -1933,6 +1933,12 @@
struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
struct msm_hsic_host_platform_data *pdata = mehci->dev->platform_data;
+ /* If the device was removed no need to call pm_runtime_disable */
+ if (pdev->dev.power.power_state.event != PM_EVENT_INVALID)
+ pm_runtime_disable(&pdev->dev);
+
+ pm_runtime_set_suspended(&pdev->dev);
+
/* Remove the HCD prior to releasing our resources. */
usb_remove_hcd(hcd);
@@ -1966,12 +1972,6 @@
ehci_hsic_msm_debugfs_cleanup();
device_init_wakeup(&pdev->dev, 0);
- /* If the device was removed no need to call pm_runtime_disable */
- if (pdev->dev.power.power_state.event != PM_EVENT_INVALID)
- pm_runtime_disable(&pdev->dev);
-
- pm_runtime_set_suspended(&pdev->dev);
-
destroy_workqueue(ehci_wq);
msm_hsic_config_gpios(mehci, 0);
diff --git a/drivers/video/msm/mdss/mdss.h b/drivers/video/msm/mdss/mdss.h
index c69676f..b6882b8 100644
--- a/drivers/video/msm/mdss/mdss.h
+++ b/drivers/video/msm/mdss/mdss.h
@@ -57,7 +57,6 @@
};
struct mdss_data_type {
- u32 rev;
u32 mdp_rev;
struct clk *mdp_clk[MDSS_MAX_CLK];
struct regulator *fs;
diff --git a/drivers/video/msm/mdss/mdss_fb.c b/drivers/video/msm/mdss/mdss_fb.c
index 79115d8..e1e82fd 100644
--- a/drivers/video/msm/mdss/mdss_fb.c
+++ b/drivers/video/msm/mdss/mdss_fb.c
@@ -618,6 +618,12 @@
static int mdss_fb_blank(int blank_mode, struct fb_info *info)
{
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
+ if (blank_mode == FB_BLANK_POWERDOWN) {
+ struct fb_event event;
+ event.info = info;
+ event.data = &blank_mode;
+ fb_notifier_call_chain(FB_EVENT_BLANK, &event);
+ }
mdss_fb_pan_idle(mfd);
if (mfd->op_enable == 0) {
if (blank_mode == FB_BLANK_UNBLANK)
diff --git a/drivers/video/msm/mdss/mdss_mdp.c b/drivers/video/msm/mdss/mdss_mdp.c
index ce5f707..308ae87 100644
--- a/drivers/video/msm/mdss/mdss_mdp.c
+++ b/drivers/video/msm/mdss/mdss_mdp.c
@@ -27,6 +27,7 @@
#include <linux/iommu.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/memory_alloc.h>
@@ -55,7 +56,6 @@
static DEFINE_SPINLOCK(mdp_lock);
static DEFINE_MUTEX(mdp_clk_lock);
-static DEFINE_MUTEX(mdp_suspend_mutex);
#define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val) \
{ \
@@ -111,7 +111,7 @@
static DEFINE_SPINLOCK(mdss_lock);
struct mdss_hw *mdss_irq_handlers[MDSS_MAX_HW_BLK];
-static int mdss_mdp_register_early_suspend(struct mdss_data_type *mdata);
+static void mdss_mdp_footswitch_ctrl(struct mdss_data_type *mdata, int on);
static int mdss_mdp_parse_dt(struct platform_device *pdev);
static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev);
static int mdss_mdp_parse_dt_mixer(struct platform_device *pdev);
@@ -612,8 +612,7 @@
pr_err("unable to get gdsc regulator\n");
return -EINVAL;
}
- regulator_enable(mdata->fs);
- mdata->fs_ena = true;
+ mdata->fs_ena = false;
if (mdss_mdp_irq_clk_register(mdata, "bus_clk", MDSS_CLK_AXI) ||
mdss_mdp_irq_clk_register(mdata, "iface_clk", MDSS_CLK_AHB) ||
@@ -673,7 +672,7 @@
int i;
if (!mdata->iommu_attached) {
- pr_warn("mdp iommu already dettached\n");
+ pr_debug("mdp iommu already dettached\n");
return 0;
}
@@ -754,9 +753,12 @@
static int mdss_hw_init(struct mdss_data_type *mdata)
{
+ int i, j;
+ char *offset;
+
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- mdata->rev = MDSS_MDP_REG_READ(MDSS_REG_HW_VERSION);
mdata->mdp_rev = MDSS_MDP_REG_READ(MDSS_MDP_REG_HW_VERSION);
+ pr_info_once("MDP Rev=%x\n", mdata->mdp_rev);
if (mdata->hw_settings) {
struct mdss_hw_settings *hws = mdata->hw_settings;
@@ -766,6 +768,16 @@
hws++;
}
}
+
+ for (i = 0; i < mdata->nmixers_intf; i++) {
+ offset = mdata->mixer_intf[i].dspp_base +
+ MDSS_MDP_REG_DSPP_HIST_LUT_BASE;
+ for (j = 0; j < ENHIST_LUT_ENTRIES; j++)
+ writel_relaxed(j, offset);
+
+ /* swap */
+ writel_relaxed(i, offset + 4);
+ }
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
pr_debug("MDP hw init done\n");
@@ -798,8 +810,6 @@
mdata->smp_mb_cnt = MDSS_MDP_SMP_MMB_BLOCKS;
mdata->smp_mb_size = MDSS_MDP_SMP_MMB_SIZE;
- pr_info("mdss_revision=%x\n", mdata->rev);
- pr_info("mdp_hw_revision=%x\n", mdata->mdp_rev);
mdata->iclient = msm_ion_client_create(-1, mdata->pdev->name);
if (IS_ERR_OR_NULL(mdata->iclient)) {
@@ -809,10 +819,6 @@
}
rc = mdss_iommu_init(mdata);
- if (!IS_ERR_VALUE(rc))
- mdss_iommu_attach(mdata);
-
- rc = mdss_hw_init(mdata);
return rc;
}
@@ -910,15 +916,16 @@
goto probe_done;
}
- rc = mdss_mdp_register_early_suspend(mdata);
+ rc = mdss_mdp_debug_init(mdata);
if (rc) {
- pr_err("unable to register early suspend\n");
+ pr_err("unable to initialize mdp debugging\n");
goto probe_done;
}
- rc = mdss_mdp_debug_init(mdata);
- if (rc)
- pr_err("unable to initialize mdp debugging\n");
+ pm_runtime_set_suspended(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+ if (!pm_runtime_enabled(&pdev->dev))
+ mdss_mdp_footswitch_ctrl(mdata, true);
probe_done:
if (IS_ERR_VALUE(rc)) {
@@ -1320,16 +1327,14 @@
static void mdss_mdp_footswitch_ctrl(struct mdss_data_type *mdata, int on)
{
- mutex_lock(&mdp_suspend_mutex);
- if (!mdata->suspend || !mdata->fs) {
- mutex_unlock(&mdp_suspend_mutex);
+ if (!mdata->fs)
return;
- }
if (on && !mdata->fs_ena) {
pr_debug("Enable MDP FS\n");
regulator_enable(mdata->fs);
mdss_iommu_attach(mdata);
+ mdss_hw_init(mdata);
mdata->fs_ena = true;
} else if (!on && mdata->fs_ena) {
pr_debug("Disable MDP FS\n");
@@ -1337,7 +1342,6 @@
regulator_disable(mdata->fs);
mdata->fs_ena = false;
}
- mutex_unlock(&mdp_suspend_mutex);
}
static inline int mdss_mdp_suspend_sub(struct mdss_data_type *mdata)
@@ -1350,18 +1354,6 @@
return ret;
}
- flush_workqueue(mdata->clk_ctrl_wq);
-
- mutex_lock(&mdp_suspend_mutex);
- mdata->suspend = true;
- mutex_unlock(&mdp_suspend_mutex);
-
- if (mdata->clk_ena) {
- pr_err("MDP suspend failed\n");
- return -EBUSY;
- }
- mdss_mdp_footswitch_ctrl(mdata, false);
-
pr_debug("suspend done\n");
return 0;
@@ -1371,11 +1363,6 @@
{
int ret = 0;
- mdss_mdp_footswitch_ctrl(mdata, true);
- mutex_lock(&mdp_suspend_mutex);
- mdata->suspend = false;
- mutex_unlock(&mdp_suspend_mutex);
- mdss_hw_init(mdata);
ret = mdss_fb_resume_all();
if (IS_ERR_VALUE(ret))
pr_err("Unable to resume all fb panels (%d)\n", ret);
@@ -1385,7 +1372,37 @@
return ret;
}
-#if defined(CONFIG_PM) && !defined(CONFIG_HAS_EARLYSUSPEND)
+#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
+static int mdss_mdp_pm_suspend(struct device *dev)
+{
+ struct mdss_data_type *mdata;
+
+ mdata = dev_get_drvdata(dev);
+ if (!mdata)
+ return -ENODEV;
+
+ dev_dbg(dev, "display pm suspend\n");
+
+ return mdss_mdp_suspend_sub(mdata);
+}
+
+static int mdss_mdp_pm_resume(struct device *dev)
+{
+ struct mdss_data_type *mdata;
+
+ mdata = dev_get_drvdata(dev);
+ if (!mdata)
+ return -ENODEV;
+
+ dev_dbg(dev, "display pm resume\n");
+
+ return mdss_mdp_resume_sub(mdata);
+}
+
+#define mdss_mdp_suspend NULL
+#define mdss_mdp_resume NULL
+#else
static int mdss_mdp_suspend(struct platform_device *pdev, pm_message_t state)
{
struct mdss_data_type *mdata = platform_get_drvdata(pdev);
@@ -1393,7 +1410,7 @@
if (!mdata)
return -ENODEV;
- pr_debug("display suspend\n");
+ dev_dbg(&pdev->dev, "display suspend\n");
return mdss_mdp_suspend_sub(mdata);
}
@@ -1405,62 +1422,63 @@
if (!mdata)
return -ENODEV;
- pr_debug("display resume\n");
+ dev_dbg(&pdev->dev, "display resume\n");
return mdss_mdp_resume_sub(mdata);
}
-#else
-#define mdss_mdp_suspend NULL
-#define mdss_mdp_resume NULL
#endif
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void mdss_mdp_early_suspend(struct early_suspend *h)
+#ifdef CONFIG_PM_RUNTIME
+static int mdss_mdp_runtime_resume(struct device *dev)
{
- struct mdss_data_type *mdata;
- mdata = container_of(h, struct mdss_data_type, early_suspend);
+ struct mdss_data_type *mdata = dev_get_drvdata(dev);
+ if (!mdata)
+ return -ENODEV;
- pr_debug("display early suspend\n");
+ dev_dbg(dev, "pm_runtime: resuming...\n");
- mdss_mdp_suspend_sub(mdata);
-}
-
-static void mdss_mdp_late_resume(struct early_suspend *h)
-{
- struct mdss_data_type *mdata;
- mdata = container_of(h, struct mdss_data_type, early_suspend);
-
- pr_debug("display early resume\n");
-
- mdss_mdp_resume_sub(mdata);
-}
-
-static int mdss_mdp_register_early_suspend(struct mdss_data_type *mdata)
-{
- mdata->early_suspend.suspend = mdss_mdp_early_suspend;
- mdata->early_suspend.resume = mdss_mdp_late_resume;
- mdata->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
- register_early_suspend(&mdata->early_suspend);
+ mdss_mdp_footswitch_ctrl(mdata, true);
return 0;
}
-static int mdss_mdp_remove_early_suspend(struct mdss_data_type *mdata)
+static int mdss_mdp_runtime_idle(struct device *dev)
{
- unregister_early_suspend(&mdata->early_suspend);
+ struct mdss_data_type *mdata = dev_get_drvdata(dev);
+ if (!mdata)
+ return -ENODEV;
+
+ dev_dbg(dev, "pm_runtime: idling...\n");
+
+ flush_workqueue(mdata->clk_ctrl_wq);
return 0;
}
-#else
-static int mdss_mdp_register_early_suspend(struct mdss_data_type *mdata)
+
+static int mdss_mdp_runtime_suspend(struct device *dev)
{
- return 0;
-}
-static int mdss_mdp_remove_early_suspend(struct mdss_data_type *mdata)
-{
+ struct mdss_data_type *mdata = dev_get_drvdata(dev);
+ if (!mdata)
+ return -ENODEV;
+ dev_dbg(dev, "pm_runtime: suspending...\n");
+
+ if (mdata->clk_ena) {
+ pr_err("MDP suspend failed\n");
+ return -EBUSY;
+ }
+ mdss_mdp_footswitch_ctrl(mdata, false);
+
return 0;
}
#endif
+#endif
+
+static const struct dev_pm_ops mdss_mdp_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mdss_mdp_pm_suspend, mdss_mdp_pm_resume)
+ SET_RUNTIME_PM_OPS(mdss_mdp_runtime_suspend,
+ mdss_mdp_runtime_resume,
+ mdss_mdp_runtime_idle)
+};
static int mdss_mdp_remove(struct platform_device *pdev)
{
@@ -1470,7 +1488,6 @@
pm_runtime_disable(&pdev->dev);
mdss_mdp_pp_term(&pdev->dev);
mdss_mdp_bus_scale_unregister(mdata);
- mdss_mdp_remove_early_suspend(mdata);
mdss_debugfs_remove(mdata);
return 0;
}
@@ -1494,6 +1511,7 @@
*/
.name = "mdp",
.of_match_table = mdss_mdp_dt_match,
+ .pm = &mdss_mdp_pm_ops,
},
};
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index 63a1aa4..0f52125 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -267,6 +267,13 @@
mutex_lock(&mdss_mdp_ctl_lock);
ctl->ref_cnt--;
+ ctl->mixer_left = NULL;
+ ctl->mixer_right = NULL;
+ ctl->power_on = false;
+ ctl->start_fnc = NULL;
+ ctl->stop_fnc = NULL;
+ ctl->prepare_fnc = NULL;
+ ctl->display_fnc = NULL;
mutex_unlock(&mdss_mdp_ctl_lock);
return 0;
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_video.c b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
index 1aea4e0..0d4037c 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_video.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_video.c
@@ -251,6 +251,7 @@
NULL, NULL);
ctx->ref_cnt--;
+ ctl->priv_data = NULL;
return 0;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index 283d3f0..a8764cb 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -18,6 +18,7 @@
#include <linux/kernel.h>
#include <linux/major.h>
#include <linux/module.h>
+#include <linux/pm_runtime.h>
#include <linux/uaccess.h>
#include <mach/iommu_domains.h>
@@ -84,11 +85,7 @@
return -EOVERFLOW;
}
- if (req->flags & MDSS_MDP_ROT_ONLY) {
- /* dst res should match src res in rotation only mode*/
- req->dst_rect.w = req->src_rect.w;
- req->dst_rect.h = req->src_rect.h;
- } else {
+ if (!(req->flags & MDSS_MDP_ROT_ONLY)) {
u32 dst_w, dst_h;
if ((CHECK_BOUNDS(req->dst_rect.x, req->dst_rect.w, xres) ||
@@ -479,9 +476,22 @@
int mdss_mdp_overlay_kickoff(struct mdss_mdp_ctl *ctl)
{
struct msm_fb_data_type *mfd = ctl->mfd;
+ struct mdss_mdp_pipe *pipe;
int ret;
mutex_lock(&mfd->ov_lock);
+ mutex_lock(&mfd->lock);
+ list_for_each_entry(pipe, &mfd->pipes_used, used_list) {
+ if (pipe->params_changed || pipe->back_buf.num_planes) {
+ ret = mdss_mdp_pipe_queue_data(pipe, &pipe->back_buf);
+ if (IS_ERR_VALUE(ret)) {
+ pr_warn("Unable to queue data for pnum=%d\n",
+ pipe->num);
+ mdss_mdp_overlay_free_buf(&pipe->back_buf);
+ }
+ }
+ }
+ mutex_unlock(&mfd->lock);
if (mfd->kickoff_fnc)
ret = mfd->kickoff_fnc(ctl);
@@ -580,6 +590,13 @@
unset_ndx |= pipe->ndx;
cnt++;
}
+
+ if (cnt == 0 && !list_empty(&mfd->pipes_cleanup)) {
+ pr_warn("overlay release on fb%d called without commit!",
+ mfd->index);
+ cnt++;
+ }
+
mutex_unlock(&mfd->lock);
if (unset_ndx) {
@@ -653,7 +670,6 @@
static int mdss_mdp_overlay_queue(struct msm_fb_data_type *mfd,
struct msmfb_overlay_data *req)
{
- struct mdss_mdp_ctl *ctl;
struct mdss_mdp_pipe *pipe;
struct mdss_mdp_data *src_data;
int ret;
@@ -679,12 +695,7 @@
ret = mdss_mdp_overlay_get_buf(mfd, src_data, &req->data, 1, flags);
if (IS_ERR_VALUE(ret)) {
pr_err("src_data pmem error\n");
- } else {
- ret = mdss_mdp_pipe_queue_data(pipe, src_data);
- if (IS_ERR_VALUE(ret))
- mdss_mdp_overlay_free_buf(src_data);
}
- ctl = pipe->mixer->ctl;
mdss_mdp_pipe_unmap(pipe);
return ret;
@@ -1291,12 +1302,16 @@
mfd->ctl = ctl;
}
+ pm_runtime_get_sync(&mfd->pdev->dev);
+
rc = mdss_mdp_ctl_start(mfd->ctl);
if (rc == 0) {
atomic_inc(&ov_active_panels);
} else {
mdss_mdp_ctl_destroy(mfd->ctl);
mfd->ctl = NULL;
+
+ pm_runtime_put(&mfd->pdev->dev);
}
return rc;
@@ -1329,6 +1344,8 @@
if (atomic_dec_return(&ov_active_panels) == 0)
mdss_mdp_rotator_release_all();
+
+ pm_runtime_put(&mfd->pdev->dev);
}
return rc;
@@ -1369,6 +1386,9 @@
return rc;
}
+ pm_runtime_set_suspended(&mfd->pdev->dev);
+ pm_runtime_enable(&mfd->pdev->dev);
+
kobject_uevent(&dev->kobj, KOBJ_ADD);
pr_debug("vsync kobject_uevent(KOBJ_ADD)\n");
diff --git a/drivers/video/msm/mdss/mdss_mdp_pp.c b/drivers/video/msm/mdss/mdss_mdp_pp.c
index ee48f31..851d608 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pp.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pp.c
@@ -844,9 +844,6 @@
int mdss_mdp_pp_init(struct device *dev)
{
int ret = 0;
- int i;
- u32 offset;
- uint32_t data[ENHIST_LUT_ENTRIES];
mutex_lock(&mdss_pp_mutex);
if (!mdss_pp_res) {
@@ -856,20 +853,6 @@
pr_err("%s mdss_pp_res allocation failed!", __func__);
ret = -ENOMEM;
}
-
- for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
- data[i] = i;
-
- mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- /* Initialize Histogram LUT for all DSPPs */
- for (i = 0; i < MDSS_MDP_MAX_DSPP; i++) {
- offset = MDSS_MDP_REG_DSPP_OFFSET(i) +
- MDSS_MDP_REG_DSPP_HIST_LUT_BASE;
- mdss_pp_res->enhist_disp_cfg[i].data = data;
- pp_update_hist_lut(offset,
- &mdss_pp_res->enhist_disp_cfg[i]);
- }
- mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
}
mutex_unlock(&mdss_pp_mutex);
return ret;
diff --git a/include/linux/qpnp/qpnp-adc.h b/include/linux/qpnp/qpnp-adc.h
index a3347c4..1849cee 100644
--- a/include/linux/qpnp/qpnp-adc.h
+++ b/include/linux/qpnp/qpnp-adc.h
@@ -1149,6 +1149,23 @@
*/
int32_t qpnp_adc_usb_scaler(struct qpnp_adc_tm_usbid_param *param,
uint32_t *low_threshold, uint32_t *high_threshold);
+/**
+ * qpnp_vadc_iadc_sync_request() - Performs Voltage ADC read and
+ * locks the peripheral. When performing simultaneous
+ * voltage and current request the VADC peripheral is
+ * prepared for conversion and the IADC sync conversion
+ * is done from the IADC peripheral.
+ * @channel: Input channel to perform the voltage ADC read.
+ */
+int32_t qpnp_vadc_iadc_sync_request(enum qpnp_vadc_channels channel);
+/**
+ * qpnp_vadc_iadc_sync_complete_request() - Reads the ADC result and
+ * unlocks the peripheral.
+ * @result: Structure pointer of type adc_chan_result
+ * in which the ADC read results are stored.
+ */
+int32_t qpnp_vadc_iadc_sync_complete_request(
+ enum qpnp_vadc_channels channel, struct qpnp_vadc_result *result);
#else
static inline int32_t qpnp_vadc_read(uint32_t channel,
struct qpnp_vadc_result *result)
@@ -1218,6 +1235,13 @@
static inline int32_t qpnp_adc_tm_scale_voltage_therm_pu2(
uint32_t reg, int64_t *result)
{ return -ENXIO; }
+static inline int32_t qpnp_vadc_iadc_sync_request(
+ enum qpnp_vadc_channels channel)
+{ return -ENXIO; }
+static inline int32_t qpnp_vadc_iadc_sync_complete_request(
+ enum qpnp_vadc_channels channel,
+ struct qpnp_vadc_result *result)
+{ return -ENXIO; }
#endif
/* Public API */
@@ -1226,7 +1250,7 @@
/**
* qpnp_iadc_read() - Performs ADC read on the current channel.
* @channel: Input channel to perform the ADC read.
- * @result: Current across rsens in mV.
+ * @result: Current across rsense in mA.
*/
int32_t qpnp_iadc_read(enum qpnp_iadc_channels channel,
struct qpnp_iadc_result *result);
@@ -1245,7 +1269,6 @@
* type qpnp_iadc_calib.
*/
int32_t qpnp_iadc_get_gain_and_offset(struct qpnp_iadc_calib *result);
-
/**
* qpnp_iadc_is_ready() - Clients can use this API to check if the
* device is ready to use.
@@ -1253,15 +1276,34 @@
* has not occured.
*/
int32_t qpnp_iadc_is_ready(void);
+/**
+ * qpnp_iadc_vadc_sync_read() - Performs synchronous VADC and IADC read.
+ * The api is to be used only by the BMS to perform
+ * simultaneous VADC and IADC measurement for battery voltage
+ * and current.
+ * @i_channel: Input battery current channel to perform the IADC read.
+ * @i_result: Current across the rsense in mA.
+ * @v_channel: Input battery voltage channel to perform VADC read.
+ * @v_result: Voltage on the vbatt channel with units in mV.
+ */
+int32_t qpnp_iadc_vadc_sync_read(
+ enum qpnp_iadc_channels i_channel, struct qpnp_iadc_result *i_result,
+ enum qpnp_vadc_channels v_channel, struct qpnp_vadc_result *v_result);
#else
static inline int32_t qpnp_iadc_read(enum qpnp_iadc_channels channel,
struct qpnp_iadc_result *result)
{ return -ENXIO; }
+static inline int32_t qpnp_iadc_get_rsense(int32_t *rsense)
+{ return -ENXIO; }
static inline int32_t qpnp_iadc_get_gain_and_offset(struct qpnp_iadc_calib
*result)
{ return -ENXIO; }
static inline int32_t qpnp_iadc_is_ready(void)
{ return -ENXIO; }
+static inline int32_t qpnp_iadc_vadc_sync_read(
+ enum qpnp_iadc_channels i_channel, struct qpnp_iadc_result *i_result,
+ enum qpnp_vadc_channels v_channel, struct qpnp_vadc_result *v_result)
+{ return -ENXIO; }
#endif
/* Public API */
@@ -1323,8 +1365,6 @@
{ return -ENXIO; }
static inline int32_t qpnp_adc_tm_is_ready(void)
{ return -ENXIO; }
-static inline int32_t qpnp_iadc_get_rsense(int32_t *rsense)
-{ return -ENXIO; }
#endif
#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index df34213..155585a 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -298,6 +298,9 @@
config SND_SOC_WCD9306
tristate
+config SND_SOC_MSM8X10_WCD
+ tristate
+
config SND_SOC_WL1273
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 11338aa..0f14dc3 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -52,7 +52,8 @@
snd-soc-wcd9310-objs := wcd9310.o wcd9310-tables.o
snd-soc-cs8427-objs := cs8427.o
snd-soc-wcd9320-objs := wcd9xxx-resmgr.o wcd9320.o wcd9320-tables.o wcd9xxx-mbhc.o
-snd-soc-wcd9306-objs := wcd9xxx-resmgr.o wcd9306.o wcd9306-tables.o wcd9xxx-mbhc.o
+snd-soc-wcd9306-objs := wcd9306.o wcd9306-tables.o
+snd-soc-msm8x10-wcd-objs := msm8x10-wcd.o msm8x10-wcd-tables.o
snd-soc-wl1273-objs := wl1273.o
snd-soc-wm1250-ev1-objs := wm1250-ev1.o
snd-soc-wm2000-objs := wm2000.o
@@ -163,7 +164,8 @@
obj-$(CONFIG_SND_SOC_WCD9310) += snd-soc-wcd9310.o
obj-$(CONFIG_SND_SOC_CS8427) += snd-soc-cs8427.o
obj-$(CONFIG_SND_SOC_WCD9320) += snd-soc-wcd9320.o
-obj-$(CONFIG_SND_SOC_WCD9306) += snd-soc-wcd9306.o
+obj-$(CONFIG_SND_SOC_WCD9306) += snd-soc-wcd9306.o wcd9xxx-resmgr.o wcd9xxx-mbhc.o
+obj-$(CONFIG_SND_SOC_MSM8X10_WCD) += snd-soc-msm8x10-wcd.o wcd9xxx-resmgr.o
obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o
obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o
diff --git a/sound/soc/codecs/msm8x10-wcd-tables.c b/sound/soc/codecs/msm8x10-wcd-tables.c
new file mode 100644
index 0000000..7e0263d
--- /dev/null
+++ b/sound/soc/codecs/msm8x10-wcd-tables.c
@@ -0,0 +1,794 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <msm8x10_wcd_registers.h>
+#include "msm8x10-wcd.h"
+
+const u8 msm8x10_wcd_reg_readable[MSM8X10_WCD_CACHE_SIZE] = {
+ [MSM8X10_WCD_A_CHIP_CTL] = 1,
+ [MSM8X10_WCD_A_CHIP_STATUS] = 1,
+ [MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT] = 1,
+ [MSM8X10_WCD_A_MODE_LOCK] = 0,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_0] = 1,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_1] = 1,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_2] = 1,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_3] = 1,
+ [MSM8X10_WCD_A_CHIP_VERSION] = 1,
+ [MSM8X10_WCD_A_ANALOG_SLAVE_ID] = 1,
+ [MSM8X10_WCD_A_PIN_CTL_OE] = 1,
+ [MSM8X10_WCD_A_PIN_CTL_DATA] = 1,
+ [MSM8X10_WCD_A_PIN_STATUS] = 1,
+ [MSM8X10_WCD_A_HDRIVE_CTL] = 1,
+ [MSM8X10_WCD_A_HDRIVE_I2C_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RST_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TOP_CLK_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_ANA_CLK_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_DIG_CLK_CTL] = 1,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL0] = 1,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL1] = 1,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL2] = 1,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL3] = 1,
+ [MSM8X10_WCD_A_QFUSE_CTL] = 1,
+ [MSM8X10_WCD_A_QFUSE_STATUS] = 1,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT0] = 1,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT1] = 1,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT2] = 1,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT3] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_TX1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_TX2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX3_CTL] = 1,
+ [MSM8X10_WCD_A_DIGITAL_DEBUG_CTL] = 1,
+ [MSM8X10_WCD_A_ANALOG_DEBUG_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_CTL] = 1,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA0] = 1,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA1] = 1,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA2] = 1,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA3] = 1,
+ [MSM8X10_WCD_A_SPARE_0] = 1,
+ [MSM8X10_WCD_A_SPARE_1] = 1,
+ [MSM8X10_WCD_A_SPARE_2] = 1,
+ [MSM8X10_WCD_A_INTR_MODE] = 1,
+ [MSM8X10_WCD_A_INTR_MASK0] = 1,
+ [MSM8X10_WCD_A_INTR_MASK1] = 1,
+ [MSM8X10_WCD_A_INTR_MASK2] = 1,
+ [MSM8X10_WCD_A_INTR_STATUS0] = 1,
+ [MSM8X10_WCD_A_INTR_STATUS1] = 1,
+ [MSM8X10_WCD_A_INTR_STATUS2] = 1,
+ [MSM8X10_WCD_A_INTR_CLEAR0] = 0,
+ [MSM8X10_WCD_A_INTR_CLEAR1] = 0,
+ [MSM8X10_WCD_A_INTR_CLEAR2] = 0,
+ [MSM8X10_WCD_A_INTR_TEST0] = 1,
+ [MSM8X10_WCD_A_INTR_TEST1] = 1,
+ [MSM8X10_WCD_A_INTR_TEST2] = 1,
+ [MSM8X10_WCD_A_INTR_SET0] = 1,
+ [MSM8X10_WCD_A_INTR_SET1] = 1,
+ [MSM8X10_WCD_A_INTR_SET2] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_EN_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_B1_STATUS] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_B2_STATUS] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_B3_STATUS] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_B4_STATUS] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_B5_STATUS] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_CLK_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_INT_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_MBHC_SPARE] = 1,
+ [MSM8X10_WCD_A_BIAS_REF_CTL] = 1,
+ [MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL] = 1,
+ [MSM8X10_WCD_A_BIAS_PRECHRG_CTL] = 1,
+ [MSM8X10_WCD_A_BIAS_CURR_CTL_1] = 1,
+ [MSM8X10_WCD_A_BIAS_CURR_CTL_2] = 1,
+ [MSM8X10_WCD_A_BIAS_OSC_BG_CTL] = 1,
+ [MSM8X10_WCD_A_MICB_CFILT_1_CTL] = 1,
+ [MSM8X10_WCD_A_MICB_CFILT_1_VAL] = 1,
+ [MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG] = 1,
+ [MSM8X10_WCD_A_MICB_1_CTL] = 1,
+ [MSM8X10_WCD_A_MICB_1_INT_RBIAS] = 1,
+ [MSM8X10_WCD_A_MICB_1_MBHC] = 1,
+ [MSM8X10_WCD_A_MBHC_INSERT_DETECT] = 1,
+ [MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS] = 1,
+ [MSM8X10_WCD_A_TX_COM_BIAS] = 1,
+ [MSM8X10_WCD_A_MBHC_SCALING_MUX_1] = 1,
+ [MSM8X10_WCD_A_MBHC_SCALING_MUX_2] = 1,
+ [MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL] = 1,
+ [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1] = 1,
+ [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2] = 1,
+ [MSM8X10_WCD_A_TX_1_EN] = 1,
+ [MSM8X10_WCD_A_TX_2_EN] = 1,
+ [MSM8X10_WCD_A_TX_1_2_ADC_CH1] = 1,
+ [MSM8X10_WCD_A_TX_1_2_ADC_CH2] = 1,
+ [MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL] = 1,
+ [MSM8X10_WCD_A_TX_1_2_TEST_CTL] = 1,
+ [MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN] = 1,
+ [MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV] = 1,
+ [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1] = 1,
+ [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2] = 1,
+ [MSM8X10_WCD_A_TX_3_EN] = 1,
+ [MSM8X10_WCD_A_TX_1_2_TEST_EN] = 1,
+ [MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL] = 1,
+ [MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR] = 1,
+ [MSM8X10_WCD_A_CP_EN] = 1,
+ [MSM8X10_WCD_A_CP_CLK] = 1,
+ [MSM8X10_WCD_A_CP_STATIC] = 1,
+ [MSM8X10_WCD_A_CP_DCC1] = 1,
+ [MSM8X10_WCD_A_CP_DCC3] = 1,
+ [MSM8X10_WCD_A_CP_ATEST] = 1,
+ [MSM8X10_WCD_A_CP_DTEST] = 1,
+ [MSM8X10_WCD_A_RX_AUX_SW_CTL] = 1,
+ [MSM8X10_WCD_A_RX_PA_AUX_IN_CONN] = 1,
+ [MSM8X10_WCD_A_RX_COM_TIMER_DIV] = 1,
+ [MSM8X10_WCD_A_RX_COM_OCP_CTL] = 1,
+ [MSM8X10_WCD_A_RX_COM_OCP_COUNT] = 1,
+ [MSM8X10_WCD_A_RX_COM_DAC_CTL] = 1,
+ [MSM8X10_WCD_A_RX_COM_BIAS] = 1,
+ [MSM8X10_WCD_A_RX_HPH_AUTO_CHOP] = 1,
+ [MSM8X10_WCD_A_RX_HPH_CHOP_CTL] = 1,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_PA] = 1,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_LDO] = 1,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_CNP] = 1,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP] = 1,
+ [MSM8X10_WCD_A_RX_HPH_OCP_CTL] = 1,
+ [MSM8X10_WCD_A_RX_HPH_CNP_EN] = 1,
+ [MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL] = 1,
+ [MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME] = 1,
+ [MSM8X10_WCD_A_RX_HPH_L_GAIN] = 1,
+ [MSM8X10_WCD_A_RX_HPH_L_TEST] = 1,
+ [MSM8X10_WCD_A_RX_HPH_L_PA_CTL] = 1,
+ [MSM8X10_WCD_A_RX_HPH_L_DAC_CTL] = 1,
+ [MSM8X10_WCD_A_RX_HPH_L_ATEST] = 1,
+ [MSM8X10_WCD_A_RX_HPH_L_STATUS] = 1,
+ [MSM8X10_WCD_A_RX_HPH_R_GAIN] = 1,
+ [MSM8X10_WCD_A_RX_HPH_R_TEST] = 1,
+ [MSM8X10_WCD_A_RX_HPH_R_PA_CTL] = 1,
+ [MSM8X10_WCD_A_RX_HPH_R_DAC_CTL] = 1,
+ [MSM8X10_WCD_A_RX_HPH_R_ATEST] = 1,
+ [MSM8X10_WCD_A_RX_HPH_R_STATUS] = 1,
+ [MSM8X10_WCD_A_RX_EAR_BIAS_PA] = 1,
+ [MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF] = 1,
+ [MSM8X10_WCD_A_RX_EAR_EN] = 1,
+ [MSM8X10_WCD_A_RX_EAR_GAIN] = 1,
+ [MSM8X10_WCD_A_RX_EAR_CMBUFF] = 1,
+ [MSM8X10_WCD_A_RX_EAR_ICTL] = 1,
+ [MSM8X10_WCD_A_RX_EAR_CCOMP] = 1,
+ [MSM8X10_WCD_A_RX_EAR_VCM] = 1,
+ [MSM8X10_WCD_A_RX_EAR_CNP] = 1,
+ [MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST] = 1,
+ [MSM8X10_WCD_A_RX_EAR_STATUS] = 1,
+ [MSM8X10_WCD_A_RX_LINE_BIAS_PA] = 1,
+ [MSM8X10_WCD_A_RX_BUCK_BIAS1] = 1,
+ [MSM8X10_WCD_A_RX_BUCK_BIAS2] = 1,
+ [MSM8X10_WCD_A_RX_LINE_COM] = 1,
+ [MSM8X10_WCD_A_RX_LINE_CNP_EN] = 1,
+ [MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL] = 1,
+ [MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME] = 1,
+ [MSM8X10_WCD_A_RX_LINE_1_GAIN] = 1,
+ [MSM8X10_WCD_A_RX_LINE_1_TEST] = 1,
+ [MSM8X10_WCD_A_RX_LINE_1_DAC_CTL] = 1,
+ [MSM8X10_WCD_A_RX_LINE_1_STATUS] = 1,
+ [MSM8X10_WCD_A_RX_LINE_CNP_DBG] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_EN] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_GAIN] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_DAC_CTL] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_OCP_CTL] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_CLIP_DET] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_IEC] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_DBG_DAC] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_DBG_PA] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_BIAS_INT] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_BIAS_PA] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP] = 1,
+ [MSM8X10_WCD_A_SPKR_DRV_STATUS_PA] = 1,
+ [MSM8X10_WCD_A_RC_OSC_FREQ] = 1,
+ [MSM8X10_WCD_A_RC_OSC_TEST] = 1,
+ [MSM8X10_WCD_A_RC_OSC_STATUS] = 1,
+ [MSM8X10_WCD_A_RC_OSC_TUNER] = 1,
+ [MSM8X10_WCD_A_MBHC_HPH] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_OTHR_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_MCLK_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_PDM_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLK_SD_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_B5_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_B5_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_B5_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_B6_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_B6_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_B6_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG] = 1,
+ [MSM8X10_WCD_A_CDC_CLSG_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER] = 1,
+ [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER] = 1,
+ [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN] = 1,
+ [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN] = 1,
+ [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG] = 1,
+ [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG] = 1,
+ [MSM8X10_WCD_A_CDC_TX1_MUX_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TX2_MUX_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TX1_DMIC_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TX2_DMIC_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE] = 1,
+ [MSM8X10_WCD_A_CDC_TOP_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_DEBUG_B1_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_DEBUG_B2_CTL] = 1,
+ [MSM8X10_WCD_A_CDC_DEBUG_B3_CTL] = 1,
+};
+
+const u8 msm8x10_wcd_reset_reg_defaults[MSM8X10_WCD_CACHE_SIZE] = {
+ [MSM8X10_WCD_A_CHIP_CTL] = MSM8X10_WCD_A_CHIP_CTL__POR,
+ [MSM8X10_WCD_A_CHIP_STATUS] = MSM8X10_WCD_A_CHIP_STATUS__POR,
+ [MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT] =
+ MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT__POR,
+ [MSM8X10_WCD_A_MODE_LOCK] = MSM8X10_WCD_A_MODE_LOCK__POR,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_0] = MSM8X10_WCD_A_CHIP_ID_BYTE_0__POR,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_1] = MSM8X10_WCD_A_CHIP_ID_BYTE_1__POR,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_2] = MSM8X10_WCD_A_CHIP_ID_BYTE_2__POR,
+ [MSM8X10_WCD_A_CHIP_ID_BYTE_3] = MSM8X10_WCD_A_CHIP_ID_BYTE_3__POR,
+ [MSM8X10_WCD_A_CHIP_VERSION] = MSM8X10_WCD_A_CHIP_VERSION__POR,
+ [MSM8X10_WCD_A_ANALOG_SLAVE_ID] = MSM8X10_WCD_A_ANALOG_SLAVE_ID__POR,
+ [MSM8X10_WCD_A_PIN_CTL_OE] = MSM8X10_WCD_A_PIN_CTL_OE__POR,
+ [MSM8X10_WCD_A_PIN_CTL_DATA] = MSM8X10_WCD_A_PIN_CTL_DATA__POR,
+ [MSM8X10_WCD_A_PIN_STATUS] = MSM8X10_WCD_A_PIN_STATUS__POR,
+ [MSM8X10_WCD_A_HDRIVE_CTL] = MSM8X10_WCD_A_HDRIVE_CTL__POR,
+ [MSM8X10_WCD_A_HDRIVE_I2C_CTL] = MSM8X10_WCD_A_HDRIVE_I2C_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RST_CTL] = MSM8X10_WCD_A_CDC_RST_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TOP_CLK_CTL] = MSM8X10_WCD_A_CDC_TOP_CLK_CTL__POR,
+ [MSM8X10_WCD_A_CDC_ANA_CLK_CTL] = MSM8X10_WCD_A_CDC_ANA_CLK_CTL__POR,
+ [MSM8X10_WCD_A_CDC_DIG_CLK_CTL] = MSM8X10_WCD_A_CDC_DIG_CLK_CTL__POR,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL0] =
+ MSM8X10_WCD_A_PROCESS_MONITOR_CTL0__POR,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL1] =
+ MSM8X10_WCD_A_PROCESS_MONITOR_CTL1__POR,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL2] =
+ MSM8X10_WCD_A_PROCESS_MONITOR_CTL2__POR,
+ [MSM8X10_WCD_A_PROCESS_MONITOR_CTL3] =
+ MSM8X10_WCD_A_PROCESS_MONITOR_CTL3__POR,
+ [MSM8X10_WCD_A_QFUSE_CTL] = MSM8X10_WCD_A_QFUSE_CTL__POR,
+ [MSM8X10_WCD_A_QFUSE_STATUS] = MSM8X10_WCD_A_QFUSE_STATUS__POR,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT0] = MSM8X10_WCD_A_QFUSE_DATA_OUT0__POR,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT1] = MSM8X10_WCD_A_QFUSE_DATA_OUT1__POR,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT2] = MSM8X10_WCD_A_QFUSE_DATA_OUT2__POR,
+ [MSM8X10_WCD_A_QFUSE_DATA_OUT3] = MSM8X10_WCD_A_QFUSE_DATA_OUT3__POR,
+ [MSM8X10_WCD_A_CDC_CONN_TX1_CTL] = MSM8X10_WCD_A_CDC_CONN_TX1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_TX2_CTL] = MSM8X10_WCD_A_CDC_CONN_TX2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_CTL] = MSM8X10_WCD_A_CDC_CONN_RX1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_CTL] = MSM8X10_WCD_A_CDC_CONN_RX2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX3_CTL] = MSM8X10_WCD_A_CDC_CONN_RX3_CTL__POR,
+ [MSM8X10_WCD_A_DIGITAL_DEBUG_CTL] =
+ MSM8X10_WCD_A_DIGITAL_DEBUG_CTL__POR,
+ [MSM8X10_WCD_A_ANALOG_DEBUG_CTL] = MSM8X10_WCD_A_ANALOG_DEBUG_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_CTL] = MSM8X10_WCD_A_CDC_RX1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_CTL] = MSM8X10_WCD_A_CDC_RX2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_CTL] = MSM8X10_WCD_A_CDC_RX3_CTL__POR,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA0] = MSM8X10_WCD_A_DEM_BYPASS_DATA0__POR,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA1] = MSM8X10_WCD_A_DEM_BYPASS_DATA1__POR,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA2] = MSM8X10_WCD_A_DEM_BYPASS_DATA2__POR,
+ [MSM8X10_WCD_A_DEM_BYPASS_DATA3] = MSM8X10_WCD_A_DEM_BYPASS_DATA3__POR,
+ [MSM8X10_WCD_A_SPARE_0] = MSM8X10_WCD_A_SPARE_0__POR,
+ [MSM8X10_WCD_A_SPARE_1] = MSM8X10_WCD_A_SPARE_1__POR,
+ [MSM8X10_WCD_A_SPARE_2] = MSM8X10_WCD_A_SPARE_2__POR,
+ [MSM8X10_WCD_A_INTR_MODE] = MSM8X10_WCD_A_INTR_MODE__POR,
+ [MSM8X10_WCD_A_INTR_MASK0] = MSM8X10_WCD_A_INTR_MASK0__POR,
+ [MSM8X10_WCD_A_INTR_MASK1] = MSM8X10_WCD_A_INTR_MASK1__POR,
+ [MSM8X10_WCD_A_INTR_MASK2] = MSM8X10_WCD_A_INTR_MASK2__POR,
+ [MSM8X10_WCD_A_INTR_STATUS0] = MSM8X10_WCD_A_INTR_STATUS0__POR,
+ [MSM8X10_WCD_A_INTR_STATUS1] = MSM8X10_WCD_A_INTR_STATUS1__POR,
+ [MSM8X10_WCD_A_INTR_STATUS2] = MSM8X10_WCD_A_INTR_STATUS2__POR,
+ [MSM8X10_WCD_A_INTR_CLEAR0] = MSM8X10_WCD_A_INTR_CLEAR0__POR,
+ [MSM8X10_WCD_A_INTR_CLEAR1] = MSM8X10_WCD_A_INTR_CLEAR1__POR,
+ [MSM8X10_WCD_A_INTR_CLEAR2] = MSM8X10_WCD_A_INTR_CLEAR2__POR,
+ [MSM8X10_WCD_A_INTR_TEST0] = MSM8X10_WCD_A_INTR_TEST0__POR,
+ [MSM8X10_WCD_A_INTR_TEST1] = MSM8X10_WCD_A_INTR_TEST1__POR,
+ [MSM8X10_WCD_A_INTR_TEST2] = MSM8X10_WCD_A_INTR_TEST2__POR,
+ [MSM8X10_WCD_A_INTR_SET0] = MSM8X10_WCD_A_INTR_SET0__POR,
+ [MSM8X10_WCD_A_INTR_SET1] = MSM8X10_WCD_A_INTR_SET1__POR,
+ [MSM8X10_WCD_A_INTR_SET2] = MSM8X10_WCD_A_INTR_SET2__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_EN_CTL] = MSM8X10_WCD_A_CDC_MBHC_EN_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG] =
+ MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG] =
+ MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_B1_STATUS] =
+ MSM8X10_WCD_A_CDC_MBHC_B1_STATUS__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_B2_STATUS] =
+ MSM8X10_WCD_A_CDC_MBHC_B2_STATUS__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_B3_STATUS] =
+ MSM8X10_WCD_A_CDC_MBHC_B3_STATUS__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_B4_STATUS] =
+ MSM8X10_WCD_A_CDC_MBHC_B4_STATUS__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_B5_STATUS] =
+ MSM8X10_WCD_A_CDC_MBHC_B5_STATUS__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_B1_CTL] = MSM8X10_WCD_A_CDC_MBHC_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_B2_CTL] = MSM8X10_WCD_A_CDC_MBHC_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_CLK_CTL] = MSM8X10_WCD_A_CDC_MBHC_CLK_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_INT_CTL] = MSM8X10_WCD_A_CDC_MBHC_INT_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL] =
+ MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL__POR,
+ [MSM8X10_WCD_A_CDC_MBHC_SPARE] = MSM8X10_WCD_A_CDC_MBHC_SPARE__POR,
+ [MSM8X10_WCD_A_BIAS_REF_CTL] = MSM8X10_WCD_A_BIAS_REF_CTL__POR,
+ [MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL] =
+ MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL__POR,
+ [MSM8X10_WCD_A_BIAS_PRECHRG_CTL] = MSM8X10_WCD_A_BIAS_PRECHRG_CTL__POR,
+ [MSM8X10_WCD_A_BIAS_CURR_CTL_1] = MSM8X10_WCD_A_BIAS_CURR_CTL_1__POR,
+ [MSM8X10_WCD_A_BIAS_CURR_CTL_2] = MSM8X10_WCD_A_BIAS_CURR_CTL_2__POR,
+ [MSM8X10_WCD_A_BIAS_OSC_BG_CTL] = MSM8X10_WCD_A_BIAS_OSC_BG_CTL__POR,
+ [MSM8X10_WCD_A_MICB_CFILT_1_CTL] = MSM8X10_WCD_A_MICB_CFILT_1_CTL__POR,
+ [MSM8X10_WCD_A_MICB_CFILT_1_VAL] = MSM8X10_WCD_A_MICB_CFILT_1_VAL__POR,
+ [MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG] =
+ MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG__POR,
+ [MSM8X10_WCD_A_MICB_1_CTL] = MSM8X10_WCD_A_MICB_1_CTL__POR,
+ [MSM8X10_WCD_A_MICB_1_INT_RBIAS] = MSM8X10_WCD_A_MICB_1_INT_RBIAS__POR,
+ [MSM8X10_WCD_A_MICB_1_MBHC] = MSM8X10_WCD_A_MICB_1_MBHC__POR,
+ [MSM8X10_WCD_A_MBHC_INSERT_DETECT] =
+ MSM8X10_WCD_A_MBHC_INSERT_DETECT__POR,
+ [MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS] =
+ MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS__POR,
+ [MSM8X10_WCD_A_TX_COM_BIAS] = MSM8X10_WCD_A_TX_COM_BIAS__POR,
+ [MSM8X10_WCD_A_MBHC_SCALING_MUX_1] =
+ MSM8X10_WCD_A_MBHC_SCALING_MUX_1__POR,
+ [MSM8X10_WCD_A_MBHC_SCALING_MUX_2] =
+ MSM8X10_WCD_A_MBHC_SCALING_MUX_2__POR,
+ [MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL] =
+ MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL__POR,
+ [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1] =
+ MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1__POR,
+ [MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2] =
+ MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2__POR,
+ [MSM8X10_WCD_A_TX_1_EN] = MSM8X10_WCD_A_TX_1_EN__POR,
+ [MSM8X10_WCD_A_TX_2_EN] = MSM8X10_WCD_A_TX_2_EN__POR,
+ [MSM8X10_WCD_A_TX_1_2_ADC_CH1] = MSM8X10_WCD_A_TX_1_2_ADC_CH1__POR,
+ [MSM8X10_WCD_A_TX_1_2_ADC_CH2] = MSM8X10_WCD_A_TX_1_2_ADC_CH2__POR,
+ [MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL] =
+ MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL__POR,
+ [MSM8X10_WCD_A_TX_1_2_TEST_CTL] =
+ MSM8X10_WCD_A_TX_1_2_TEST_CTL__POR,
+ [MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN] =
+ MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN__POR,
+ [MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV] =
+ MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV__POR,
+ [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1] =
+ MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1__POR,
+ [MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2] =
+ MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2__POR,
+ [MSM8X10_WCD_A_TX_3_EN] = MSM8X10_WCD_A_TX_3_EN__POR,
+ [MSM8X10_WCD_A_TX_1_2_TEST_EN] = MSM8X10_WCD_A_TX_1_2_TEST_EN__POR,
+ [MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL] =
+ MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL__POR,
+ [MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR] =
+ MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR__POR,
+ [MSM8X10_WCD_A_CP_EN] = MSM8X10_WCD_A_CP_EN__POR,
+ [MSM8X10_WCD_A_CP_CLK] = MSM8X10_WCD_A_CP_CLK__POR,
+ [MSM8X10_WCD_A_CP_STATIC] = MSM8X10_WCD_A_CP_STATIC__POR,
+ [MSM8X10_WCD_A_CP_DCC1] = MSM8X10_WCD_A_CP_DCC1__POR,
+ [MSM8X10_WCD_A_CP_DCC3] = MSM8X10_WCD_A_CP_DCC3__POR,
+ [MSM8X10_WCD_A_CP_ATEST] = MSM8X10_WCD_A_CP_ATEST__POR,
+ [MSM8X10_WCD_A_CP_DTEST] = MSM8X10_WCD_A_CP_DTEST__POR,
+ [MSM8X10_WCD_A_RX_AUX_SW_CTL] = MSM8X10_WCD_A_RX_AUX_SW_CTL__POR,
+ [MSM8X10_WCD_A_RX_PA_AUX_IN_CONN] =
+ MSM8X10_WCD_A_RX_PA_AUX_IN_CONN__POR,
+ [MSM8X10_WCD_A_RX_COM_TIMER_DIV] = MSM8X10_WCD_A_RX_COM_TIMER_DIV__POR,
+ [MSM8X10_WCD_A_RX_COM_OCP_CTL] = MSM8X10_WCD_A_RX_COM_OCP_CTL__POR,
+ [MSM8X10_WCD_A_RX_COM_OCP_COUNT] = MSM8X10_WCD_A_RX_COM_OCP_COUNT__POR,
+ [MSM8X10_WCD_A_RX_COM_DAC_CTL] = MSM8X10_WCD_A_RX_COM_DAC_CTL__POR,
+ [MSM8X10_WCD_A_RX_COM_BIAS] = MSM8X10_WCD_A_RX_COM_BIAS__POR,
+ [MSM8X10_WCD_A_RX_HPH_AUTO_CHOP] = MSM8X10_WCD_A_RX_HPH_AUTO_CHOP__POR,
+ [MSM8X10_WCD_A_RX_HPH_CHOP_CTL] = MSM8X10_WCD_A_RX_HPH_CHOP_CTL__POR,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_PA] = MSM8X10_WCD_A_RX_HPH_BIAS_PA__POR,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_LDO] = MSM8X10_WCD_A_RX_HPH_BIAS_LDO__POR,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_CNP] = MSM8X10_WCD_A_RX_HPH_BIAS_CNP__POR,
+ [MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP] =
+ MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP__POR,
+ [MSM8X10_WCD_A_RX_HPH_OCP_CTL] = MSM8X10_WCD_A_RX_HPH_OCP_CTL__POR,
+ [MSM8X10_WCD_A_RX_HPH_CNP_EN] = MSM8X10_WCD_A_RX_HPH_CNP_EN__POR,
+ [MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL] =
+ MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL__POR,
+ [MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME] =
+ MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME__POR,
+ [MSM8X10_WCD_A_RX_HPH_L_GAIN] = MSM8X10_WCD_A_RX_HPH_L_GAIN__POR,
+ [MSM8X10_WCD_A_RX_HPH_L_TEST] = MSM8X10_WCD_A_RX_HPH_L_TEST__POR,
+ [MSM8X10_WCD_A_RX_HPH_L_PA_CTL] = MSM8X10_WCD_A_RX_HPH_L_PA_CTL__POR,
+ [MSM8X10_WCD_A_RX_HPH_L_DAC_CTL] =
+ MSM8X10_WCD_A_RX_HPH_L_DAC_CTL__POR,
+ [MSM8X10_WCD_A_RX_HPH_L_ATEST] = MSM8X10_WCD_A_RX_HPH_L_ATEST__POR,
+ [MSM8X10_WCD_A_RX_HPH_L_STATUS] = MSM8X10_WCD_A_RX_HPH_L_STATUS__POR,
+ [MSM8X10_WCD_A_RX_HPH_R_GAIN] = MSM8X10_WCD_A_RX_HPH_R_GAIN__POR,
+ [MSM8X10_WCD_A_RX_HPH_R_TEST] = MSM8X10_WCD_A_RX_HPH_R_TEST__POR,
+ [MSM8X10_WCD_A_RX_HPH_R_PA_CTL] = MSM8X10_WCD_A_RX_HPH_R_PA_CTL__POR,
+ [MSM8X10_WCD_A_RX_HPH_R_DAC_CTL] = MSM8X10_WCD_A_RX_HPH_R_DAC_CTL__POR,
+ [MSM8X10_WCD_A_RX_HPH_R_ATEST] = MSM8X10_WCD_A_RX_HPH_R_ATEST__POR,
+ [MSM8X10_WCD_A_RX_HPH_R_STATUS] = MSM8X10_WCD_A_RX_HPH_R_STATUS__POR,
+ [MSM8X10_WCD_A_RX_EAR_BIAS_PA] = MSM8X10_WCD_A_RX_EAR_BIAS_PA__POR,
+ [MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF] =
+ MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF__POR,
+ [MSM8X10_WCD_A_RX_EAR_EN] = MSM8X10_WCD_A_RX_EAR_EN__POR,
+ [MSM8X10_WCD_A_RX_EAR_GAIN] = MSM8X10_WCD_A_RX_EAR_GAIN__POR,
+ [MSM8X10_WCD_A_RX_EAR_CMBUFF] = MSM8X10_WCD_A_RX_EAR_CMBUFF__POR,
+ [MSM8X10_WCD_A_RX_EAR_ICTL] = MSM8X10_WCD_A_RX_EAR_ICTL__POR,
+ [MSM8X10_WCD_A_RX_EAR_CCOMP] = MSM8X10_WCD_A_RX_EAR_CCOMP__POR,
+ [MSM8X10_WCD_A_RX_EAR_VCM] = MSM8X10_WCD_A_RX_EAR_VCM__POR,
+ [MSM8X10_WCD_A_RX_EAR_CNP] = MSM8X10_WCD_A_RX_EAR_CNP__POR,
+ [MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST] =
+ MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST__POR,
+ [MSM8X10_WCD_A_RX_EAR_STATUS] = MSM8X10_WCD_A_RX_EAR_STATUS__POR,
+ [MSM8X10_WCD_A_RX_LINE_BIAS_PA] =
+ MSM8X10_WCD_A_RX_LINE_BIAS_PA__POR,
+ [MSM8X10_WCD_A_RX_BUCK_BIAS1] = MSM8X10_WCD_A_RX_BUCK_BIAS1__POR,
+ [MSM8X10_WCD_A_RX_BUCK_BIAS2] = MSM8X10_WCD_A_RX_BUCK_BIAS2__POR,
+ [MSM8X10_WCD_A_RX_LINE_COM] = MSM8X10_WCD_A_RX_LINE_COM__POR,
+ [MSM8X10_WCD_A_RX_LINE_CNP_EN] = MSM8X10_WCD_A_RX_LINE_CNP_EN__POR,
+ [MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL] =
+ MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL__POR,
+ [MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME] =
+ MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME__POR,
+ [MSM8X10_WCD_A_RX_LINE_1_GAIN] = MSM8X10_WCD_A_RX_LINE_1_GAIN__POR,
+ [MSM8X10_WCD_A_RX_LINE_1_TEST] = MSM8X10_WCD_A_RX_LINE_1_TEST__POR,
+ [MSM8X10_WCD_A_RX_LINE_1_DAC_CTL] =
+ MSM8X10_WCD_A_RX_LINE_1_DAC_CTL__POR,
+ [MSM8X10_WCD_A_RX_LINE_1_STATUS] =
+ MSM8X10_WCD_A_RX_LINE_1_STATUS__POR,
+ [MSM8X10_WCD_A_RX_LINE_CNP_DBG] = MSM8X10_WCD_A_RX_LINE_CNP_DBG__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_EN] = MSM8X10_WCD_A_SPKR_DRV_EN__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_GAIN] = MSM8X10_WCD_A_SPKR_DRV_GAIN__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_DAC_CTL] = MSM8X10_WCD_A_SPKR_DRV_DAC_CTL__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_OCP_CTL] = MSM8X10_WCD_A_SPKR_DRV_OCP_CTL__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_CLIP_DET] =
+ MSM8X10_WCD_A_SPKR_DRV_CLIP_DET__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_IEC] = MSM8X10_WCD_A_SPKR_DRV_IEC__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_DBG_DAC] = MSM8X10_WCD_A_SPKR_DRV_DBG_DAC__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_DBG_PA] = MSM8X10_WCD_A_SPKR_DRV_DBG_PA__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG] =
+ MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO] =
+ MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_BIAS_INT] =
+ MSM8X10_WCD_A_SPKR_DRV_BIAS_INT__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_BIAS_PA] = MSM8X10_WCD_A_SPKR_DRV_BIAS_PA__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP] =
+ MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP__POR,
+ [MSM8X10_WCD_A_SPKR_DRV_STATUS_PA] =
+ MSM8X10_WCD_A_SPKR_DRV_STATUS_PA__POR,
+ [MSM8X10_WCD_A_RC_OSC_FREQ] = MSM8X10_WCD_A_RC_OSC_FREQ__POR,
+ [MSM8X10_WCD_A_RC_OSC_TEST] = MSM8X10_WCD_A_RC_OSC_TEST__POR,
+ [MSM8X10_WCD_A_RC_OSC_STATUS] = MSM8X10_WCD_A_RC_OSC_STATUS__POR,
+ [MSM8X10_WCD_A_RC_OSC_TUNER] = MSM8X10_WCD_A_RC_OSC_TUNER__POR,
+ [MSM8X10_WCD_A_MBHC_HPH] = MSM8X10_WCD_A_MBHC_HPH__POR,
+ [MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_OTHR_CTL] = MSM8X10_WCD_A_CDC_CLK_OTHR_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_MCLK_CTL] = MSM8X10_WCD_A_CDC_CLK_MCLK_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_PDM_CTL] = MSM8X10_WCD_A_CDC_CLK_PDM_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLK_SD_CTL] = MSM8X10_WCD_A_CDC_CLK_SD_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_B1_CTL] = MSM8X10_WCD_A_CDC_RX1_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_B1_CTL] = MSM8X10_WCD_A_CDC_RX2_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_B1_CTL] = MSM8X10_WCD_A_CDC_RX3_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_B2_CTL] = MSM8X10_WCD_A_CDC_RX1_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_B2_CTL] = MSM8X10_WCD_A_CDC_RX2_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_B2_CTL] = MSM8X10_WCD_A_CDC_RX3_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_B3_CTL] = MSM8X10_WCD_A_CDC_RX1_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_B3_CTL] = MSM8X10_WCD_A_CDC_RX2_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_B3_CTL] = MSM8X10_WCD_A_CDC_RX3_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_B4_CTL] = MSM8X10_WCD_A_CDC_RX1_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_B4_CTL] = MSM8X10_WCD_A_CDC_RX2_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_B4_CTL] = MSM8X10_WCD_A_CDC_RX3_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_B5_CTL] = MSM8X10_WCD_A_CDC_RX1_B5_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_B5_CTL] = MSM8X10_WCD_A_CDC_RX2_B5_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_B5_CTL] = MSM8X10_WCD_A_CDC_RX3_B5_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_B6_CTL] = MSM8X10_WCD_A_CDC_RX1_B6_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_B6_CTL] = MSM8X10_WCD_A_CDC_RX2_B6_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_B6_CTL] = MSM8X10_WCD_A_CDC_RX3_B6_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL] =
+ MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL] =
+ MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL] =
+ MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL] =
+ MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL] =
+ MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL] =
+ MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL] =
+ MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL] =
+ MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL] =
+ MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL] =
+ MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG] =
+ MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG] =
+ MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG__POR,
+ [MSM8X10_WCD_A_CDC_CLSG_CTL] = MSM8X10_WCD_A_CDC_CLSG_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER] =
+ MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER__POR,
+ [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER] =
+ MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER__POR,
+ [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN] =
+ MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN__POR,
+ [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN] =
+ MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN__POR,
+ [MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG] =
+ MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG__POR,
+ [MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG] =
+ MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG__POR,
+ [MSM8X10_WCD_A_CDC_TX1_MUX_CTL] =
+ MSM8X10_WCD_A_CDC_TX1_MUX_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TX2_MUX_CTL] =
+ MSM8X10_WCD_A_CDC_TX2_MUX_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL] =
+ MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL] =
+ MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TX1_DMIC_CTL] =
+ MSM8X10_WCD_A_CDC_TX1_DMIC_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TX2_DMIC_CTL] =
+ MSM8X10_WCD_A_CDC_TX2_DMIC_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_CTL] = MSM8X10_WCD_A_CDC_IIR1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_CTL] = MSM8X10_WCD_A_CDC_IIR2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL] =
+ MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL] =
+ MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL__POR,
+ [MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL] =
+ MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE] =
+ MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE__POR,
+ [MSM8X10_WCD_A_CDC_TOP_CTL] = MSM8X10_WCD_A_CDC_TOP_CTL__POR,
+ [MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL] =
+ MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL] =
+ MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_DEBUG_B1_CTL] =
+ MSM8X10_WCD_A_CDC_DEBUG_B1_CTL__POR,
+ [MSM8X10_WCD_A_CDC_DEBUG_B2_CTL] =
+ MSM8X10_WCD_A_CDC_DEBUG_B2_CTL__POR,
+ [MSM8X10_WCD_A_CDC_DEBUG_B3_CTL] =
+ MSM8X10_WCD_A_CDC_DEBUG_B3_CTL__POR,
+};
diff --git a/sound/soc/codecs/msm8x10-wcd.c b/sound/soc/codecs/msm8x10-wcd.c
new file mode 100644
index 0000000..4bcea07
--- /dev/null
+++ b/sound/soc/codecs/msm8x10-wcd.c
@@ -0,0 +1,2427 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/firmware.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+#include <linux/debugfs.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9xxx/pdata.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+#include "msm8x10-wcd.h"
+#include "wcd9xxx-resmgr.h"
+#include "msm8x10_wcd_registers.h"
+
+#define MSM8X10_WCD_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
+#define MSM8X10_WCD_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
+
+#define NUM_DECIMATORS 2
+#define NUM_INTERPOLATORS 3
+#define BITS_PER_REG 8
+#define MSM8X10_WCD_TX_PORT_NUMBER 4
+
+#define MSM8X10_WCD_I2S_MASTER_MODE_MASK 0x08
+#define MSM8X10_DINO_CODEC_BASE_ADDR 0xFE043000
+
+#define MAX_MSM8X10_WCD_DEVICE 2
+#define CODEC_DT_MAX_PROP_SIZE 40
+#define MSM8X10_WCD_I2C_GSBI_SLAVE_ID "2-000d"
+
+enum {
+ MSM8X10_WCD_I2C_TOP_LEVEL = 0,
+ MSM8X10_WCD_I2C_ANALOG,
+ MSM8X10_WCD_I2C_DIGITAL_1,
+ MSM8X10_WCD_I2C_DIGITAL_2,
+};
+
+enum {
+ AIF1_PB = 0,
+ AIF1_CAP,
+ NUM_CODEC_DAIS,
+};
+
+enum {
+ RX_MIX1_INP_SEL_ZERO = 0,
+ RX_MIX1_INP_SEL_IIR1,
+ RX_MIX1_INP_SEL_IIR2,
+ RX_MIX1_INP_SEL_RX1,
+ RX_MIX1_INP_SEL_RX2,
+ RX_MIX1_INP_SEL_RX3,
+};
+
+static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
+static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
+static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
+static struct snd_soc_dai_driver msm8x10_wcd_i2s_dai[];
+static const DECLARE_TLV_DB_SCALE(aux_pga_gain, 0, 2, 0);
+
+/* Codec supports 2 IIR filters */
+enum {
+ IIR1 = 0,
+ IIR2,
+ IIR_MAX,
+};
+/* Codec supports 5 bands */
+enum {
+ BAND1 = 0,
+ BAND2,
+ BAND3,
+ BAND4,
+ BAND5,
+ BAND_MAX,
+};
+
+struct hpf_work {
+ struct msm8x10_wcd_priv *msm8x10_wcd;
+ u32 decimator;
+ u8 tx_hpf_cut_of_freq;
+ struct delayed_work dwork;
+};
+
+static struct hpf_work tx_hpf_work[NUM_DECIMATORS];
+
+struct msm8x10_wcd_priv {
+ struct snd_soc_codec *codec;
+ u32 adc_count;
+ u32 rx_bias_count;
+ s32 dmic_1_2_clk_cnt;
+
+ /* resmgr module */
+ struct wcd9xxx_resmgr resmgr;
+ /* mbhc module */
+ struct wcd9xxx_mbhc mbhc;
+};
+
+
+static unsigned short rx_digital_gain_reg[] = {
+ MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
+ MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
+ MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
+};
+
+static unsigned short tx_digital_gain_reg[] = {
+ MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN,
+ MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN,
+};
+
+struct msm8x10_wcd_i2c {
+ struct i2c_client *client;
+ struct i2c_msg xfer_msg[2];
+ struct mutex xfer_lock;
+ int mod_id;
+};
+
+static char *msm8x10_wcd_supplies[] = {
+ "cdc-vdd-mic-bias", "cdc-vdda-h", "cdc-vdd-1p2", "cdc-vdd-px",
+ "cdc-vdda-cp",
+};
+
+static int msm8x10_wcd_dt_parse_vreg_info(struct device *dev,
+ struct msm8x10_wcd_regulator *vreg, const char *vreg_name);
+static int msm8x10_wcd_dt_parse_micbias_info(struct device *dev,
+ struct msm8x10_wcd_micbias_setting *micbias);
+static struct msm8x10_wcd_pdata *msm8x10_wcd_populate_dt_pdata(
+ struct device *dev);
+
+struct msm8x10_wcd_i2c msm8x10_wcd_modules[MAX_MSM8X10_WCD_DEVICE];
+
+
+static int get_i2c_msm8x10_wcd_device_info(u16 reg,
+ struct msm8x10_wcd_i2c **msm8x10_wcd)
+{
+ int rtn = 0;
+ int value = ((reg & 0x0f00) >> 8) & 0x000f;
+ pr_debug("%s: reg(0x%x) value(%d)\n", __func__, reg, value);
+ switch (value) {
+ case 0:
+ case 1:
+ *msm8x10_wcd = &msm8x10_wcd_modules[value];
+ break;
+ default:
+ rtn = -EINVAL;
+ break;
+ }
+ return rtn;
+}
+
+static int msm8x10_wcd_abh_write_device(u16 reg, u8 *value, u32 bytes)
+{
+ u32 temp = ((u32)(*value)) & 0x000000FF;
+ u32 offset = (((u32)(reg)) ^ 0x00000400) & 0x00000FFF;
+ iowrite32(temp, ioremap(MSM8X10_DINO_CODEC_BASE_ADDR + offset, 4));
+ return 0;
+}
+
+static int msm8x10_wcd_abh_read_device(u16 reg, u32 bytes, u8 *value)
+{
+ u32 offset = (((u32)(reg)) ^ 0x00000400) & 0x00000FFF;
+ *value = (u8)ioread32(ioremap(MSM8X10_DINO_CODEC_BASE_ADDR +
+ offset, 4));
+ return 0;
+}
+
+static int msm8x10_wcd_i2c_write_device(u16 reg, u8 *value, u32 bytes)
+{
+
+ struct i2c_msg *msg;
+ int ret;
+ u8 reg_addr = 0;
+ u8 data[bytes + 1];
+ struct msm8x10_wcd_i2c *msm8x10_wcd;
+
+ ret = get_i2c_msm8x10_wcd_device_info(reg, &msm8x10_wcd);
+ if (!ret) {
+ pr_err("%s: Invalid register address\n", __func__);
+ return ret;
+ }
+
+ if (msm8x10_wcd == NULL || msm8x10_wcd->client == NULL) {
+ pr_err("%s: Failed to get device info\n", __func__);
+ return -ENODEV;
+ }
+ reg_addr = (u8)reg;
+ msg = &msm8x10_wcd->xfer_msg[0];
+ msg->addr = msm8x10_wcd->client->addr;
+ msg->len = bytes + 1;
+ msg->flags = 0;
+ data[0] = reg;
+ data[1] = *value;
+ msg->buf = data;
+ ret = i2c_transfer(msm8x10_wcd->client->adapter,
+ msm8x10_wcd->xfer_msg, 1);
+ /* Try again if the write fails */
+ if (ret != 1) {
+ ret = i2c_transfer(msm8x10_wcd->client->adapter,
+ msm8x10_wcd->xfer_msg, 1);
+ if (ret != 1) {
+ pr_err("failed to write the device\n");
+ return ret;
+ }
+ }
+ pr_debug("write sucess register = %x val = %x\n", reg, data[1]);
+ return 0;
+}
+
+
+int msm8x10_wcd_i2c_read_device(u32 reg, u32 bytes, u8 *dest)
+{
+ struct i2c_msg *msg;
+ int ret = 0;
+ u8 reg_addr = 0;
+ struct msm8x10_wcd_i2c *msm8x10_wcd;
+ u8 i = 0;
+
+ ret = get_i2c_msm8x10_wcd_device_info(reg, &msm8x10_wcd);
+ if (!ret) {
+ pr_err("%s: Invalid register address\n", __func__);
+ return ret;
+ }
+
+ if (msm8x10_wcd == NULL || msm8x10_wcd->client == NULL) {
+ pr_err("%s: Failed to get device info\n", __func__);
+ return -ENODEV;
+ }
+
+ for (i = 0; i < bytes; i++) {
+ reg_addr = (u8)reg++;
+ msg = &msm8x10_wcd->xfer_msg[0];
+ msg->addr = msm8x10_wcd->client->addr;
+ msg->len = 1;
+ msg->flags = 0;
+ msg->buf = ®_addr;
+
+ msg = &msm8x10_wcd->xfer_msg[1];
+ msg->addr = msm8x10_wcd->client->addr;
+ msg->len = 1;
+ msg->flags = I2C_M_RD;
+ msg->buf = dest++;
+ ret = i2c_transfer(msm8x10_wcd->client->adapter,
+ msm8x10_wcd->xfer_msg, 2);
+
+ /* Try again if read fails first time */
+ if (ret != 2) {
+ ret = i2c_transfer(msm8x10_wcd->client->adapter,
+ msm8x10_wcd->xfer_msg, 2);
+ if (ret != 2) {
+ pr_err("failed to read msm8x10_wcd register\n");
+ return ret;
+ }
+ }
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_reg_read(struct msm8x10_wcd *msm8x10_wcd, u16 reg)
+{
+ u8 val;
+ int ret = -EINVAL;
+
+ /* check if use I2C interface for Helicon or AHB for Dino */
+ mutex_lock(&msm8x10_wcd->io_lock);
+ if (MSM8X10_WCD_IS_HELICON_REG(reg))
+ ret = msm8x10_wcd_i2c_read_device(reg, 1, &val);
+ else if (MSM8X10_WCD_IS_DINO_REG(reg))
+ ret = msm8x10_wcd_abh_read_device(reg, 1, &val);
+ mutex_unlock(&msm8x10_wcd->io_lock);
+
+ if (ret < 0)
+ return ret;
+ else
+ return val;
+}
+
+
+static int msm8x10_wcd_reg_write(struct msm8x10_wcd *msm8x10_wcd, u16 reg,
+ u8 val)
+{
+ int ret = -EINVAL;
+
+ /* check if use I2C interface for Helicon or AHB for Dino */
+ mutex_lock(&msm8x10_wcd->io_lock);
+ if (MSM8X10_WCD_IS_HELICON_REG(reg))
+ ret = msm8x10_wcd_i2c_write_device(reg, &val, 1);
+ else if (MSM8X10_WCD_IS_DINO_REG(reg))
+ ret = msm8x10_wcd_abh_write_device(reg, &val, 1);
+ mutex_unlock(&msm8x10_wcd->io_lock);
+
+ return ret;
+}
+
+static bool msm8x10_wcd_is_digital_gain_register(unsigned int reg)
+{
+ bool rtn = false;
+ switch (reg) {
+ case MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL:
+ case MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL:
+ case MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL:
+ case MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN:
+ case MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN:
+ rtn = true;
+ break;
+ default:
+ break;
+ }
+ return rtn;
+}
+
+static int msm8x10_wcd_volatile(struct snd_soc_codec *ssc, unsigned int reg)
+{
+ /*
+ * Registers lower than 0x100 are top level registers which can be
+ * written by the Taiko core driver.
+ */
+
+ if ((reg >= MSM8X10_WCD_A_CDC_MBHC_EN_CTL) || (reg < 0x100))
+ return 1;
+
+ /* IIR Coeff registers are not cacheable */
+ if ((reg >= MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL) &&
+ (reg <= MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL))
+ return 1;
+
+ /*
+ * Digital gain register is not cacheable so we have to write
+ * the setting even it is the same
+ */
+ if (msm8x10_wcd_is_digital_gain_register(reg))
+ return 1;
+
+ /* HPH status registers */
+ if (reg == MSM8X10_WCD_A_RX_HPH_L_STATUS ||
+ reg == MSM8X10_WCD_A_RX_HPH_R_STATUS)
+ return 1;
+
+ if (reg == MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS)
+ return 1;
+
+ return 0;
+}
+
+static int msm8x10_wcd_readable(struct snd_soc_codec *ssc, unsigned int reg)
+{
+ return msm8x10_wcd_reg_readable[reg];
+}
+
+static int msm8x10_wcd_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
+{
+ int ret;
+
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > MSM8X10_WCD_MAX_REGISTER);
+
+ if (!msm8x10_wcd_volatile(codec, reg)) {
+ ret = snd_soc_cache_write(codec, reg, value);
+ if (ret != 0)
+ dev_err(codec->dev, "Cache write to %x failed: %d\n",
+ reg, ret);
+ }
+
+ return msm8x10_wcd_reg_write(codec->control_data, reg, value);
+}
+
+static unsigned int msm8x10_wcd_read(struct snd_soc_codec *codec,
+ unsigned int reg)
+{
+ unsigned int val;
+ int ret;
+
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > MSM8X10_WCD_MAX_REGISTER);
+
+ if (!msm8x10_wcd_volatile(codec, reg) &&
+ msm8x10_wcd_readable(codec, reg) &&
+ reg < codec->driver->reg_cache_size) {
+ ret = snd_soc_cache_read(codec, reg, &val);
+ if (ret >= 0) {
+ return val;
+ } else
+ dev_err(codec->dev, "Cache read from %x failed: %d\n",
+ reg, ret);
+ }
+
+ val = msm8x10_wcd_reg_read(codec->control_data, reg);
+ return val;
+}
+
+
+static int msm8x10_wcd_dt_parse_vreg_info(struct device *dev,
+ struct msm8x10_wcd_regulator *vreg, const char *vreg_name)
+{
+ int len, ret = 0;
+ const __be32 *prop;
+ char prop_name[CODEC_DT_MAX_PROP_SIZE];
+ struct device_node *regnode = NULL;
+ u32 prop_val;
+
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply",
+ vreg_name);
+ regnode = of_parse_phandle(dev->of_node, prop_name, 0);
+
+ if (!regnode) {
+ dev_err(dev, "Looking up %s property in node %s failed",
+ prop_name, dev->of_node->full_name);
+ return -ENODEV;
+ }
+ vreg->name = vreg_name;
+
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
+ "qcom,%s-voltage", vreg_name);
+ prop = of_get_property(dev->of_node, prop_name, &len);
+
+ if (!prop || (len != (2 * sizeof(__be32)))) {
+ dev_err(dev, "%s %s property\n",
+ prop ? "invalid format" : "no", prop_name);
+ return -ENODEV;
+ } else {
+ vreg->min_uV = be32_to_cpup(&prop[0]);
+ vreg->max_uV = be32_to_cpup(&prop[1]);
+ }
+
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
+ "qcom,%s-current", vreg_name);
+
+ ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
+ if (ret) {
+ dev_err(dev, "Looking up %s property in node %s failed",
+ prop_name, dev->of_node->full_name);
+ return -ENODEV;
+ }
+ vreg->optimum_uA = prop_val;
+
+ dev_info(dev, "%s: vol=[%d %d]uV, curr=[%d]uA\n", vreg->name,
+ vreg->min_uV, vreg->max_uV, vreg->optimum_uA);
+ return 0;
+}
+
+static int msm8x10_wcd_dt_parse_micbias_info(struct device *dev,
+ struct msm8x10_wcd_micbias_setting *micbias)
+{
+ int ret = 0;
+ char prop_name[CODEC_DT_MAX_PROP_SIZE];
+ u32 prop_val;
+
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
+ "qcom,cdc-micbias-ldoh-v");
+ ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
+ if (ret) {
+ dev_err(dev, "Looking up %s property in node %s failed",
+ prop_name, dev->of_node->full_name);
+ return -ENODEV;
+ }
+ micbias->ldoh_v = (u8)prop_val;
+
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
+ "qcom,cdc-micbias-cfilt1-mv");
+ ret = of_property_read_u32(dev->of_node, prop_name,
+ &micbias->cfilt1_mv);
+ if (ret) {
+ dev_err(dev, "Looking up %s property in node %s failed",
+ prop_name, dev->of_node->full_name);
+ return -ENODEV;
+ }
+
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
+ "qcom,cdc-micbias1-cfilt-sel");
+ ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
+ if (ret) {
+ dev_err(dev, "Looking up %s property in node %s failed",
+ prop_name, dev->of_node->full_name);
+ return -ENODEV;
+ }
+ micbias->bias1_cfilt_sel = (u8)prop_val;
+
+ /* micbias external cap */
+ micbias->bias1_cap_mode =
+ (of_property_read_bool(dev->of_node, "qcom,cdc-micbias1-ext-cap") ?
+ MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
+
+ dev_dbg(dev, "ldoh_v %u cfilt1_mv %u\n",
+ (u32)micbias->ldoh_v, (u32)micbias->cfilt1_mv);
+ dev_dbg(dev, "bias1_cfilt_sel %u\n", (u32)micbias->bias1_cfilt_sel);
+ dev_dbg(dev, "bias1_ext_cap %d\n", micbias->bias1_cap_mode);
+
+ return 0;
+}
+
+static struct msm8x10_wcd_pdata *msm8x10_wcd_populate_dt_pdata(
+ struct device *dev)
+{
+ struct msm8x10_wcd_pdata *pdata;
+ int ret, i;
+ char **codec_supplies;
+ u32 num_of_supplies = 0;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ dev_err(dev, "could not allocate memory for platform data\n");
+ return NULL;
+ }
+ if ((!strcmp(dev_name(dev), MSM8X10_WCD_I2C_GSBI_SLAVE_ID))) {
+ codec_supplies = msm8x10_wcd_supplies;
+ num_of_supplies = ARRAY_SIZE(msm8x10_wcd_supplies);
+ } else {
+ dev_err(dev, "%s unsupported device %s\n",
+ __func__, dev_name(dev));
+ goto err;
+ }
+
+ if (num_of_supplies > ARRAY_SIZE(pdata->regulator)) {
+ dev_err(dev, "%s: Num of supplies %u > max supported %u\n",
+ __func__, num_of_supplies, ARRAY_SIZE(pdata->regulator));
+
+ goto err;
+ }
+
+ for (i = 0; i < num_of_supplies; i++) {
+ ret = msm8x10_wcd_dt_parse_vreg_info(dev, &pdata->regulator[i],
+ codec_supplies[i]);
+ if (ret)
+ goto err;
+ }
+
+ ret = msm8x10_wcd_dt_parse_micbias_info(dev, &pdata->micbias);
+ if (ret)
+ goto err;
+
+ pdata->reset_gpio = of_get_named_gpio(dev->of_node,
+ "qcom,cdc-reset-gpio", 0);
+ if (pdata->reset_gpio < 0) {
+ dev_err(dev, "Looking up %s property in node %s failed %d\n",
+ "qcom, cdc-reset-gpio", dev->of_node->full_name,
+ pdata->reset_gpio);
+ goto err;
+ }
+ dev_dbg(dev, "%s: reset gpio %d", __func__, pdata->reset_gpio);
+ return pdata;
+err:
+ devm_kfree(dev, pdata);
+ return NULL;
+}
+
+static int msm8x10_wcd_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ pr_debug("%s %d\n", __func__, event);
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ /* Enable charge pump clock*/
+ snd_soc_update_bits(codec, MSM8X10_WCD_A_CDC_CLK_OTHR_CTL,
+ 0x01, 0x01);
+ snd_soc_update_bits(codec, MSM8X10_WCD_A_CDC_CLSG_CTL,
+ 0x08, 0x08);
+ usleep_range(200, 300);
+ snd_soc_update_bits(codec, MSM8X10_WCD_A_CP_STATIC,
+ 0x10, 0x00);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL,
+ 0x01, 0x01);
+ usleep_range(20, 100);
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CP_STATIC, 0x08, 0x08);
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CP_STATIC, 0x10, 0x10);
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CDC_CLSG_CTL, 0x08, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CDC_CLK_OTHR_CTL, 0x01,
+ 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CP_STATIC, 0x08, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_pa_gain_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ u8 ear_pa_gain;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ear_pa_gain = snd_soc_read(codec, MSM8X10_WCD_A_RX_EAR_GAIN);
+
+ ear_pa_gain = ear_pa_gain >> 5;
+
+ if (ear_pa_gain == 0x00) {
+ ucontrol->value.integer.value[0] = 0;
+ } else if (ear_pa_gain == 0x04) {
+ ucontrol->value.integer.value[0] = 1;
+ } else {
+ pr_err("%s: ERROR: Unsupported Ear Gain = 0x%x\n",
+ __func__, ear_pa_gain);
+ return -EINVAL;
+ }
+
+ pr_debug("%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain);
+
+ return 0;
+}
+
+static int msm8x10_wcd_pa_gain_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ u8 ear_pa_gain;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ pr_debug("%s: ucontrol->value.integer.value[0] = %ld\n",
+ __func__, ucontrol->value.integer.value[0]);
+
+ switch (ucontrol->value.integer.value[0]) {
+ case 0:
+ ear_pa_gain = 0x00;
+ break;
+ case 1:
+ ear_pa_gain = 0x80;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ snd_soc_update_bits(codec, MSM8X10_WCD_A_RX_EAR_GAIN,
+ 0xE0, ear_pa_gain);
+ return 0;
+}
+
+static int msm8x10_wcd_get_iir_enable_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_read(codec,
+ (MSM8X10_WCD_A_CDC_IIR1_CTL + 64 * iir_idx)) &
+ (1 << band_idx);
+
+ pr_debug("%s: IIR #%d band #%d enable %d\n", __func__,
+ iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[0]);
+ return 0;
+}
+
+static int msm8x10_wcd_put_iir_enable_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+ int value = ucontrol->value.integer.value[0];
+
+ /* Mask first 5 bits, 6-8 are reserved */
+ snd_soc_update_bits(codec, (MSM8X10_WCD_A_CDC_IIR1_CTL + 64 * iir_idx),
+ (1 << band_idx), (value << band_idx));
+
+ pr_debug("%s: IIR #%d band #%d enable %d\n", __func__,
+ iir_idx, band_idx, value);
+ return 0;
+}
+static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec,
+ int iir_idx, int band_idx,
+ int coeff_idx)
+{
+ /* Address does not automatically update if reading */
+ snd_soc_write(codec,
+ (MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
+ (band_idx * BAND_MAX + coeff_idx) & 0x1F);
+
+ /* Mask bits top 2 bits since they are reserved */
+ return ((snd_soc_read(codec,
+ (MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 24)) &
+ 0x3FFFFFFF;
+}
+
+static int msm8x10_wcd_get_iir_band_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ ucontrol->value.integer.value[0] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 0);
+ ucontrol->value.integer.value[1] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 1);
+ ucontrol->value.integer.value[2] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 2);
+ ucontrol->value.integer.value[3] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 3);
+ ucontrol->value.integer.value[4] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 4);
+
+ pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
+ "%s: IIR #%d band #%d b1 = 0x%x\n"
+ "%s: IIR #%d band #%d b2 = 0x%x\n"
+ "%s: IIR #%d band #%d a1 = 0x%x\n"
+ "%s: IIR #%d band #%d a2 = 0x%x\n",
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[0],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[1],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[2],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[3],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[4]);
+ return 0;
+}
+
+static void set_iir_band_coeff(struct snd_soc_codec *codec,
+ int iir_idx, int band_idx,
+ int coeff_idx, uint32_t value)
+{
+ /* Mask top 3 bits, 6-8 are reserved */
+ /* Update address manually each time */
+ snd_soc_write(codec,
+ (MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
+ (band_idx * BAND_MAX + coeff_idx) & 0x1F);
+
+ /* Mask top 2 bits, 7-8 are reserved */
+ snd_soc_write(codec,
+ (MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
+ (value >> 24) & 0x3F);
+
+}
+
+static int msm8x10_wcd_put_iir_band_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ set_iir_band_coeff(codec, iir_idx, band_idx, 0,
+ ucontrol->value.integer.value[0]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 1,
+ ucontrol->value.integer.value[1]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 2,
+ ucontrol->value.integer.value[2]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 3,
+ ucontrol->value.integer.value[3]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 4,
+ ucontrol->value.integer.value[4]);
+
+ pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
+ "%s: IIR #%d band #%d b1 = 0x%x\n"
+ "%s: IIR #%d band #%d b2 = 0x%x\n"
+ "%s: IIR #%d band #%d a1 = 0x%x\n"
+ "%s: IIR #%d band #%d a2 = 0x%x\n",
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 0),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 1),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 2),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 3),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 4));
+ return 0;
+}
+
+static const char * const msm8x10_wcd_ear_pa_gain_text[] = {
+ "POS_6_DB", "POS_2_DB"};
+static const struct soc_enum msm8x10_wcd_ear_pa_gain_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, msm8x10_wcd_ear_pa_gain_text),
+};
+
+/*cut of frequency for high pass filter*/
+static const char * const cf_text[] = {
+ "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
+};
+
+static const struct soc_enum cf_dec1_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec2_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_rxmix1_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_RX1_B4_CTL, 0, 3, cf_text);
+
+static const struct soc_enum cf_rxmix2_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_RX2_B4_CTL, 0, 3, cf_text);
+
+static const struct soc_enum cf_rxmix3_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_RX3_B4_CTL, 0, 3, cf_text);
+
+static const struct snd_kcontrol_new msm8x10_wcd_snd_controls[] = {
+
+ SOC_ENUM_EXT("EAR PA Gain", msm8x10_wcd_ear_pa_gain_enum[0],
+ msm8x10_wcd_pa_gain_get, msm8x10_wcd_pa_gain_put),
+
+ SOC_SINGLE_TLV("LINEOUT1 Volume", MSM8X10_WCD_A_RX_LINE_1_GAIN,
+ 0, 12, 1, line_gain),
+
+ SOC_SINGLE_TLV("HPHL Volume", MSM8X10_WCD_A_RX_HPH_L_GAIN,
+ 0, 12, 1, line_gain),
+ SOC_SINGLE_TLV("HPHR Volume", MSM8X10_WCD_A_RX_HPH_R_GAIN,
+ 0, 12, 1, line_gain),
+
+ SOC_SINGLE_S8_TLV("RX1 Digital Volume",
+ MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX2 Digital Volume",
+ MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX3 Digital Volume",
+ MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+
+ SOC_SINGLE_S8_TLV("DEC1 Volume",
+ MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("DEC2 Volume",
+ MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN,
+ -84, 40, digital_gain),
+
+ SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP4 Volume",
+ MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL,
+ -84, 40, digital_gain),
+
+ SOC_SINGLE("MICBIAS1 CAPLESS Switch",
+ MSM8X10_WCD_A_MICB_1_CTL, 4, 1, 1),
+
+ SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
+ SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
+
+ SOC_SINGLE("TX1 HPF Switch", MSM8X10_WCD_A_CDC_TX1_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX2 HPF Switch", MSM8X10_WCD_A_CDC_TX2_MUX_CTL, 3, 1, 0),
+
+ SOC_SINGLE("RX1 HPF Switch", MSM8X10_WCD_A_CDC_RX1_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX2 HPF Switch", MSM8X10_WCD_A_CDC_RX2_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX3 HPF Switch", MSM8X10_WCD_A_CDC_RX3_B5_CTL, 2, 1, 0),
+
+ SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
+ SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
+ SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
+
+ SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0,
+ msm8x10_wcd_get_iir_enable_audio_mixer,
+ msm8x10_wcd_put_iir_enable_audio_mixer),
+
+ SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5,
+ msm8x10_wcd_get_iir_band_audio_mixer,
+ msm8x10_wcd_put_iir_band_audio_mixer),
+
+};
+
+static const char * const rx_mix1_text[] = {
+ "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
+};
+
+static const char * const rx_mix2_text[] = {
+ "ZERO", "IIR1", "IIR2"
+};
+
+static const char * const dec_mux_text[] = {
+ "ZERO", "ADC1", "ADC2", "DMIC1", "DMIC2"
+};
+
+
+static const char * const anc_mux_text[] = {
+ "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC_MB",
+ "RSVD_1", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", "DMIC6"
+};
+
+static const char * const anc1_fb_mux_text[] = {
+ "ZERO", "EAR_HPH_L", "EAR_LINE_1",
+};
+
+static const char * const iir1_inp1_text[] = {
+ "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
+};
+
+static const struct soc_enum rx_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp3_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text);
+
+static const struct soc_enum rx3_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text);
+
+static const struct soc_enum rx3_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text);
+
+static const struct soc_enum rx1_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL, 0, 3, rx_mix2_text);
+
+static const struct soc_enum rx2_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL, 0, 3, rx_mix2_text);
+
+static const struct soc_enum dec1_mux_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL, 0, 5, dec_mux_text);
+
+static const struct soc_enum dec2_mux_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL, 3, 5, dec_mux_text);
+
+static const struct soc_enum iir1_inp1_mux_enum =
+ SOC_ENUM_SINGLE(MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL, 0, 6,
+ iir1_inp1_text);
+
+static const struct snd_kcontrol_new rx_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp3_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx1_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
+
+static int msm8x10_wcd_put_dec_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *w = wlist->widgets[0];
+ struct snd_soc_codec *codec = w->codec;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int dec_mux, decimator;
+ char *dec_name = NULL;
+ char *widget_name = NULL;
+ char *temp;
+ u16 tx_mux_ctl_reg;
+ u8 adc_dmic_sel = 0x0;
+ int ret = 0;
+
+ if (ucontrol->value.enumerated.item[0] > e->max - 1)
+ return -EINVAL;
+
+ dec_mux = ucontrol->value.enumerated.item[0];
+
+ widget_name = kstrndup(w->name, 15, GFP_KERNEL);
+ if (!widget_name)
+ return -ENOMEM;
+ temp = widget_name;
+
+ dec_name = strsep(&widget_name, " ");
+ widget_name = temp;
+ if (!dec_name) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = kstrtouint(strpbrk(dec_name, "12"), 10, &decimator);
+ if (ret < 0) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n"
+ , __func__, w->name, decimator, dec_mux);
+
+ switch (decimator) {
+ case 1:
+ case 2:
+ if (dec_mux == 1)
+ adc_dmic_sel = 0x1;
+ else
+ adc_dmic_sel = 0x0;
+ break;
+ default:
+ pr_err("%s: Invalid Decimator = %u\n", __func__, decimator);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ tx_mux_ctl_reg = MSM8X10_WCD_A_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
+
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel);
+
+ ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
+
+out:
+ kfree(widget_name);
+ return ret;
+}
+
+#define MSM8X10_WCD_DEC_ENUM(xname, xenum) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_enum_double, \
+ .get = snd_soc_dapm_get_enum_double, \
+ .put = msm8x10_wcd_put_dec_enum, \
+ .private_value = (unsigned long)&xenum }
+
+static const struct snd_kcontrol_new dec1_mux =
+ MSM8X10_WCD_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum);
+
+static const struct snd_kcontrol_new dec2_mux =
+ MSM8X10_WCD_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum);
+
+static const struct snd_kcontrol_new iir1_inp1_mux =
+ SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
+
+static const struct snd_kcontrol_new dac1_switch[] = {
+ SOC_DAPM_SINGLE("Switch", MSM8X10_WCD_A_RX_EAR_EN, 5, 1, 0)
+};
+static const struct snd_kcontrol_new hphl_switch[] = {
+ SOC_DAPM_SINGLE("Switch", MSM8X10_WCD_A_RX_HPH_L_DAC_CTL, 6, 1, 0)
+};
+
+/* virtual port entries */
+static int slim_tx_mixer_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+
+ ucontrol->value.integer.value[0] = widget->value;
+ return 0;
+}
+
+static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return 0;
+}
+
+static int slim_rx_mux_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+
+ ucontrol->value.enumerated.item[0] = widget->value;
+ return 0;
+}
+
+static int slim_rx_mux_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return 0;
+}
+
+
+static const char *const slim_rx_mux_text[] = {
+ "ZERO", "AIF1_PB"
+};
+
+static const struct soc_enum slim_rx_mux_enum =
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
+
+static const struct snd_kcontrol_new slim_rx_mux[MSM8X10_WCD_RX_MAX] = {
+ SOC_DAPM_ENUM_EXT("I2S RX1 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("I2S RX2 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("I2S RX3 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+};
+
+static const struct snd_kcontrol_new aif_cap_mixer[] = {
+ SOC_SINGLE_EXT("I2S TX1", SND_SOC_NOPM, MSM8X10_WCD_TX1, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("I2S TX2", SND_SOC_NOPM, MSM8X10_WCD_TX2, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("I2S TX3", SND_SOC_NOPM, MSM8X10_WCD_TX3, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("I2S TX4", SND_SOC_NOPM, MSM8X10_WCD_TX4, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+};
+
+
+static void msm8x10_wcd_codec_enable_adc_block(struct snd_soc_codec *codec,
+ int enable)
+{
+ struct msm8x10_wcd_priv *taiko = snd_soc_codec_get_drvdata(codec);
+
+ pr_debug("%s %d\n", __func__, enable);
+
+ if (enable) {
+ taiko->adc_count++;
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CDC_ANA_CLK_CTL,
+ 0x20, 0x20);
+ } else {
+ taiko->adc_count--;
+ if (!taiko->adc_count)
+ snd_soc_update_bits(codec,
+ MSM8X10_WCD_A_CDC_ANA_CLK_CTL,
+ 0x20, 0x0);
+ }
+}
+
+static int msm8x10_wcd_codec_enable_adc(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ u16 adc_reg;
+ u8 init_bit_shift;
+
+ pr_debug("%s %d\n", __func__, event);
+ adc_reg = MSM8X10_WCD_A_TX_1_2_TEST_CTL;
+
+ if (w->reg == MSM8X10_WCD_A_TX_1_EN)
+ init_bit_shift = 7;
+ else if (adc_reg == MSM8X10_WCD_A_TX_2_EN)
+ init_bit_shift = 6;
+ else {
+ pr_err("%s: Error, invalid adc register\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ msm8x10_wcd_codec_enable_adc_block(codec, 1);
+ snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
+ 1 << init_bit_shift);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ msm8x10_wcd_codec_enable_adc_block(codec, 0);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_codec_enable_lineout(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ u16 lineout_gain_reg;
+
+ pr_debug("%s %d %s\n", __func__, event, w->name);
+
+ switch (w->shift) {
+ case 0:
+ lineout_gain_reg = MSM8X10_WCD_A_RX_LINE_1_GAIN;
+ break;
+ default:
+ pr_err("%s: Error, incorrect lineout register value\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x40);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ pr_debug("%s: sleeping 16 ms after %s PA turn on\n",
+ __func__, w->name);
+ usleep_range(16000, 16100);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ pr_debug("%s %d %s\n", __func__, event, w->name);
+ return 0;
+}
+
+static int msm8x10_wcd_codec_enable_dmic(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct msm8x10_wcd_priv *msm8x10_wcd = snd_soc_codec_get_drvdata(codec);
+ u8 dmic_clk_en;
+ u16 dmic_clk_reg;
+ s32 *dmic_clk_cnt;
+ unsigned int dmic;
+ int ret;
+
+ ret = kstrtouint(strpbrk(w->name, "12"), 10, &dmic);
+ if (ret < 0) {
+ pr_err("%s: Invalid DMIC line on the codec\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (dmic) {
+ case 1:
+ case 2:
+ dmic_clk_en = 0x01;
+ dmic_clk_cnt = &(msm8x10_wcd->dmic_1_2_clk_cnt);
+ dmic_clk_reg = MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL;
+ pr_debug("%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n",
+ __func__, event, dmic, *dmic_clk_cnt);
+ break;
+ default:
+ pr_err("%s: Invalid DMIC Selection\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+
+ (*dmic_clk_cnt)++;
+ if (*dmic_clk_cnt == 1)
+ snd_soc_update_bits(codec, dmic_clk_reg,
+ dmic_clk_en, dmic_clk_en);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+
+ (*dmic_clk_cnt)--;
+ if (*dmic_clk_cnt == 0)
+ snd_soc_update_bits(codec, dmic_clk_reg,
+ dmic_clk_en, 0);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_codec_enable_micbias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct msm8x10_wcd_priv *msm8x10_wcd = snd_soc_codec_get_drvdata(codec);
+ u16 micb_int_reg;
+ u8 cfilt_sel_val = 0;
+ char *internal1_text = "Internal1";
+ char *internal2_text = "Internal2";
+ char *internal3_text = "Internal3";
+ enum wcd9xxx_notify_event e_post_off, e_pre_on, e_post_on;
+
+ pr_debug("%s %d\n", __func__, event);
+ switch (w->reg) {
+ case MSM8X10_WCD_A_MICB_1_CTL:
+ micb_int_reg = MSM8X10_WCD_A_MICB_1_INT_RBIAS;
+ cfilt_sel_val =
+ msm8x10_wcd->resmgr.pdata->micbias.bias1_cfilt_sel;
+ e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_1_ON;
+ e_post_on = WCD9XXX_EVENT_POST_MICBIAS_1_ON;
+ e_post_off = WCD9XXX_EVENT_POST_MICBIAS_1_OFF;
+ break;
+ default:
+ pr_err("%s: Error, invalid micbias register\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Let MBHC module know so micbias switch to be off */
+ wcd9xxx_resmgr_notifier_call(&msm8x10_wcd->resmgr, e_pre_on);
+
+ /* Get cfilt */
+ wcd9xxx_resmgr_cfilt_get(&msm8x10_wcd->resmgr, cfilt_sel_val);
+
+ if (strnstr(w->name, internal1_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0xE0, 0xE0);
+ else if (strnstr(w->name, internal2_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x1C, 0x1C);
+ else if (strnstr(w->name, internal3_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x3, 0x3);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(20000, 20100);
+ /* Let MBHC module know so micbias is on */
+ wcd9xxx_resmgr_notifier_call(&msm8x10_wcd->resmgr, e_post_on);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ /* Let MBHC module know so micbias switch to be off */
+ wcd9xxx_resmgr_notifier_call(&msm8x10_wcd->resmgr, e_post_off);
+
+ if (strnstr(w->name, internal1_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x00);
+ else if (strnstr(w->name, internal2_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x00);
+ else if (strnstr(w->name, internal3_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
+
+ /* Put cfilt */
+ wcd9xxx_resmgr_cfilt_put(&msm8x10_wcd->resmgr, cfilt_sel_val);
+ break;
+ }
+
+ return 0;
+}
+
+#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30
+#define CF_MIN_3DB_4HZ 0x0
+#define CF_MIN_3DB_75HZ 0x1
+#define CF_MIN_3DB_150HZ 0x2
+
+static int msm8x10_wcd_codec_enable_dec(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ unsigned int decimator;
+ char *dec_name = NULL;
+ char *widget_name = NULL;
+ char *temp;
+ int ret = 0;
+ u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
+ u8 dec_hpf_cut_of_freq;
+ int offset;
+
+ pr_debug("%s %d\n", __func__, event);
+
+ widget_name = kstrndup(w->name, 15, GFP_KERNEL);
+ if (!widget_name)
+ return -ENOMEM;
+ temp = widget_name;
+
+ dec_name = strsep(&widget_name, " ");
+ widget_name = temp;
+ if (!dec_name) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = kstrtouint(strpbrk(dec_name, "12"), 10, &decimator);
+ if (ret < 0) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ pr_debug("%s(): widget = %s dec_name = %s decimator = %u\n", __func__,
+ w->name, dec_name, decimator);
+
+ if (w->reg == MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL) {
+ dec_reset_reg = MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL;
+ offset = 0;
+ } else {
+ pr_err("%s: Error, incorrect dec\n", __func__);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ tx_vol_ctl_reg = MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG +
+ 32 * (decimator - 1);
+ tx_mux_ctl_reg = MSM8X10_WCD_A_CDC_TX1_MUX_CTL +
+ 32 * (decimator - 1);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Enableable TX digital mute */
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
+
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
+ 1 << w->shift);
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
+
+ dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg);
+
+ dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4;
+
+ tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq =
+ dec_hpf_cut_of_freq;
+
+ if ((dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ)) {
+
+ /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
+ CF_MIN_3DB_150HZ << 4);
+ }
+
+ /* enable HPF */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg , 0x08, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ /* Disable TX digital mute */
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
+
+ if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq !=
+ CF_MIN_3DB_150HZ) {
+
+ schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork,
+ msecs_to_jiffies(300));
+ }
+ /* apply the digital gain after the decimator is enabled*/
+ if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg))
+ snd_soc_write(codec,
+ tx_digital_gain_reg[w->shift + offset],
+ snd_soc_read(codec,
+ tx_digital_gain_reg[w->shift + offset])
+ );
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
+ cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
+ (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4);
+ break;
+ }
+out:
+ kfree(widget_name);
+ return ret;
+}
+
+static int msm8x10_wcd_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ pr_debug("%s %d %s\n", __func__, event, w->name);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 1 << w->shift);
+ snd_soc_update_bits(codec, MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 0x0);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ /* apply the digital gain after the interpolator is enabled*/
+ if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
+ snd_soc_write(codec,
+ rx_digital_gain_reg[w->shift],
+ snd_soc_read(codec,
+ rx_digital_gain_reg[w->shift])
+ );
+ break;
+ }
+ return 0;
+}
+
+
+/* The register address is the same as other codec so it can use resmgr */
+static int msm8x10_wcd_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct msm8x10_wcd_priv *msm8x10_wcd = snd_soc_codec_get_drvdata(codec);
+
+ pr_debug("%s %d\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ wcd9xxx_resmgr_enable_rx_bias(&msm8x10_wcd->resmgr, 1);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ wcd9xxx_resmgr_enable_rx_bias(&msm8x10_wcd->resmgr, 0);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_hphr_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ pr_debug("%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_hph_pa_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct msm8x10_wcd_priv *msm8x10_wcd = snd_soc_codec_get_drvdata(codec);
+ enum wcd9xxx_notify_event e_pre_on, e_post_off;
+
+ pr_debug("%s: %s event = %d\n", __func__, w->name, event);
+ if (w->shift == 5) {
+ e_pre_on = WCD9XXX_EVENT_PRE_HPHR_PA_ON;
+ e_post_off = WCD9XXX_EVENT_POST_HPHR_PA_OFF;
+ } else if (w->shift == 4) {
+ e_pre_on = WCD9XXX_EVENT_PRE_HPHL_PA_ON;
+ e_post_off = WCD9XXX_EVENT_POST_HPHL_PA_OFF;
+ } else {
+ pr_err("%s: Invalid w->shift %d\n", __func__, w->shift);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Let MBHC module know PA is turning on */
+ wcd9xxx_resmgr_notifier_call(&msm8x10_wcd->resmgr, e_pre_on);
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(10000, 10100);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ /* Let MBHC module know PA turned off */
+ wcd9xxx_resmgr_notifier_call(&msm8x10_wcd->resmgr, e_post_off);
+
+ /*
+ * schedule work is required because at the time HPH PA DAPM
+ * event callback is called by DAPM framework, CODEC dapm mutex
+ * would have been locked while snd_soc_jack_report also
+ * attempts to acquire same lock.
+ */
+ pr_debug("%s: sleep 10 ms after %s PA disable.\n", __func__,
+ w->name);
+ usleep_range(10000, 10100);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_lineout_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ pr_debug("%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x10_wcd_spk_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ pr_debug("%s %s %d\n", __func__, w->name, event);
+ return 0;
+}
+
+static const struct snd_soc_dapm_route audio_map[] = {
+ {"RX_I2S_CLK", NULL, "CDC_CONN"},
+ {"I2S RX1", NULL, "RX_I2S_CLK"},
+ {"I2S RX2", NULL, "RX_I2S_CLK"},
+ {"I2S RX3", NULL, "RX_I2S_CLK"},
+
+ {"I2S TX1", NULL, "TX_I2S_CLK"},
+ {"I2S TX2", NULL, "TX_I2S_CLK"},
+ {"I2S TX3", NULL, "TX_I2S_CLK"},
+ {"I2S TX4", NULL, "TX_I2S_CLK"},
+
+ {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
+
+ {"AIF1_CAP Mixer", "I2S TX1", "I2S TX1 MUX"},
+ {"AIF1_CAP Mixer", "I2S TX2", "I2S TX2 MUX"},
+ {"AIF1_CAP Mixer", "I2S TX3", "I2S TX3 MUX"},
+ {"AIF1_CAP Mixer", "I2S TX4", "I2S TX4 MUX"},
+
+ {"I2S TX1 MUX", NULL, "DEC1 MUX"},
+ {"I2S TX2 MUX", NULL, "DEC2 MUX"},
+ {"I2S TX3 MUX", NULL, "RX1 MIX1"},
+ {"I2S TX4 MUX", "RMIX2", "RX1 MIX2"},
+ {"I2S TX4 MUX", "RMIX3", "RX1 MIX3"},
+
+ /* Earpiece (RX MIX1) */
+ {"EAR", NULL, "EAR PA"},
+ {"EAR PA", NULL, "DAC1"},
+ {"DAC1", NULL, "CP"},
+
+ /* Headset (RX MIX1 and RX MIX2) */
+ {"HEADPHONE", NULL, "HPHL"},
+ {"HEADPHONE", NULL, "HPHR"},
+
+ {"HPHL", NULL, "HPHL DAC"},
+
+ {"HPHR", NULL, "HPHR DAC"},
+ {"HPHR_PA_MIXER", NULL, "HPHR DAC"},
+
+ {"HPHL DAC", NULL, "CP"},
+
+ {"HPHR DAC", NULL, "CP"},
+
+ {"DAC1", "Switch", "RX1 CHAIN"},
+ {"HPHL DAC", "Switch", "RX1 CHAIN"},
+ {"HPHR DAC", NULL, "RX2 CHAIN"},
+
+ {"LINEOUT1", NULL, "LINEOUT1 PA"},
+ {"SPK_OUT", NULL, "SPK PA"},
+
+ {"LINEOUT1 PA", NULL, "CP"},
+ {"LINEOUT1 PA", NULL, "LINEOUT1 DAC"},
+
+ {"LINEOUT1 DAC", "RX2 INPUT", "RX2 MIX1"},
+ {"LINEOUT1 DAC", "RX3 INPUT", "RX3 MIX1"},
+
+ {"SPK PA", NULL, "SPK DAC"},
+ {"SPK DAC", NULL, "RX7 MIX2"},
+
+ {"RX1 CHAIN", NULL, "RX1 MIX2"},
+ {"RX2 CHAIN", NULL, "RX2 MIX2"},
+
+ {"LINEOUT1 DAC", NULL, "RX_BIAS"},
+ {"SPK DAC", NULL, "RX_BIAS"},
+
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
+ {"RX1 MIX2", NULL, "RX1 MIX1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP2"},
+ {"RX2 MIX2", NULL, "RX2 MIX1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP2"},
+
+ {"I2S RX1 MUX", "AIF1_PB", "AIF1 PB"},
+ {"I2S RX2 MUX", "AIF1_PB", "AIF1 PB"},
+ {"I2S RX3 MUX", "AIF1_PB", "AIF1 PB"},
+
+ {"I2S RX1", NULL, "I2S RX1 MUX"},
+ {"I2S RX2", NULL, "I2S RX2 MUX"},
+ {"I2S RX3", NULL, "I2S RX3 MUX"},
+
+ {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
+ {"RX1 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
+ {"RX1 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
+
+ {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
+ {"RX2 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
+ {"RX2 MIX1 INP2", "IIR1", "IIR1"},
+
+ {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
+ {"RX3 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
+ {"RX3 MIX1 INP2", "IIR1", "IIR1"},
+
+ /* Decimator Inputs */
+ {"DEC1 MUX", "DMIC1", "DMIC1"},
+ {"DEC1 MUX", "DMIC2", "DMIC2"},
+ {"DEC1 MUX", "ADC1", "ADC1"},
+ {"DEC1 MUX", "ADC2", "ADC2"},
+ {"DEC1 MUX", NULL, "CDC_CONN"},
+
+ {"DEC2 MUX", "DMIC1", "DMIC1"},
+ {"DEC2 MUX", "DMIC2", "DMIC2"},
+ {"DEC2 MUX", "ADC1", "ADC1"},
+ {"DEC2 MUX", "ADC2", "ADC2"},
+ {"DEC2 MUX", NULL, "CDC_CONN"},
+
+ /* ADC Connections */
+ {"ADC1", NULL, "AMIC1"},
+ {"ADC2", NULL, "AMIC2"},
+
+ {"IIR1", NULL, "IIR1 INP1 MUX"},
+ {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
+ {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
+
+ /* There is no LDO_H in Helicon */
+ {"MIC BIAS1 Internal1", NULL, "LDO_H"},
+ {"MIC BIAS1 Internal2", NULL, "LDO_H"},
+ {"MIC BIAS1 External", NULL, "LDO_H"},
+};
+
+
+static int msm8x10_wcd_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct msm8x10_wcd *msm8x10_wcd_core =
+ dev_get_drvdata(dai->codec->dev);
+ pr_debug("%s(): substream = %s stream = %d\n" , __func__,
+ substream->name, substream->stream);
+ if ((msm8x10_wcd_core != NULL) &&
+ (msm8x10_wcd_core->dev != NULL))
+ pm_runtime_get_sync(msm8x10_wcd_core->dev);
+
+ return 0;
+}
+
+static void msm8x10_wcd_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct msm8x10_wcd *msm8x10_wcd_core =
+ dev_get_drvdata(dai->codec->dev);
+ pr_debug("%s(): substream = %s stream = %d\n" , __func__,
+ substream->name, substream->stream);
+ if ((msm8x10_wcd_core != NULL) &&
+ (msm8x10_wcd_core->dev != NULL)) {
+ pm_runtime_mark_last_busy(msm8x10_wcd_core->dev);
+ pm_runtime_put(msm8x10_wcd_core->dev);
+ }
+}
+
+int msm8x10_wcd_mclk_enable(struct snd_soc_codec *codec,
+ int mclk_enable, bool dapm)
+{
+ struct msm8x10_wcd_priv *msm8x10_wcd = snd_soc_codec_get_drvdata(codec);
+
+ pr_debug("%s: mclk_enable = %u, dapm = %d\n", __func__, mclk_enable,
+ dapm);
+
+ WCD9XXX_BCL_LOCK(&msm8x10_wcd->resmgr);
+ if (mclk_enable) {
+ wcd9xxx_resmgr_get_bandgap(&msm8x10_wcd->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ wcd9xxx_resmgr_get_clk_block(&msm8x10_wcd->resmgr,
+ WCD9XXX_CLK_MCLK);
+ } else {
+ /* Put clock and BG */
+ wcd9xxx_resmgr_put_clk_block(&msm8x10_wcd->resmgr,
+ WCD9XXX_CLK_MCLK);
+ wcd9xxx_resmgr_put_bandgap(&msm8x10_wcd->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ }
+ WCD9XXX_BCL_UNLOCK(&msm8x10_wcd->resmgr);
+
+ return 0;
+}
+
+static int msm8x10_wcd_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ pr_debug("%s\n", __func__);
+ return 0;
+}
+
+static int msm8x10_wcd_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ pr_debug("%s\n", __func__);
+ return 0;
+}
+
+static int msm8x10_wcd_set_channel_map(struct snd_soc_dai *dai,
+ unsigned int tx_num, unsigned int *tx_slot,
+ unsigned int rx_num, unsigned int *rx_slot)
+
+{
+ pr_debug("%s\n", __func__);
+ return 0;
+}
+
+static int msm8x10_wcd_get_channel_map(struct snd_soc_dai *dai,
+ unsigned int *tx_num, unsigned int *tx_slot,
+ unsigned int *rx_num, unsigned int *rx_slot)
+
+{
+ pr_debug("%s\n", __func__);
+ return 0;
+}
+
+static int msm8x10_wcd_set_interpolator_rate(struct snd_soc_dai *dai,
+ u8 rx_fs_rate_reg_val, u32 sample_rate)
+{
+ return 0;
+}
+
+static int msm8x10_wcd_set_decimator_rate(struct snd_soc_dai *dai,
+ u8 tx_fs_rate_reg_val, u32 sample_rate)
+{
+ return 0;
+}
+
+static int msm8x10_wcd_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ u8 tx_fs_rate, rx_fs_rate;
+ int ret;
+
+ pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
+ dai->name, dai->id, params_rate(params),
+ params_channels(params));
+
+ switch (params_rate(params)) {
+ case 8000:
+ tx_fs_rate = 0x00;
+ rx_fs_rate = 0x00;
+ break;
+ case 16000:
+ tx_fs_rate = 0x01;
+ rx_fs_rate = 0x20;
+ break;
+ case 32000:
+ tx_fs_rate = 0x02;
+ rx_fs_rate = 0x40;
+ break;
+ case 48000:
+ tx_fs_rate = 0x03;
+ rx_fs_rate = 0x60;
+ break;
+ case 96000:
+ tx_fs_rate = 0x04;
+ rx_fs_rate = 0x80;
+ break;
+ case 192000:
+ tx_fs_rate = 0x05;
+ rx_fs_rate = 0xA0;
+ break;
+ default:
+ pr_err("%s: Invalid sampling rate %d\n", __func__,
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ switch (substream->stream) {
+ case SNDRV_PCM_STREAM_CAPTURE:
+ ret = msm8x10_wcd_set_decimator_rate(dai, tx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ pr_err("%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+ break;
+ case SNDRV_PCM_STREAM_PLAYBACK:
+ ret = msm8x10_wcd_set_interpolator_rate(dai, rx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ pr_err("%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+ break;
+ default:
+ pr_err("%s: Invalid stream type %d\n", __func__,
+ substream->stream);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct snd_soc_dai_ops msm8x10_wcd_dai_ops = {
+ .startup = msm8x10_wcd_startup,
+ .shutdown = msm8x10_wcd_shutdown,
+ .hw_params = msm8x10_wcd_hw_params,
+ .set_sysclk = msm8x10_wcd_set_dai_sysclk,
+ .set_fmt = msm8x10_wcd_set_dai_fmt,
+ .set_channel_map = msm8x10_wcd_set_channel_map,
+ .get_channel_map = msm8x10_wcd_get_channel_map,
+};
+
+static struct snd_soc_dai_driver msm8x10_wcd_i2s_dai[] = {
+ {
+ .name = "msm8x10_wcd_i2s_rx1",
+ .id = AIF1_PB,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .rates = MSM8X10_WCD_RATES,
+ .formats = MSM8X10_WCD_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &msm8x10_wcd_dai_ops,
+ },
+ {
+ .name = "msm8x10_wcd_i2s_tx1",
+ .id = AIF1_CAP,
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .rates = MSM8X10_WCD_RATES,
+ .formats = MSM8X10_WCD_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &msm8x10_wcd_dai_ops,
+ },
+};
+
+static int msm8x10_wcd_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ pr_debug("%s: Sleeping 20ms after enabling EAR PA\n",
+ __func__);
+ msleep(20);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ pr_debug("%s: Sleeping 20ms after disabling EAR PA\n",
+ __func__);
+ msleep(20);
+ break;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget msm8x10_wcd_dapm_widgets[] = {
+ /*RX stuff */
+ SND_SOC_DAPM_OUTPUT("EAR"),
+
+ SND_SOC_DAPM_PGA_E("EAR PA", MSM8X10_WCD_A_RX_EAR_EN, 4, 0, NULL, 0,
+ msm8x10_wcd_codec_enable_ear_pa, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_MIXER("DAC1", MSM8X10_WCD_A_RX_EAR_EN, 6, 0, dac1_switch,
+ ARRAY_SIZE(dac1_switch)),
+
+ SND_SOC_DAPM_AIF_IN("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
+ AIF1_PB, 0),
+
+ SND_SOC_DAPM_MUX("I2S RX1 MUX", SND_SOC_NOPM, MSM8X10_WCD_RX1, 0,
+ &slim_rx_mux[MSM8X10_WCD_RX1]),
+ SND_SOC_DAPM_MUX("I2S RX2 MUX", SND_SOC_NOPM, MSM8X10_WCD_RX2, 0,
+ &slim_rx_mux[MSM8X10_WCD_RX2]),
+ SND_SOC_DAPM_MUX("I2S RX3 MUX", SND_SOC_NOPM, MSM8X10_WCD_RX3, 0,
+ &slim_rx_mux[MSM8X10_WCD_RX3]),
+
+ SND_SOC_DAPM_MIXER("I2S RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("I2S RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("I2S RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("I2S RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("I2S RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Headphone */
+ SND_SOC_DAPM_OUTPUT("HEADPHONE"),
+ SND_SOC_DAPM_PGA_E("HPHL", MSM8X10_WCD_A_RX_HPH_CNP_EN,
+ 5, 0, NULL, 0,
+ msm8x10_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER("HPHL DAC", MSM8X10_WCD_A_RX_HPH_L_DAC_CTL,
+ 7, 0,
+ hphl_switch, ARRAY_SIZE(hphl_switch)),
+
+ SND_SOC_DAPM_PGA_E("HPHR", MSM8X10_WCD_A_RX_HPH_CNP_EN,
+ 4, 0, NULL, 0,
+ msm8x10_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("HPHR DAC", NULL, MSM8X10_WCD_A_RX_HPH_R_DAC_CTL,
+ 7, 0,
+ msm8x10_wcd_hphr_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* Speaker */
+ SND_SOC_DAPM_OUTPUT("LINEOUT1"),
+ SND_SOC_DAPM_OUTPUT("SPK_OUT"),
+
+ SND_SOC_DAPM_PGA_E("LINEOUT1 PA", MSM8X10_WCD_A_RX_LINE_CNP_EN,
+ 0, 0, NULL, 0, msm8x10_wcd_codec_enable_lineout,
+ SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_PGA_E("SPK PA", MSM8X10_WCD_A_SPKR_DRV_EN,
+ 7, 0 , NULL, 0, msm8x10_wcd_codec_enable_spk_pa,
+ SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("LINEOUT1 DAC", NULL,
+ MSM8X10_WCD_A_RX_LINE_1_DAC_CTL, 7, 0,
+ msm8x10_wcd_lineout_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("SPK DAC", NULL, SND_SOC_NOPM, 0, 0,
+ msm8x10_wcd_spk_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_MIXER_E("RX1 MIX2",
+ MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
+ 0, msm8x10_wcd_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX2 MIX2",
+ MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
+ 0, msm8x10_wcd_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX3 MIX1",
+ MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
+ 0, msm8x10_wcd_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_MIXER("RX1 CHAIN", MSM8X10_WCD_A_CDC_RX1_B6_CTL,
+ 5, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 CHAIN", MSM8X10_WCD_A_CDC_RX2_B6_CTL,
+ 5, 0, NULL, 0),
+
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp3_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp1_mux),
+
+ SND_SOC_DAPM_SUPPLY("CP", MSM8X10_WCD_A_CP_EN, 0, 0,
+ msm8x10_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+ SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
+ msm8x10_wcd_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* TX */
+
+ SND_SOC_DAPM_SUPPLY("CDC_CONN", MSM8X10_WCD_A_CDC_CLK_OTHR_CTL,
+ 2, 0, NULL, 0),
+
+
+ SND_SOC_DAPM_INPUT("AMIC1"),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 External",
+ MSM8X10_WCD_A_MICB_1_CTL, 7, 0,
+ msm8x10_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal1",
+ MSM8X10_WCD_A_MICB_1_CTL, 7, 0,
+ msm8x10_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal2",
+ MSM8X10_WCD_A_MICB_1_CTL, 7, 0,
+ msm8x10_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_ADC_E("ADC1", NULL, MSM8X10_WCD_A_TX_1_EN, 7, 0,
+ msm8x10_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("ADC1", NULL, MSM8X10_WCD_A_TX_2_EN, 7, 0,
+ msm8x10_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_INPUT("AMIC3"),
+
+ SND_SOC_DAPM_MUX_E("DEC1 MUX",
+ MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
+ &dec1_mux, msm8x10_wcd_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX_E("DEC2 MUX",
+ MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
+ &dec2_mux, msm8x10_wcd_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_INPUT("AMIC2"),
+ SND_SOC_DAPM_AIF_OUT("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
+ AIF1_CAP, 0),
+
+ SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
+ aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
+
+ /* Digital Mic Inputs */
+ SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
+ msm8x10_wcd_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
+ msm8x10_wcd_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* Sidetone */
+ SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
+ SND_SOC_DAPM_PGA("IIR1", MSM8X10_WCD_A_CDC_CLK_SD_CTL, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL,
+ 4, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL, 4,
+ 0, NULL, 0),
+};
+
+static const struct msm8x10_wcd_reg_mask_val msm8x10_wcd_reg_defaults[] = {
+
+ /* set MCLk to 9.6 */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_CHIP_CTL, 0x0A),
+
+ /* EAR PA deafults */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_RX_EAR_CMBUFF, 0x05),
+
+ /* RX deafults */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_CDC_RX1_B5_CTL, 0x78),
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_CDC_RX2_B5_CTL, 0x78),
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_CDC_RX3_B5_CTL, 0x78),
+
+ /* RX1 and RX2 defaults */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_CDC_RX1_B6_CTL, 0xA0),
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_CDC_RX2_B6_CTL, 0xA0),
+
+ /* RX3 to RX7 defaults */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_CDC_RX3_B6_CTL, 0x80),
+
+ /* Reduce HPH DAC bias to 70% */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_RX_HPH_BIAS_PA, 0x7A),
+ /*Reduce EAR DAC bias to 70% */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_RX_EAR_BIAS_PA, 0x76),
+ /* Reduce LINE DAC bias to 70% */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_RX_LINE_BIAS_PA, 0x78),
+
+
+ /* Disable TX7 internal biasing path which can cause leakage */
+ MSM8X10_WCD_REG_VAL(MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1, 0xBF),
+};
+
+static void msm8x10_wcd_update_reg_defaults(struct snd_soc_codec *codec)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(msm8x10_wcd_reg_defaults); i++)
+ snd_soc_write(codec, msm8x10_wcd_reg_defaults[i].reg,
+ msm8x10_wcd_reg_defaults[i].val);
+}
+
+static const struct msm8x10_wcd_reg_mask_val
+ msm8x10_wcd_codec_reg_init_val[] = {
+ /* Initialize current threshold to 350MA
+ * number of wait and run cycles to 4096
+ */
+ {MSM8X10_WCD_A_RX_HPH_OCP_CTL, 0xE1, 0x61},
+ {MSM8X10_WCD_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
+
+ /* Initialize gain registers to use register gain */
+ {MSM8X10_WCD_A_RX_HPH_L_GAIN, 0x20, 0x20},
+ {MSM8X10_WCD_A_RX_HPH_R_GAIN, 0x20, 0x20},
+ {MSM8X10_WCD_A_RX_LINE_1_GAIN, 0x20, 0x20},
+
+ /*enable HPF filter for TX paths */
+ {MSM8X10_WCD_A_CDC_TX1_MUX_CTL, 0x8, 0x0},
+ {MSM8X10_WCD_A_CDC_TX2_MUX_CTL, 0x8, 0x0},
+
+ /* config Decimator for DMIC CLK_MODE_1(3.2Mhz@9.6Mhz mclk) */
+ {MSM8X10_WCD_A_CDC_TX1_DMIC_CTL, 0x7, 0x1},
+ {MSM8X10_WCD_A_CDC_TX2_DMIC_CTL, 0x7, 0x1},
+
+ /* config DMIC clk to CLK_MODE_1 (3.2Mhz@9.6Mhz mclk) */
+ {MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL, 0xEE, 0x22},
+
+};
+
+static void msm8x10_wcd_codec_init_reg(struct snd_soc_codec *codec)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(msm8x10_wcd_codec_reg_init_val); i++)
+ snd_soc_update_bits(codec,
+ msm8x10_wcd_codec_reg_init_val[i].reg,
+ msm8x10_wcd_codec_reg_init_val[i].mask,
+ msm8x10_wcd_codec_reg_init_val[i].val);
+}
+
+int msm8x10_wcd_hs_detect(struct snd_soc_codec *codec,
+ struct msm8x10_wcd_mbhc_config *mbhc_cfg)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(msm8x10_wcd_hs_detect);
+
+static int msm8x10_wcd_codec_probe(struct snd_soc_codec *codec)
+{
+ msm8x10_wcd_codec_init_reg(codec);
+
+ msm8x10_wcd_update_reg_defaults(codec);
+
+ dev_dbg(codec->dev, "%s()\n", __func__);
+
+ return 0;
+}
+
+static int msm8x10_wcd_codec_remove(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_msm8x10_wcd = {
+ .probe = msm8x10_wcd_codec_probe,
+ .remove = msm8x10_wcd_codec_remove,
+
+ .read = msm8x10_wcd_read,
+ .write = msm8x10_wcd_write,
+
+ .readable_register = msm8x10_wcd_readable,
+ .volatile_register = msm8x10_wcd_volatile,
+
+ .reg_cache_size = MSM8X10_WCD_CACHE_SIZE,
+ .reg_cache_default = msm8x10_wcd_reset_reg_defaults,
+ .reg_word_size = 1,
+
+ .controls = msm8x10_wcd_snd_controls,
+ .num_controls = ARRAY_SIZE(msm8x10_wcd_snd_controls),
+ .dapm_widgets = msm8x10_wcd_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(msm8x10_wcd_dapm_widgets),
+ .dapm_routes = audio_map,
+ .num_dapm_routes = ARRAY_SIZE(audio_map),
+};
+
+static int __devinit msm8x10_wcd_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret;
+ struct msm8x10_wcd_pdata *pdata;
+ if (client->dev.of_node) {
+ dev_dbg(&client->dev, "%s:Platform data from device tree\n",
+ __func__);
+ pdata = msm8x10_wcd_populate_dt_pdata(&client->dev);
+ client->dev.platform_data = pdata;
+ } else {
+ dev_dbg(&client->dev, "%s:Platform data from board file\n",
+ __func__);
+ pdata = client->dev.platform_data;
+ }
+
+ ret = snd_soc_register_codec(&client->dev,
+ &soc_codec_dev_msm8x10_wcd,
+ msm8x10_wcd_i2s_dai, ARRAY_SIZE(msm8x10_wcd_i2s_dai));
+ dev_dbg(&client->dev, "%s:ret = 0x%x\n", __func__, ret);
+
+ return ret;
+}
+
+static int __devexit msm8x10_wcd_i2c_remove(struct i2c_client *client)
+{
+ return 0;
+}
+
+static struct i2c_device_id msm8x10_wcd_id_table[] = {
+ {"msm8x10-wcd-i2c", MSM8X10_WCD_I2C_TOP_LEVEL},
+ {"msm8x10-wcd-i2c", MSM8X10_WCD_I2C_ANALOG},
+ {"msm8x10-wcd-i2c", MSM8X10_WCD_I2C_DIGITAL_1},
+ {"msm8x10-wcd-i2c", MSM8X10_WCD_I2C_DIGITAL_2},
+ {}
+};
+
+static struct of_device_id msm8x10_wcd_of_match[] = {
+ { .compatible = "qcom,msm8x10-wcd-i2c",},
+ { },
+};
+
+
+static struct i2c_driver msm8x10_wcd_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "msm8x10-wcd-i2c-core",
+ .of_match_table = msm8x10_wcd_of_match
+ },
+ .id_table = msm8x10_wcd_id_table,
+ .probe = msm8x10_wcd_i2c_probe,
+ .remove = __devexit_p(msm8x10_wcd_i2c_remove),
+};
+
+static int __init msm8x10_wcd_codec_init(void)
+{
+ int ret;
+
+ pr_debug("%s:\n", __func__);
+ ret = i2c_add_driver(&msm8x10_wcd_i2c_driver);
+ if (ret != 0)
+ pr_err("%s: Failed to add msm8x10 wcd I2C driver - error code %d\n",
+ __func__, ret);
+ return ret;
+}
+
+static void __exit msm8x10_wcd_codec_exit(void)
+{
+ i2c_del_driver(&msm8x10_wcd_i2c_driver);
+}
+
+
+module_init(msm8x10_wcd_codec_init);
+module_exit(msm8x10_wcd_codec_exit);
+
+MODULE_DESCRIPTION("MSM8x10 Audio codec driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(i2c, msm8x10_wcd_id_table);
+
diff --git a/sound/soc/codecs/msm8x10-wcd.h b/sound/soc/codecs/msm8x10-wcd.h
new file mode 100644
index 0000000..365d526
--- /dev/null
+++ b/sound/soc/codecs/msm8x10-wcd.h
@@ -0,0 +1,226 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef MSM8X10_WCD_H
+#define MSM8X10_WCD_H
+
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include "wcd9xxx-mbhc.h"
+#include "wcd9xxx-resmgr.h"
+
+#define MSM8X10_WCD_NUM_REGISTERS 0x600
+#define MSM8X10_WCD_MAX_REGISTER (MSM8X10_WCD_NUM_REGISTERS-1)
+#define MSM8X10_WCD_CACHE_SIZE MSM8X10_WCD_NUM_REGISTERS
+#define MSM8X10_WCD_NUM_IRQ_REGS 3
+#define MAX_REGULATOR 7
+#define MSM8X10_WCD_REG_VAL(reg, val) {reg, 0, val}
+
+#define MSM8X10_WCD_IS_DINO_REG(reg) \
+ (((reg >= 0x400) && (reg <= 0x5FF)) ? 1 : 0)
+#define MSM8X10_WCD_IS_HELICON_REG(reg) \
+ (((reg >= 0x000) && (reg <= 0x1FF)) ? 1 : 0)
+extern const u8 msm8x10_wcd_reg_readable[MSM8X10_WCD_CACHE_SIZE];
+extern const u8 msm8x10_wcd_reset_reg_defaults[MSM8X10_WCD_CACHE_SIZE];
+struct msm8x10_wcd_codec_dai_data {
+ u32 rate;
+ u32 *ch_num;
+ u32 ch_act;
+ u32 ch_tot;
+};
+
+enum msm8x10_wcd_pid_current {
+ MSM8X10_WCD_PID_MIC_2P5_UA,
+ MSM8X10_WCD_PID_MIC_5_UA,
+ MSM8X10_WCD_PID_MIC_10_UA,
+ MSM8X10_WCD_PID_MIC_20_UA,
+};
+
+struct msm8x10_wcd_reg_mask_val {
+ u16 reg;
+ u8 mask;
+ u8 val;
+};
+
+enum msm8x10_wcd_mbhc_analog_pwr_cfg {
+ MSM8X10_WCD_ANALOG_PWR_COLLAPSED = 0,
+ MSM8X10_WCD_ANALOG_PWR_ON,
+ MSM8X10_WCD_NUM_ANALOG_PWR_CONFIGS,
+};
+
+/* Number of input and output Slimbus port */
+enum {
+ MSM8X10_WCD_RX1 = 0,
+ MSM8X10_WCD_RX2,
+ MSM8X10_WCD_RX3,
+ MSM8X10_WCD_RX_MAX,
+};
+
+enum {
+ MSM8X10_WCD_TX1 = 0,
+ MSM8X10_WCD_TX2,
+ MSM8X10_WCD_TX3,
+ MSM8X10_WCD_TX4,
+ MSM8X10_WCD_TX_MAX,
+};
+
+enum {
+ /* INTR_REG 0 */
+ MSM8X10_WCD_IRQ_RESERVED_0 = 0,
+ MSM8X10_WCD_IRQ_MBHC_REMOVAL,
+ MSM8X10_WCD_IRQ_MBHC_SHORT_TERM,
+ MSM8X10_WCD_IRQ_MBHC_PRESS,
+ MSM8X10_WCD_IRQ_MBHC_RELEASE,
+ MSM8X10_WCD_IRQ_MBHC_POTENTIAL,
+ MSM8X10_WCD_IRQ_MBHC_INSERTION,
+ MSM8X10_WCD_IRQ_MBHC_HS_DET,
+ /* INTR_REG 1 */
+ MSM8X10_WCD_IRQ_PA_STARTUP,
+ MSM8X10_WCD_IRQ_BG_PRECHARGE,
+ MSM8X10_WCD_IRQ_RESERVED_1,
+ MSM8X10_WCD_IRQ_EAR_PA_OCPL_FAULT,
+ MSM8X10_WCD_IRQ_EAR_PA_STARTUP,
+ MSM8X10_WCD_IRQ_SPKR_PA_OCPL_FAULT,
+ MSM8X10_WCD_IRQ_SPKR_CLIP_FAULT,
+ MSM8X10_WCD_IRQ_RESERVED_2,
+ /* INTR_REG 2 */
+ MSM8X10_WCD_IRQ_HPH_L_PA_STARTUP,
+ MSM8X10_WCD_IRQ_HPH_R_PA_STARTUP,
+ MSM8X10_WCD_IRQ_HPH_PA_OCPL_FAULT,
+ MSM8X10_WCD_IRQ_HPH_PA_OCPR_FAULT,
+ MSM8X10_WCD_IRQ_RESERVED_3,
+ MSM8X10_WCD_IRQ_RESERVED_4,
+ MSM8X10_WCD_IRQ_RESERVED_5,
+ MSM8X10_WCD_IRQ_RESERVED_6,
+ MSM8X10_WCD_NUM_IRQS,
+};
+
+/*
+ * Each micbias can be assigned to one of three cfilters
+ * Vbatt_min >= .15V + ldoh_v
+ * ldoh_v >= .15v + cfiltx_mv
+ * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
+ * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
+ * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
+ * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
+ */
+struct msm8x10_wcd_micbias_setting {
+ u8 ldoh_v;
+ u32 cfilt1_mv; /* in mv */
+ /*
+ * Different WCD9xxx series codecs may not
+ * have 4 mic biases. If a codec has fewer
+ * mic biases, some of these properties will
+ * not be used.
+ */
+ u8 bias1_cfilt_sel;
+ u8 bias1_cap_mode;
+};
+
+struct msm8x10_wcd_ocp_setting {
+ unsigned int use_pdata:1; /* 0 - use sys default as recommended */
+ unsigned int num_attempts:4; /* up to 15 attempts */
+ unsigned int run_time:4; /* in duty cycle */
+ unsigned int wait_time:4; /* in duty cycle */
+ unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */
+};
+
+struct msm8x10_wcd_regulator {
+ const char *name;
+ int min_uV;
+ int max_uV;
+ int optimum_uA;
+ struct regulator *regulator;
+};
+
+struct msm8x10_wcd_pdata {
+ int irq;
+ int irq_base;
+ int num_irqs;
+ int reset_gpio;
+ void *msm8x10_wcd_ahb_base_vaddr;
+ struct msm8x10_wcd_micbias_setting micbias;
+ struct msm8x10_wcd_ocp_setting ocp;
+ struct msm8x10_wcd_regulator regulator[MAX_REGULATOR];
+ u32 mclk_rate;
+};
+
+enum msm8x10_wcd_micbias_num {
+ MSM8X10_WCD_MICBIAS1 = 0,
+};
+
+struct msm8x10_wcd_mbhc_config {
+ struct snd_soc_jack *headset_jack;
+ struct snd_soc_jack *button_jack;
+ bool read_fw_bin;
+ /*
+ * void* calibration contains:
+ * struct msm8x10_wcd_mbhc_general_cfg generic;
+ * struct msm8x10_wcd_mbhc_plug_detect_cfg plug_det;
+ * struct msm8x10_wcd_mbhc_plug_type_cfg plug_type;
+ * struct msm8x10_wcd_mbhc_btn_detect_cfg btn_det;
+ * struct msm8x10_wcd_mbhc_imped_detect_cfg imped_det;
+ * Note: various size depends on btn_det->num_btn
+ */
+ void *calibration;
+ enum msm8x10_wcd_micbias_num micbias;
+ int (*mclk_cb_fn) (struct snd_soc_codec*, int, bool);
+ unsigned int mclk_rate;
+ unsigned int gpio;
+ unsigned int gpio_irq;
+ int gpio_level_insert;
+ bool detect_extn_cable;
+ /* swap_gnd_mic returns true if extern GND/MIC swap switch toggled */
+ bool (*swap_gnd_mic) (struct snd_soc_codec *);
+};
+
+enum msm8x10_wcd_pm_state {
+ MSM8X10_WCD_PM_SLEEPABLE,
+ MSM8X10_WCD_PM_AWAKE,
+ MSM8X10_WCD_PM_ASLEEP,
+};
+
+struct msm8x10_wcd {
+ struct device *dev;
+ struct mutex io_lock;
+ struct mutex xfer_lock;
+ struct mutex irq_lock;
+ u8 version;
+
+ int reset_gpio;
+
+ u32 num_of_supplies;
+ struct regulator_bulk_data *supplies;
+
+ enum msm8x10_wcd_pm_state pm_state;
+ struct mutex pm_lock;
+ /* pm_wq notifies change of pm_state */
+ wait_queue_head_t pm_wq;
+ struct pm_qos_request pm_qos_req;
+ int wlock_holders;
+
+ u8 idbyte[4];
+
+ unsigned int irq_base;
+ unsigned int irq;
+ u8 irq_masks_cur[MSM8X10_WCD_NUM_IRQ_REGS];
+ u8 irq_masks_cache[MSM8X10_WCD_NUM_IRQ_REGS];
+ bool irq_level_high[MSM8X10_WCD_NUM_IRQS];
+ int num_irqs;
+ u32 mclk_rate;
+};
+
+extern int msm8x10_wcd_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
+ bool dapm);
+extern int msm8x10_wcd_hs_detect(struct snd_soc_codec *codec,
+ struct msm8x10_wcd_mbhc_config *mbhc_cfg);
+
+#endif
diff --git a/sound/soc/codecs/msm8x10_wcd_registers.h b/sound/soc/codecs/msm8x10_wcd_registers.h
new file mode 100644
index 0000000..a10f31f
--- /dev/null
+++ b/sound/soc/codecs/msm8x10_wcd_registers.h
@@ -0,0 +1,641 @@
+ /* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef MSM8X10_WCD_REGISTERS_H
+#define MSM8X10_WCD_REGISTERS_H
+
+#define MSM8X10_WCD_A_CHIP_CTL (0x000)
+#define MSM8X10_WCD_A_CHIP_CTL__POR (0x04)
+#define MSM8X10_WCD_A_CHIP_STATUS (0x001)
+#define MSM8X10_WCD_A_CHIP_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT (0x002)
+#define MSM8X10_WCD_A_CDC_TLMM_MODE_SELECT__POR (0x00)
+#define MSM8X10_WCD_A_MODE_LOCK (0x003)
+#define MSM8X10_WCD_A_MODE_LOCK__POR (0x00)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_0 (0x004)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_0__POR (0x00)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_1 (0x005)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_1__POR (0x00)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_2 (0x006)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_2__POR (0x04)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_3 (0x007)
+#define MSM8X10_WCD_A_CHIP_ID_BYTE_3__POR (0x01)
+#define MSM8X10_WCD_A_CHIP_VERSION (0x008)
+#define MSM8X10_WCD_A_CHIP_VERSION__POR (0x00)
+#define MSM8X10_WCD_A_ANALOG_SLAVE_ID (0x00C)
+#define MSM8X10_WCD_A_ANALOG_SLAVE_ID__POR (0x77)
+#define MSM8X10_WCD_A_PIN_CTL_OE (0x010)
+#define MSM8X10_WCD_A_PIN_CTL_OE__POR (0x07)
+#define MSM8X10_WCD_A_PIN_CTL_DATA (0x012)
+#define MSM8X10_WCD_A_PIN_CTL_DATA__POR (0x00)
+#define MSM8X10_WCD_A_PIN_STATUS (0x014)
+#define MSM8X10_WCD_A_PIN_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_HDRIVE_CTL (0x018)
+#define MSM8X10_WCD_A_HDRIVE_CTL__POR (0x01)
+#define MSM8X10_WCD_A_HDRIVE_I2C_CTL (0x019)
+#define MSM8X10_WCD_A_HDRIVE_I2C_CTL__POR (0x01)
+#define MSM8X10_WCD_A_CDC_RST_CTL (0x020)
+#define MSM8X10_WCD_A_CDC_RST_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TOP_CLK_CTL (0x022)
+#define MSM8X10_WCD_A_CDC_TOP_CLK_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_ANA_CLK_CTL (0x023)
+#define MSM8X10_WCD_A_CDC_ANA_CLK_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_DIG_CLK_CTL (0x024)
+#define MSM8X10_WCD_A_CDC_DIG_CLK_CTL__POR (0x00)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL0 (0x030)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL0__POR (0x80)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL1 (0x031)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL1__POR (0x00)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL2 (0x032)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL2__POR (0x00)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL3 (0x033)
+#define MSM8X10_WCD_A_PROCESS_MONITOR_CTL3__POR (0x01)
+#define MSM8X10_WCD_A_QFUSE_CTL (0x034)
+#define MSM8X10_WCD_A_QFUSE_CTL__POR (0x00)
+#define MSM8X10_WCD_A_QFUSE_STATUS (0x035)
+#define MSM8X10_WCD_A_QFUSE_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT0 (0x036)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT0__POR (0x00)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT1 (0x037)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT1__POR (0x00)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT2 (0x038)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT2__POR (0x00)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT3 (0x039)
+#define MSM8X10_WCD_A_QFUSE_DATA_OUT3__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_TX1_CTL (0x040)
+#define MSM8X10_WCD_A_CDC_CONN_TX1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_TX2_CTL (0x041)
+#define MSM8X10_WCD_A_CDC_CONN_TX2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL (0x042)
+#define MSM8X10_WCD_A_CDC_CONN_HPHR_DAC_CTL__POR (0x01)
+#define MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL (0x043)
+#define MSM8X10_WCD_A_CDC_CONN_LO_DAC_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_CTL (0x044)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_CTL (0x045)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX3_CTL (0x046)
+#define MSM8X10_WCD_A_CDC_CONN_RX3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_DIGITAL_DEBUG_CTL (0x048)
+#define MSM8X10_WCD_A_DIGITAL_DEBUG_CTL__POR (0x00)
+#define MSM8X10_WCD_A_ANALOG_DEBUG_CTL (0x049)
+#define MSM8X10_WCD_A_ANALOG_DEBUG_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_CTL (0x050)
+#define MSM8X10_WCD_A_CDC_RX1_CTL__POR (0x7C)
+#define MSM8X10_WCD_A_CDC_RX2_CTL (0x058)
+#define MSM8X10_WCD_A_CDC_RX2_CTL__POR (0x7C)
+#define MSM8X10_WCD_A_CDC_RX3_CTL (0x060)
+#define MSM8X10_WCD_A_CDC_RX3_CTL__POR (0x7C)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA0 (0x070)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA0__POR (0x00)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA1 (0x071)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA1__POR (0x00)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA2 (0x072)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA2__POR (0x00)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA3 (0x073)
+#define MSM8X10_WCD_A_DEM_BYPASS_DATA3__POR (0x00)
+#define MSM8X10_WCD_A_SPARE_0 (0x080)
+#define MSM8X10_WCD_A_SPARE_0__POR (0x00)
+#define MSM8X10_WCD_A_SPARE_1 (0x082)
+#define MSM8X10_WCD_A_SPARE_1__POR (0x00)
+#define MSM8X10_WCD_A_SPARE_2 (0x084)
+#define MSM8X10_WCD_A_SPARE_2__POR (0x00)
+#define MSM8X10_WCD_A_INTR_MODE (0x090)
+#define MSM8X10_WCD_A_INTR_MODE__POR (0x00)
+#define MSM8X10_WCD_A_INTR_MASK0 (0x094)
+#define MSM8X10_WCD_A_INTR_MASK0__POR (0xFF)
+#define MSM8X10_WCD_A_INTR_MASK1 (0x095)
+#define MSM8X10_WCD_A_INTR_MASK1__POR (0xFF)
+#define MSM8X10_WCD_A_INTR_MASK2 (0x096)
+#define MSM8X10_WCD_A_INTR_MASK2__POR (0x3F)
+#define MSM8X10_WCD_A_INTR_STATUS0 (0x098)
+#define MSM8X10_WCD_A_INTR_STATUS0__POR (0x00)
+#define MSM8X10_WCD_A_INTR_STATUS1 (0x099)
+#define MSM8X10_WCD_A_INTR_STATUS1__POR (0x00)
+#define MSM8X10_WCD_A_INTR_STATUS2 (0x09A)
+#define MSM8X10_WCD_A_INTR_STATUS2__POR (0x00)
+#define MSM8X10_WCD_A_INTR_CLEAR0 (0x09C)
+#define MSM8X10_WCD_A_INTR_CLEAR0__POR (0x00)
+#define MSM8X10_WCD_A_INTR_CLEAR1 (0x09D)
+#define MSM8X10_WCD_A_INTR_CLEAR1__POR (0x00)
+#define MSM8X10_WCD_A_INTR_CLEAR2 (0x09E)
+#define MSM8X10_WCD_A_INTR_CLEAR2__POR (0x00)
+#define MSM8X10_WCD_A_INTR_TEST0 (0x0A4)
+#define MSM8X10_WCD_A_INTR_TEST0__POR (0x00)
+#define MSM8X10_WCD_A_INTR_TEST1 (0x0A5)
+#define MSM8X10_WCD_A_INTR_TEST1__POR (0x00)
+#define MSM8X10_WCD_A_INTR_TEST2 (0x0A6)
+#define MSM8X10_WCD_A_INTR_TEST2__POR (0x00)
+#define MSM8X10_WCD_A_INTR_SET0 (0x0A8)
+#define MSM8X10_WCD_A_INTR_SET0__POR (0x00)
+#define MSM8X10_WCD_A_INTR_SET1 (0x0A9)
+#define MSM8X10_WCD_A_INTR_SET1__POR (0x00)
+#define MSM8X10_WCD_A_INTR_SET2 (0x0AA)
+#define MSM8X10_WCD_A_INTR_SET2__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_EN_CTL (0x0C0)
+#define MSM8X10_WCD_A_CDC_MBHC_EN_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG (0x0C1)
+#define MSM8X10_WCD_A_CDC_MBHC_FIR_B1_CFG__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG (0x0C2)
+#define MSM8X10_WCD_A_CDC_MBHC_FIR_B2_CFG__POR (0x06)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL (0x0C3)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL (0x0C4)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL (0x0C5)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL (0x0C6)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL (0x0C7)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL (0x0C8)
+#define MSM8X10_WCD_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78)
+#define MSM8X10_WCD_A_CDC_MBHC_B1_STATUS (0x0C9)
+#define MSM8X10_WCD_A_CDC_MBHC_B1_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_B2_STATUS (0x0CA)
+#define MSM8X10_WCD_A_CDC_MBHC_B2_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_B3_STATUS (0x0CB)
+#define MSM8X10_WCD_A_CDC_MBHC_B3_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_B4_STATUS (0x0CC)
+#define MSM8X10_WCD_A_CDC_MBHC_B4_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_B5_STATUS (0x0CD)
+#define MSM8X10_WCD_A_CDC_MBHC_B5_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_B1_CTL (0x0CE)
+#define MSM8X10_WCD_A_CDC_MBHC_B1_CTL__POR (0xC0)
+#define MSM8X10_WCD_A_CDC_MBHC_B2_CTL (0x0CF)
+#define MSM8X10_WCD_A_CDC_MBHC_B2_CTL__POR (0x5D)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL (0x0D0)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL (0x0D1)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL (0x0D2)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL (0x0D3)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL (0x0D4)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL (0x0D5)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL (0x0D6)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL (0x0D7)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL (0x0D8)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL (0x0D9)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL (0x0DA)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL (0x0DB)
+#define MSM8X10_WCD_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80)
+#define MSM8X10_WCD_A_CDC_MBHC_CLK_CTL (0x0DC)
+#define MSM8X10_WCD_A_CDC_MBHC_CLK_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_INT_CTL (0x0DD)
+#define MSM8X10_WCD_A_CDC_MBHC_INT_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL (0x0DE)
+#define MSM8X10_WCD_A_CDC_MBHC_DEBUG_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_MBHC_SPARE (0x0DF)
+#define MSM8X10_WCD_A_CDC_MBHC_SPARE__POR (0x00)
+#define MSM8X10_WCD_A_BIAS_REF_CTL (0x100)
+#define MSM8X10_WCD_A_BIAS_REF_CTL__POR (0x1C)
+#define MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL (0x101)
+#define MSM8X10_WCD_A_BIAS_CENTRAL_BG_CTL__POR (0x50)
+#define MSM8X10_WCD_A_BIAS_PRECHRG_CTL (0x102)
+#define MSM8X10_WCD_A_BIAS_PRECHRG_CTL__POR (0x07)
+#define MSM8X10_WCD_A_BIAS_CURR_CTL_1 (0x103)
+#define MSM8X10_WCD_A_BIAS_CURR_CTL_1__POR (0x52)
+#define MSM8X10_WCD_A_BIAS_CURR_CTL_2 (0x104)
+#define MSM8X10_WCD_A_BIAS_CURR_CTL_2__POR (0x00)
+#define MSM8X10_WCD_A_BIAS_OSC_BG_CTL (0x105)
+#define MSM8X10_WCD_A_BIAS_OSC_BG_CTL__POR (0x16)
+#define MSM8X10_WCD_A_MICB_CFILT_1_CTL (0x128)
+#define MSM8X10_WCD_A_MICB_CFILT_1_CTL__POR (0x40)
+#define MSM8X10_WCD_A_MICB_CFILT_1_VAL (0x129)
+#define MSM8X10_WCD_A_MICB_CFILT_1_VAL__POR (0x80)
+#define MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG (0x12A)
+#define MSM8X10_WCD_A_MICB_CFILT_1_PRECHRG__POR (0x00)
+#define MSM8X10_WCD_A_MICB_1_CTL (0x12B)
+#define MSM8X10_WCD_A_MICB_1_CTL__POR (0x02)
+#define MSM8X10_WCD_A_MICB_1_INT_RBIAS (0x12C)
+#define MSM8X10_WCD_A_MICB_1_INT_RBIAS__POR (0x00)
+#define MSM8X10_WCD_A_MICB_1_MBHC (0x12D)
+#define MSM8X10_WCD_A_MICB_1_MBHC__POR (0x00)
+#define MSM8X10_WCD_A_MBHC_INSERT_DETECT (0x14A)
+#define MSM8X10_WCD_A_MBHC_INSERT_DETECT__POR (0x00)
+#define MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS (0x14B)
+#define MSM8X10_WCD_A_MBHC_INSERT_DET_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_TX_COM_BIAS (0x14C)
+#define MSM8X10_WCD_A_TX_COM_BIAS__POR (0xF0)
+#define MSM8X10_WCD_A_MBHC_SCALING_MUX_1 (0x14E)
+#define MSM8X10_WCD_A_MBHC_SCALING_MUX_1__POR (0x00)
+#define MSM8X10_WCD_A_MBHC_SCALING_MUX_2 (0x14F)
+#define MSM8X10_WCD_A_MBHC_SCALING_MUX_2__POR (0x80)
+#define MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL (0x150)
+#define MSM8X10_WCD_A_RESERVED_MAD_ANA_CTRL__POR (0xF1)
+#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1 (0x151)
+#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_1__POR (0x00)
+#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2 (0x152)
+#define MSM8X10_WCD_A_TX_SUP_SWITCH_CTRL_2__POR (0x80)
+#define MSM8X10_WCD_A_TX_1_EN (0x153)
+#define MSM8X10_WCD_A_TX_1_EN__POR (0x02)
+#define MSM8X10_WCD_A_TX_2_EN (0x154)
+#define MSM8X10_WCD_A_TX_2_EN__POR (0x02)
+#define MSM8X10_WCD_A_TX_1_2_ADC_CH1 (0x155)
+#define MSM8X10_WCD_A_TX_1_2_ADC_CH1__POR (0x44)
+#define MSM8X10_WCD_A_TX_1_2_ADC_CH2 (0x156)
+#define MSM8X10_WCD_A_TX_1_2_ADC_CH2__POR (0x44)
+#define MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL (0x157)
+#define MSM8X10_WCD_A_TX_1_2_ATEST_REFCTRL__POR (0x00)
+#define MSM8X10_WCD_A_TX_1_2_TEST_CTL (0x158)
+#define MSM8X10_WCD_A_TX_1_2_TEST_CTL__POR (0x38)
+#define MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN (0x159)
+#define MSM8X10_WCD_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC)
+#define MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV (0x15A)
+#define MSM8X10_WCD_A_TX_1_2_TXFE_CLKDIV__POR (0x55)
+#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1 (0x15B)
+#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH1__POR (0x00)
+#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2 (0x15C)
+#define MSM8X10_WCD_A_TX_1_2_SAR_ERR_CH2__POR (0x00)
+#define MSM8X10_WCD_A_TX_3_EN (0x15D)
+#define MSM8X10_WCD_A_TX_3_EN__POR (0x00)
+#define MSM8X10_WCD_A_TX_1_2_TEST_EN (0x15E)
+#define MSM8X10_WCD_A_TX_1_2_TEST_EN__POR (0xCC)
+#define MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL (0x171)
+#define MSM8X10_WCD_A_TX_7_MBHC_EN_ATEST_CTRL__POR (0x10)
+#define MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR (0x175)
+#define MSM8X10_WCD_A_TX_7_MBHC_SAR_ERR__POR (0x00)
+#define MSM8X10_WCD_A_CP_EN (0x192)
+#define MSM8X10_WCD_A_CP_EN__POR (0xE6)
+#define MSM8X10_WCD_A_CP_CLK (0x193)
+#define MSM8X10_WCD_A_CP_CLK__POR (0x29)
+#define MSM8X10_WCD_A_CP_STATIC (0x194)
+#define MSM8X10_WCD_A_CP_STATIC__POR (0x10)
+#define MSM8X10_WCD_A_CP_DCC1 (0x195)
+#define MSM8X10_WCD_A_CP_DCC1__POR (0x52)
+#define MSM8X10_WCD_A_CP_DCC3 (0x196)
+#define MSM8X10_WCD_A_CP_DCC3__POR (0x01)
+#define MSM8X10_WCD_A_CP_ATEST (0x197)
+#define MSM8X10_WCD_A_CP_ATEST__POR (0x00)
+#define MSM8X10_WCD_A_CP_DTEST (0x198)
+#define MSM8X10_WCD_A_CP_DTEST__POR (0x00)
+#define MSM8X10_WCD_A_RX_AUX_SW_CTL (0x19B)
+#define MSM8X10_WCD_A_RX_AUX_SW_CTL__POR (0x00)
+#define MSM8X10_WCD_A_RX_PA_AUX_IN_CONN (0x19C)
+#define MSM8X10_WCD_A_RX_PA_AUX_IN_CONN__POR (0x00)
+#define MSM8X10_WCD_A_RX_COM_TIMER_DIV (0x19E)
+#define MSM8X10_WCD_A_RX_COM_TIMER_DIV__POR (0xE8)
+#define MSM8X10_WCD_A_RX_COM_OCP_CTL (0x19F)
+#define MSM8X10_WCD_A_RX_COM_OCP_CTL__POR (0x1F)
+#define MSM8X10_WCD_A_RX_COM_OCP_COUNT (0x1A0)
+#define MSM8X10_WCD_A_RX_COM_OCP_COUNT__POR (0x77)
+#define MSM8X10_WCD_A_RX_COM_DAC_CTL (0x1A1)
+#define MSM8X10_WCD_A_RX_COM_DAC_CTL__POR (0x00)
+#define MSM8X10_WCD_A_RX_COM_BIAS (0x1A2)
+#define MSM8X10_WCD_A_RX_COM_BIAS__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_AUTO_CHOP (0x1A4)
+#define MSM8X10_WCD_A_RX_HPH_AUTO_CHOP__POR (0x38)
+#define MSM8X10_WCD_A_RX_HPH_CHOP_CTL (0x1A5)
+#define MSM8X10_WCD_A_RX_HPH_CHOP_CTL__POR (0x34)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_PA (0x1A6)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_PA__POR (0x5A)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_LDO (0x1A7)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_LDO__POR (0x87)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_CNP (0x1A8)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_CNP__POR (0x8A)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP (0x1A9)
+#define MSM8X10_WCD_A_RX_HPH_BIAS_WG_OCP__POR (0x2A)
+#define MSM8X10_WCD_A_RX_HPH_OCP_CTL (0x1AA)
+#define MSM8X10_WCD_A_RX_HPH_OCP_CTL__POR (0x69)
+#define MSM8X10_WCD_A_RX_HPH_CNP_EN (0x1AB)
+#define MSM8X10_WCD_A_RX_HPH_CNP_EN__POR (0x80)
+#define MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL (0x1AC)
+#define MSM8X10_WCD_A_RX_HPH_CNP_WG_CTL__POR (0xDE)
+#define MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME (0x1AD)
+#define MSM8X10_WCD_A_RX_HPH_CNP_WG_TIME__POR (0x15)
+#define MSM8X10_WCD_A_RX_HPH_L_GAIN (0x1AE)
+#define MSM8X10_WCD_A_RX_HPH_L_GAIN__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_L_TEST (0x1AF)
+#define MSM8X10_WCD_A_RX_HPH_L_TEST__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_L_PA_CTL (0x1B0)
+#define MSM8X10_WCD_A_RX_HPH_L_PA_CTL__POR (0x40)
+#define MSM8X10_WCD_A_RX_HPH_L_DAC_CTL (0x1B1)
+#define MSM8X10_WCD_A_RX_HPH_L_DAC_CTL__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_L_ATEST (0x1B2)
+#define MSM8X10_WCD_A_RX_HPH_L_ATEST__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_L_STATUS (0x1B3)
+#define MSM8X10_WCD_A_RX_HPH_L_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_R_GAIN (0x1B4)
+#define MSM8X10_WCD_A_RX_HPH_R_GAIN__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_R_TEST (0x1B5)
+#define MSM8X10_WCD_A_RX_HPH_R_TEST__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_R_PA_CTL (0x1B6)
+#define MSM8X10_WCD_A_RX_HPH_R_PA_CTL__POR (0x40)
+#define MSM8X10_WCD_A_RX_HPH_R_DAC_CTL (0x1B7)
+#define MSM8X10_WCD_A_RX_HPH_R_DAC_CTL__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_R_ATEST (0x1B8)
+#define MSM8X10_WCD_A_RX_HPH_R_ATEST__POR (0x00)
+#define MSM8X10_WCD_A_RX_HPH_R_STATUS (0x1B9)
+#define MSM8X10_WCD_A_RX_HPH_R_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_RX_EAR_BIAS_PA (0x1BA)
+#define MSM8X10_WCD_A_RX_EAR_BIAS_PA__POR (0x56)
+#define MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF (0x1BB)
+#define MSM8X10_WCD_A_RX_EAR_BIAS_CMBUFF__POR (0xA0)
+#define MSM8X10_WCD_A_RX_EAR_EN (0x1BC)
+#define MSM8X10_WCD_A_RX_EAR_EN__POR (0x00)
+#define MSM8X10_WCD_A_RX_EAR_GAIN (0x1BD)
+#define MSM8X10_WCD_A_RX_EAR_GAIN__POR (0x02)
+#define MSM8X10_WCD_A_RX_EAR_CMBUFF (0x1BE)
+#define MSM8X10_WCD_A_RX_EAR_CMBUFF__POR (0x05)
+#define MSM8X10_WCD_A_RX_EAR_ICTL (0x1BF)
+#define MSM8X10_WCD_A_RX_EAR_ICTL__POR (0x40)
+#define MSM8X10_WCD_A_RX_EAR_CCOMP (0x1C0)
+#define MSM8X10_WCD_A_RX_EAR_CCOMP__POR (0x08)
+#define MSM8X10_WCD_A_RX_EAR_VCM (0x1C1)
+#define MSM8X10_WCD_A_RX_EAR_VCM__POR (0x03)
+#define MSM8X10_WCD_A_RX_EAR_CNP (0x1C2)
+#define MSM8X10_WCD_A_RX_EAR_CNP__POR (0xF2)
+#define MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST (0x1C3)
+#define MSM8X10_WCD_A_RX_EAR_DAC_CTL_ATEST__POR (0x00)
+#define MSM8X10_WCD_A_RX_EAR_STATUS (0x1C5)
+#define MSM8X10_WCD_A_RX_EAR_STATUS__POR (0x04)
+#define MSM8X10_WCD_A_RX_LINE_BIAS_PA (0x1C6)
+#define MSM8X10_WCD_A_RX_LINE_BIAS_PA__POR (0x58)
+#define MSM8X10_WCD_A_RX_BUCK_BIAS1 (0x1C7)
+#define MSM8X10_WCD_A_RX_BUCK_BIAS1__POR (0x42)
+#define MSM8X10_WCD_A_RX_BUCK_BIAS2 (0x1C8)
+#define MSM8X10_WCD_A_RX_BUCK_BIAS2__POR (0x84)
+#define MSM8X10_WCD_A_RX_LINE_COM (0x1C9)
+#define MSM8X10_WCD_A_RX_LINE_COM__POR (0x80)
+#define MSM8X10_WCD_A_RX_LINE_CNP_EN (0x1CA)
+#define MSM8X10_WCD_A_RX_LINE_CNP_EN__POR (0x00)
+#define MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL (0x1CB)
+#define MSM8X10_WCD_A_RX_LINE_CNP_WG_CTL__POR (0x00)
+#define MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME (0x1CC)
+#define MSM8X10_WCD_A_RX_LINE_CNP_WG_TIME__POR (0x04)
+#define MSM8X10_WCD_A_RX_LINE_1_GAIN (0x1CD)
+#define MSM8X10_WCD_A_RX_LINE_1_GAIN__POR (0x00)
+#define MSM8X10_WCD_A_RX_LINE_1_TEST (0x1CE)
+#define MSM8X10_WCD_A_RX_LINE_1_TEST__POR (0x00)
+#define MSM8X10_WCD_A_RX_LINE_1_DAC_CTL (0x1CF)
+#define MSM8X10_WCD_A_RX_LINE_1_DAC_CTL__POR (0x00)
+#define MSM8X10_WCD_A_RX_LINE_1_STATUS (0x1D0)
+#define MSM8X10_WCD_A_RX_LINE_1_STATUS__POR (0x00)
+#define MSM8X10_WCD_A_RX_LINE_CNP_DBG (0x1DD)
+#define MSM8X10_WCD_A_RX_LINE_CNP_DBG__POR (0x00)
+#define MSM8X10_WCD_A_SPKR_DRV_EN (0x1DF)
+#define MSM8X10_WCD_A_SPKR_DRV_EN__POR (0x6F)
+#define MSM8X10_WCD_A_SPKR_DRV_GAIN (0x1E0)
+#define MSM8X10_WCD_A_SPKR_DRV_GAIN__POR (0x00)
+#define MSM8X10_WCD_A_SPKR_DRV_DAC_CTL (0x1E1)
+#define MSM8X10_WCD_A_SPKR_DRV_DAC_CTL__POR (0x04)
+#define MSM8X10_WCD_A_SPKR_DRV_OCP_CTL (0x1E2)
+#define MSM8X10_WCD_A_SPKR_DRV_OCP_CTL__POR (0x98)
+#define MSM8X10_WCD_A_SPKR_DRV_CLIP_DET (0x1E3)
+#define MSM8X10_WCD_A_SPKR_DRV_CLIP_DET__POR (0x01)
+#define MSM8X10_WCD_A_SPKR_DRV_IEC (0x1E4)
+#define MSM8X10_WCD_A_SPKR_DRV_IEC__POR (0x00)
+#define MSM8X10_WCD_A_SPKR_DRV_DBG_DAC (0x1E5)
+#define MSM8X10_WCD_A_SPKR_DRV_DBG_DAC__POR (0x05)
+#define MSM8X10_WCD_A_SPKR_DRV_DBG_PA (0x1E6)
+#define MSM8X10_WCD_A_SPKR_DRV_DBG_PA__POR (0x18)
+#define MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG (0x1E7)
+#define MSM8X10_WCD_A_SPKR_DRV_DBG_PWRSTG__POR (0x00)
+#define MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO (0x1E8)
+#define MSM8X10_WCD_A_SPKR_DRV_BIAS_LDO__POR (0x45)
+#define MSM8X10_WCD_A_SPKR_DRV_BIAS_INT (0x1E9)
+#define MSM8X10_WCD_A_SPKR_DRV_BIAS_INT__POR (0xA5)
+#define MSM8X10_WCD_A_SPKR_DRV_BIAS_PA (0x1EA)
+#define MSM8X10_WCD_A_SPKR_DRV_BIAS_PA__POR (0x55)
+#define MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP (0x1EB)
+#define MSM8X10_WCD_A_SPKR_DRV_STATUS_OCP__POR (0x00)
+#define MSM8X10_WCD_A_SPKR_DRV_STATUS_PA (0x1EC)
+#define MSM8X10_WCD_A_SPKR_DRV_STATUS_PA__POR (0x00)
+#define MSM8X10_WCD_A_RC_OSC_FREQ (0x1FA)
+#define MSM8X10_WCD_A_RC_OSC_FREQ__POR (0x46)
+#define MSM8X10_WCD_A_RC_OSC_TEST (0x1FB)
+#define MSM8X10_WCD_A_RC_OSC_TEST__POR (0x0A)
+#define MSM8X10_WCD_A_RC_OSC_STATUS (0x1FC)
+#define MSM8X10_WCD_A_RC_OSC_STATUS__POR (0x18)
+#define MSM8X10_WCD_A_RC_OSC_TUNER (0x1FD)
+#define MSM8X10_WCD_A_RC_OSC_TUNER__POR (0x00)
+#define MSM8X10_WCD_A_MBHC_HPH (0x1FE)
+#define MSM8X10_WCD_A_MBHC_HPH__POR (0x44)
+#define MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL (0x400)
+#define MSM8X10_WCD_A_CDC_CLK_RX_RESET_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL (0x404)
+#define MSM8X10_WCD_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL (0x408)
+#define MSM8X10_WCD_A_CDC_CLK_DMIC_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL (0x40C)
+#define MSM8X10_WCD_A_CDC_CLK_RX_I2S_CTL__POR (0x10)
+#define MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL (0x410)
+#define MSM8X10_WCD_A_CDC_CLK_TX_I2S_CTL__POR (0x10)
+#define MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL (0x414)
+#define MSM8X10_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x418)
+#define MSM8X10_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_OTHR_CTL (0x41C)
+#define MSM8X10_WCD_A_CDC_CLK_OTHR_CTL__POR (0x04)
+#define MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL (0x420)
+#define MSM8X10_WCD_A_CDC_CLK_RX_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_MCLK_CTL (0x424)
+#define MSM8X10_WCD_A_CDC_CLK_MCLK_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_PDM_CTL (0x428)
+#define MSM8X10_WCD_A_CDC_CLK_PDM_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLK_SD_CTL (0x42C)
+#define MSM8X10_WCD_A_CDC_CLK_SD_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_B1_CTL (0x440)
+#define MSM8X10_WCD_A_CDC_RX1_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX2_B1_CTL (0x460)
+#define MSM8X10_WCD_A_CDC_RX2_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX3_B1_CTL (0x480)
+#define MSM8X10_WCD_A_CDC_RX3_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_B2_CTL (0x444)
+#define MSM8X10_WCD_A_CDC_RX1_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX2_B2_CTL (0x464)
+#define MSM8X10_WCD_A_CDC_RX2_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX3_B2_CTL (0x484)
+#define MSM8X10_WCD_A_CDC_RX3_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_B3_CTL (0x448)
+#define MSM8X10_WCD_A_CDC_RX1_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX2_B3_CTL (0x468)
+#define MSM8X10_WCD_A_CDC_RX2_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX3_B3_CTL (0x488)
+#define MSM8X10_WCD_A_CDC_RX3_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_B4_CTL (0x44C)
+#define MSM8X10_WCD_A_CDC_RX1_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX2_B4_CTL (0x46C)
+#define MSM8X10_WCD_A_CDC_RX2_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX3_B4_CTL (0x48C)
+#define MSM8X10_WCD_A_CDC_RX3_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_B5_CTL (0x450)
+#define MSM8X10_WCD_A_CDC_RX1_B5_CTL__POR (0x68)
+#define MSM8X10_WCD_A_CDC_RX2_B5_CTL (0x470)
+#define MSM8X10_WCD_A_CDC_RX2_B5_CTL__POR (0x68)
+#define MSM8X10_WCD_A_CDC_RX3_B5_CTL (0x490)
+#define MSM8X10_WCD_A_CDC_RX3_B5_CTL__POR (0x68)
+#define MSM8X10_WCD_A_CDC_RX1_B6_CTL (0x454)
+#define MSM8X10_WCD_A_CDC_RX1_B6_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX2_B6_CTL (0x474)
+#define MSM8X10_WCD_A_CDC_RX2_B6_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX3_B6_CTL (0x494)
+#define MSM8X10_WCD_A_CDC_RX3_B6_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL (0x458)
+#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL (0x478)
+#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL (0x498)
+#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL (0x45C)
+#define MSM8X10_WCD_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL (0x47C)
+#define MSM8X10_WCD_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL (0x49C)
+#define MSM8X10_WCD_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x4A0)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x07)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x4A4)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x13)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x4A8)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x1B)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x4AC)
+#define MSM8X10_WCD_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x7F)
+#define MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL (0x4B0)
+#define MSM8X10_WCD_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x26)
+#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG (0x4B4)
+#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0A)
+#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG (0x4B8)
+#define MSM8X10_WCD_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CLSG_CTL (0x4BC)
+#define MSM8X10_WCD_A_CDC_CLSG_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER (0x4C0)
+#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER (0x4E0)
+#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN (0x4C4)
+#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN (0x4E4)
+#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG (0x4C8)
+#define MSM8X10_WCD_A_CDC_TX1_VOL_CTL_CFG__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG (0x4E8)
+#define MSM8X10_WCD_A_CDC_TX2_VOL_CTL_CFG__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX1_MUX_CTL (0x4CC)
+#define MSM8X10_WCD_A_CDC_TX1_MUX_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX2_MUX_CTL (0x4EC)
+#define MSM8X10_WCD_A_CDC_TX2_MUX_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL (0x4D0)
+#define MSM8X10_WCD_A_CDC_TX1_CLK_FS_CTL__POR (0x03)
+#define MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL (0x4F0)
+#define MSM8X10_WCD_A_CDC_TX2_CLK_FS_CTL__POR (0x03)
+#define MSM8X10_WCD_A_CDC_TX1_DMIC_CTL (0x4D4)
+#define MSM8X10_WCD_A_CDC_TX1_DMIC_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TX2_DMIC_CTL (0x4F4)
+#define MSM8X10_WCD_A_CDC_TX2_DMIC_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL (0x500)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL (0x540)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL (0x504)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL (0x544)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL (0x508)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL (0x548)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL (0x50C)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL (0x54C)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL (0x510)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL (0x550)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL (0x514)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL (0x554)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL (0x518)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL (0x558)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL (0x51C)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL (0x55C)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_CTL (0x520)
+#define MSM8X10_WCD_A_CDC_IIR1_CTL__POR (0x40)
+#define MSM8X10_WCD_A_CDC_IIR2_CTL (0x560)
+#define MSM8X10_WCD_A_CDC_IIR2_CTL__POR (0x40)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL (0x524)
+#define MSM8X10_WCD_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL (0x564)
+#define MSM8X10_WCD_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL (0x528)
+#define MSM8X10_WCD_A_CDC_IIR1_COEF_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL (0x568)
+#define MSM8X10_WCD_A_CDC_IIR2_COEF_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL (0x52C)
+#define MSM8X10_WCD_A_CDC_IIR1_COEF_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL (0x56C)
+#define MSM8X10_WCD_A_CDC_IIR2_COEF_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL (0x580)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL (0x584)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL (0x588)
+#define MSM8X10_WCD_A_CDC_CONN_RX1_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL (0x58C)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL (0x590)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL (0x594)
+#define MSM8X10_WCD_A_CDC_CONN_RX2_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL (0x598)
+#define MSM8X10_WCD_A_CDC_CONN_RX3_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL (0x59C)
+#define MSM8X10_WCD_A_CDC_CONN_RX3_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL (0x5A4)
+#define MSM8X10_WCD_A_CDC_CONN_TX_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL (0x5A8)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL (0x5AC)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL (0x5B0)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL (0x5B4)
+#define MSM8X10_WCD_A_CDC_CONN_EQ1_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL (0x5B8)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL (0x5BC)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL (0x5C0)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B3_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL (0x5C4)
+#define MSM8X10_WCD_A_CDC_CONN_EQ2_B4_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL (0x5C8)
+#define MSM8X10_WCD_A_CDC_CONN_TX_I2S_SD1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE (0x5D0)
+#define MSM8X10_WCD_A_CDC_TOP_GAIN_UPDATE__POR (0x00)
+#define MSM8X10_WCD_A_CDC_TOP_CTL (0x5D8)
+#define MSM8X10_WCD_A_CDC_TOP_CTL__POR (0x01)
+#define MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL (0x5E0)
+#define MSM8X10_WCD_A_CDC_DEBUG_DESER1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL (0x5E4)
+#define MSM8X10_WCD_A_CDC_DEBUG_DESER2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_DEBUG_B1_CTL (0x5E8)
+#define MSM8X10_WCD_A_CDC_DEBUG_B1_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_DEBUG_B2_CTL (0x5EC)
+#define MSM8X10_WCD_A_CDC_DEBUG_B2_CTL__POR (0x00)
+#define MSM8X10_WCD_A_CDC_DEBUG_B3_CTL (0x5F0)
+#define MSM8X10_WCD_A_CDC_DEBUG_B3_CTL__POR (0x00)
+#endif
diff --git a/sound/soc/msm/msm-pcm-voip.c b/sound/soc/msm/msm-pcm-voip.c
index 41e4c60..22bc9e1 100644
--- a/sound/soc/msm/msm-pcm-voip.c
+++ b/sound/soc/msm/msm-pcm-voip.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -155,7 +155,8 @@
};
static int voip_get_media_type(uint32_t mode, uint32_t rate_type,
- unsigned int samp_rate);
+ unsigned int samp_rate,
+ uint32_t *media_type);
static int voip_get_rate_type(uint32_t mode,
uint32_t rate,
uint32_t *rate_type);
@@ -934,12 +935,12 @@
goto done;
}
prtd->rate_type = rate_type;
- media_type = voip_get_media_type(prtd->mode,
- prtd->rate_type,
- prtd->play_samp_rate);
- if (media_type < 0) {
+ ret = voip_get_media_type(prtd->mode,
+ prtd->rate_type,
+ prtd->play_samp_rate,
+ &media_type);
+ if (ret < 0) {
pr_err("fail at getting media_type\n");
- ret = -EINVAL;
goto done;
}
pr_debug(" media_type=%d, rate_type=%d\n", media_type,
@@ -1210,49 +1211,50 @@
}
static int voip_get_media_type(uint32_t mode, uint32_t rate_type,
- unsigned int samp_rate)
+ unsigned int samp_rate,
+ uint32_t *media_type)
{
- uint32_t media_type;
+ int ret = 0;
pr_debug("%s: mode=%d, samp_rate=%d\n", __func__,
mode, samp_rate);
switch (mode) {
case MODE_AMR:
- media_type = VSS_MEDIA_ID_AMR_NB_MODEM;
+ *media_type = VSS_MEDIA_ID_AMR_NB_MODEM;
break;
case MODE_AMR_WB:
- media_type = VSS_MEDIA_ID_AMR_WB_MODEM;
+ *media_type = VSS_MEDIA_ID_AMR_WB_MODEM;
break;
case MODE_PCM:
if (samp_rate == 8000)
- media_type = VSS_MEDIA_ID_PCM_NB;
+ *media_type = VSS_MEDIA_ID_PCM_NB;
else
- media_type = VSS_MEDIA_ID_PCM_WB;
+ *media_type = VSS_MEDIA_ID_PCM_WB;
break;
case MODE_IS127: /* EVRC-A */
- media_type = VSS_MEDIA_ID_EVRC_MODEM;
+ *media_type = VSS_MEDIA_ID_EVRC_MODEM;
break;
case MODE_4GV_NB: /* EVRC-B */
- media_type = VSS_MEDIA_ID_4GV_NB_MODEM;
+ *media_type = VSS_MEDIA_ID_4GV_NB_MODEM;
break;
case MODE_4GV_WB: /* EVRC-WB */
- media_type = VSS_MEDIA_ID_4GV_WB_MODEM;
+ *media_type = VSS_MEDIA_ID_4GV_WB_MODEM;
break;
case MODE_G711:
case MODE_G711A:
if (rate_type == MVS_G711A_MODE_MULAW)
- media_type = VSS_MEDIA_ID_G711_MULAW;
+ *media_type = VSS_MEDIA_ID_G711_MULAW;
else
- media_type = VSS_MEDIA_ID_G711_ALAW;
+ *media_type = VSS_MEDIA_ID_G711_ALAW;
break;
default:
pr_debug(" input mode is not supported\n");
- media_type = -EINVAL;
+ ret = -EINVAL;
}
- pr_debug("%s: media_type is 0x%x\n", __func__, media_type);
+ pr_debug("%s: media_type is 0x%x\n", __func__, *media_type);
- return media_type;
+ return ret;
}
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-voip-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-voip-v2.c
index 49f1d70..b5ce28f 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-voip-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-voip-v2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -140,7 +140,8 @@
};
static int voip_get_media_type(uint32_t mode,
- unsigned int samp_rate);
+ unsigned int samp_rate,
+ unsigned int *media_type);
static int voip_get_rate_type(uint32_t mode,
uint32_t rate,
uint32_t *rate_type);
@@ -782,11 +783,11 @@
goto done;
}
prtd->rate_type = rate_type;
- media_type = voip_get_media_type(prtd->mode,
- prtd->play_samp_rate);
- if (media_type < 0) {
+ ret = voip_get_media_type(prtd->mode,
+ prtd->play_samp_rate,
+ &media_type);
+ if (ret < 0) {
pr_err("fail at getting media_type\n");
- ret = -EINVAL;
goto done;
}
pr_debug(" media_type=%d, rate_type=%d\n", media_type,
@@ -1058,42 +1059,43 @@
}
static int voip_get_media_type(uint32_t mode,
- unsigned int samp_rate)
+ unsigned int samp_rate,
+ unsigned int *media_type)
{
- uint32_t media_type;
+ int ret = 0;
pr_debug("%s: mode=%d, samp_rate=%d\n", __func__,
mode, samp_rate);
switch (mode) {
case MODE_AMR:
- media_type = VSS_MEDIA_ID_AMR_NB_MODEM;
+ *media_type = VSS_MEDIA_ID_AMR_NB_MODEM;
break;
case MODE_AMR_WB:
- media_type = VSS_MEDIA_ID_AMR_WB_MODEM;
+ *media_type = VSS_MEDIA_ID_AMR_WB_MODEM;
break;
case MODE_PCM:
if (samp_rate == 8000)
- media_type = VSS_MEDIA_ID_PCM_NB;
+ *media_type = VSS_MEDIA_ID_PCM_NB;
else
- media_type = VSS_MEDIA_ID_PCM_WB;
+ *media_type = VSS_MEDIA_ID_PCM_WB;
break;
case MODE_IS127: /* EVRC-A */
- media_type = VSS_MEDIA_ID_EVRC_MODEM;
+ *media_type = VSS_MEDIA_ID_EVRC_MODEM;
break;
case MODE_4GV_NB: /* EVRC-B */
- media_type = VSS_MEDIA_ID_4GV_NB_MODEM;
+ *media_type = VSS_MEDIA_ID_4GV_NB_MODEM;
break;
case MODE_4GV_WB: /* EVRC-WB */
- media_type = VSS_MEDIA_ID_4GV_WB_MODEM;
+ *media_type = VSS_MEDIA_ID_4GV_WB_MODEM;
break;
default:
pr_debug(" input mode is not supported\n");
- media_type = -EINVAL;
+ ret = -EINVAL;
}
- pr_debug("%s: media_type is 0x%x\n", __func__, media_type);
+ pr_debug("%s: media_type is 0x%x\n", __func__, *media_type);
- return media_type;
+ return ret;
}