[MIPS] MT: Scheduler support for SMT
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index ed5c02c..0c5a358 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -55,6 +55,7 @@
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
+ int core; /* physical core number */
#if defined(CONFIG_MIPS_MT_SMTC)
/*
* In the MIPS MT "SMTC" model, each TC is considered
@@ -63,8 +64,10 @@
* to all TCs within the same VPE.
*/
int vpe_id; /* Virtual Processor number */
- int tc_id; /* Thread Context number */
#endif /* CONFIG_MIPS_MT */
+#ifdef CONFIG_MIPS_MT_SMTC
+ int tc_id; /* Thread Context number */
+#endif
void *data; /* Additional data */
} __attribute__((aligned(SMP_CACHE_BYTES)));