msm: kgsl: Rearrange some drawctxt functions
Move some of the drawctxt functions that are common
to A2XX and A3XX back to the generic drawctxt code
and headers.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index cd99302..3aa601c 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -244,25 +244,6 @@
1 << 9 /* Mip Address[31:12] = TBD */
};
-/* quad for copying GMEM to context shadow */
-#define QUAD_LEN 12
-
-static unsigned int gmem_copy_quad[QUAD_LEN] = {
- 0x00000000, 0x00000000, 0x3f800000,
- 0x00000000, 0x00000000, 0x3f800000,
- 0x00000000, 0x00000000, 0x3f800000,
- 0x00000000, 0x00000000, 0x3f800000
-};
-
-#define TEXCOORD_LEN 8
-
-static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = {
- 0x00000000, 0x3f800000,
- 0x3f800000, 0x3f800000,
- 0x00000000, 0x00000000,
- 0x3f800000, 0x00000000
-};
-
#define NUM_COLOR_FORMATS 13
static enum SURFACEFORMAT surface_format_table[NUM_COLOR_FORMATS] = {
@@ -300,32 +281,6 @@
/* shader linkage info */
#define SHADER_CONST_ADDR (11 * 6 + 3)
-/* gmem command buffer length */
-#define PM4_REG(reg) ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg)))
-
-/* functions */
-static void config_gmemsize(struct gmem_shadow_t *shadow, int gmem_size)
-{
- int w = 64, h = 64; /* 16KB surface, minimum */
-
- shadow->format = COLORX_8_8_8_8;
- /* convert from bytes to 32-bit words */
- gmem_size = (gmem_size + 3) / 4;
-
- /* find the right surface size, close to a square. */
- while (w * h < gmem_size)
- if (w < h)
- w *= 2;
- else
- h *= 2;
-
- shadow->width = w;
- shadow->pitch = w;
- shadow->height = h;
- shadow->gmem_pitch = shadow->pitch;
-
- shadow->size = shadow->pitch * shadow->height * 4;
-}
static unsigned int *program_shader(unsigned int *cmds, int vtxfrag,
unsigned int *shader_pgm, int dwords)
@@ -606,17 +561,17 @@
*cmds++ = 0x1;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
- *cmds++ = PM4_REG(REG_VGT_MAX_VTX_INDX);
+ *cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX);
*cmds++ = 0x00ffffff; /* REG_VGT_MAX_VTX_INDX */
*cmds++ = 0x0; /* REG_VGT_MIN_VTX_INDX */
*cmds++ = 0x00000000; /* REG_VGT_INDX_OFFSET */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_SC_AA_MASK);
+ *cmds++ = CP_REG(REG_PA_SC_AA_MASK);
*cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_COLORCONTROL);
+ *cmds++ = CP_REG(REG_RB_COLORCONTROL);
*cmds++ = 0x00000c20;
/* Repartition shaders */
@@ -639,7 +594,7 @@
/* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_SQ_PROGRAM_CNTL);
+ *cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x10018001;
else
@@ -650,13 +605,13 @@
/* PA_CL_VTE_CNTL */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_CL_VTE_CNTL);
+ *cmds++ = CP_REG(REG_PA_CL_VTE_CNTL);
/* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */
*cmds++ = 0x00000b00;
/* program surface info */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_RB_SURFACE_INFO);
+ *cmds++ = CP_REG(REG_RB_SURFACE_INFO);
*cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */
/* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0,
@@ -670,7 +625,7 @@
/* disable Z */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_DEPTHCONTROL);
+ *cmds++ = CP_REG(REG_RB_DEPTHCONTROL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 0x08;
else
@@ -682,17 +637,17 @@
* Provoking vertex = last
*/
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_SU_SC_MODE_CNTL);
+ *cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL);
*cmds++ = 0x00080240;
/* Use maximum scissor values -- quad vertices already have the
* correct bounds */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
+ *cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
*cmds++ = (0 << 16) | 0;
*cmds++ = (0x1fff << 16) | (0x1fff);
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
+ *cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
*cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0);
*cmds++ = (0x1fff << 16) | (0x1fff);
@@ -700,20 +655,20 @@
* z offset = 0.0f
*/
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_PA_CL_VPORT_ZSCALE);
+ *cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE);
*cmds++ = 0xbf800000; /* -1.0f */
*cmds++ = 0x0;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_COLOR_MASK);
+ *cmds++ = CP_REG(REG_RB_COLOR_MASK);
*cmds++ = 0x0000000f; /* R = G = B = 1:enabled */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_COLOR_DEST_MASK);
+ *cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK);
*cmds++ = 0xffffffff;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_SQ_WRAPPING_0);
+ *cmds++ = CP_REG(REG_SQ_WRAPPING_0);
*cmds++ = 0x00000000;
*cmds++ = 0x00000000;
@@ -723,7 +678,7 @@
/* load the COPY state */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 6);
- *cmds++ = PM4_REG(REG_RB_COPY_CONTROL);
+ *cmds++ = CP_REG(REG_RB_COPY_CONTROL);
*cmds++ = 0; /* RB_COPY_CONTROL */
*cmds++ = addr & 0xfffff000; /* RB_COPY_DEST_BASE */
*cmds++ = shadow->pitch >> 5; /* RB_COPY_DEST_PITCH */
@@ -738,11 +693,11 @@
*cmds++ = offset;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_MODECONTROL);
+ *cmds++ = CP_REG(REG_RB_MODECONTROL);
*cmds++ = 0x6; /* EDRAM copy */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_CL_CLIP_CNTL);
+ *cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
if (adreno_is_a22x(adreno_dev)) {
@@ -750,7 +705,7 @@
*cmds++ = 0;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_LEIA_RB_LRZ_VSC_CONTROL);
+ *cmds++ = CP_REG(REG_LEIA_RB_LRZ_VSC_CONTROL);
*cmds++ = 0x0000000;
*cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 3);
@@ -837,43 +792,43 @@
/* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_SQ_PROGRAM_CNTL);
+ *cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL);
*cmds++ = 0x10030002;
*cmds++ = 0x00000008;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_SC_AA_MASK);
+ *cmds++ = CP_REG(REG_PA_SC_AA_MASK);
*cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */
if (!adreno_is_a22x(adreno_dev)) {
/* PA_SC_VIZ_QUERY */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_SC_VIZ_QUERY);
+ *cmds++ = CP_REG(REG_PA_SC_VIZ_QUERY);
*cmds++ = 0x0; /*REG_PA_SC_VIZ_QUERY */
}
/* RB_COLORCONTROL */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_COLORCONTROL);
+ *cmds++ = CP_REG(REG_RB_COLORCONTROL);
*cmds++ = 0x00000c20;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4);
- *cmds++ = PM4_REG(REG_VGT_MAX_VTX_INDX);
+ *cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX);
*cmds++ = 0x00ffffff; /* mmVGT_MAX_VTX_INDX */
*cmds++ = 0x0; /* mmVGT_MIN_VTX_INDX */
*cmds++ = 0x00000000; /* mmVGT_INDX_OFFSET */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL);
+ *cmds++ = CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL);
*cmds++ = 0x00000002; /* mmVGT_VERTEX_REUSE_BLOCK_CNTL */
*cmds++ = 0x00000002; /* mmVGT_OUT_DEALLOC_CNTL */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_SQ_INTERPOLATOR_CNTL);
+ *cmds++ = CP_REG(REG_SQ_INTERPOLATOR_CNTL);
*cmds++ = 0xffffffff; /* mmSQ_INTERPOLATOR_CNTL */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_SC_AA_CONFIG);
+ *cmds++ = CP_REG(REG_PA_SC_AA_CONFIG);
*cmds++ = 0x00000000; /* REG_PA_SC_AA_CONFIG */
/* set REG_PA_SU_SC_MODE_CNTL
@@ -882,7 +837,7 @@
* Provoking vertex = last
*/
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_SU_SC_MODE_CNTL);
+ *cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL);
*cmds++ = 0x00080240;
/* texture constants */
@@ -898,7 +853,7 @@
/* program surface info */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_RB_SURFACE_INFO);
+ *cmds++ = CP_REG(REG_RB_SURFACE_INFO);
*cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */
/* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0,
@@ -910,7 +865,7 @@
/* RB_DEPTHCONTROL */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_DEPTHCONTROL);
+ *cmds++ = CP_REG(REG_RB_DEPTHCONTROL);
if (adreno_is_a22x(adreno_dev))
*cmds++ = 8; /* disable Z */
@@ -920,35 +875,35 @@
/* Use maximum scissor values -- quad vertices already
* have the correct bounds */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
+ *cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL);
*cmds++ = (0 << 16) | 0;
*cmds++ = ((0x1fff) << 16) | 0x1fff;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
+ *cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL);
*cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0);
*cmds++ = ((0x1fff) << 16) | 0x1fff;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_CL_VTE_CNTL);
+ *cmds++ = CP_REG(REG_PA_CL_VTE_CNTL);
/* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */
*cmds++ = 0x00000b00;
/*load the viewport so that z scale = clear depth and z offset = 0.0f */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_PA_CL_VPORT_ZSCALE);
+ *cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE);
*cmds++ = 0xbf800000;
*cmds++ = 0x0;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_COLOR_MASK);
+ *cmds++ = CP_REG(REG_RB_COLOR_MASK);
*cmds++ = 0x0000000f; /* R = G = B = 1:enabled */
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_COLOR_DEST_MASK);
+ *cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK);
*cmds++ = 0xffffffff;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3);
- *cmds++ = PM4_REG(REG_SQ_WRAPPING_0);
+ *cmds++ = CP_REG(REG_SQ_WRAPPING_0);
*cmds++ = 0x00000000;
*cmds++ = 0x00000000;
@@ -956,12 +911,12 @@
* $AAM - do this later
*/
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_RB_MODECONTROL);
+ *cmds++ = CP_REG(REG_RB_MODECONTROL);
/* draw pixels with color and depth/stencil component */
*cmds++ = 0x4;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_PA_CL_CLIP_CNTL);
+ *cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL);
*cmds++ = 0x00010000;
if (adreno_is_a22x(adreno_dev)) {
@@ -969,7 +924,7 @@
*cmds++ = 0;
*cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2);
- *cmds++ = PM4_REG(REG_LEIA_RB_LRZ_VSC_CONTROL);
+ *cmds++ = CP_REG(REG_LEIA_RB_LRZ_VSC_CONTROL);
*cmds++ = 0x0000000;
*cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 3);
@@ -991,15 +946,6 @@
return cmds;
}
-/* restore h/w regs, alu constants, texture constants, etc. ... */
-static unsigned *reg_range(unsigned int *cmd, unsigned int start,
- unsigned int end)
-{
- *cmd++ = PM4_REG(start); /* h/w regs, start addr */
- *cmd++ = end - start + 1; /* count */
- return cmd;
-}
-
static void build_regrestore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
@@ -1121,49 +1067,6 @@
tmp_ctx.cmd = cmd;
}
-/* quad for saving/restoring gmem */
-static void set_gmem_copy_quad(struct gmem_shadow_t *shadow)
-{
- /* set vertex buffer values */
- gmem_copy_quad[1] = uint2float(shadow->height);
- gmem_copy_quad[3] = uint2float(shadow->width);
- gmem_copy_quad[4] = uint2float(shadow->height);
- gmem_copy_quad[9] = uint2float(shadow->width);
-
- gmem_copy_quad[0] = uint2float(0);
- gmem_copy_quad[6] = uint2float(0);
- gmem_copy_quad[7] = uint2float(0);
- gmem_copy_quad[10] = uint2float(0);
-
- memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2);
-
- memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord,
- TEXCOORD_LEN << 2);
-}
-
-/* quad for saving/restoring gmem */
-static void build_quad_vtxbuff(struct adreno_context *drawctxt,
- struct gmem_shadow_t *shadow)
-{
- unsigned int *cmd = tmp_ctx.cmd;
-
- /* quad vertex buffer location (in GPU space) */
- shadow->quad_vertices.hostptr = cmd;
- shadow->quad_vertices.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
-
- cmd += QUAD_LEN;
-
- /* tex coord buffer location (in GPU space) */
- shadow->quad_texcoords.hostptr = cmd;
- shadow->quad_texcoords.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
-
- cmd += TEXCOORD_LEN;
-
- set_gmem_copy_quad(shadow);
-
- tmp_ctx.cmd = cmd;
-}
-
static void
build_shader_save_restore_cmds(struct adreno_context *drawctxt)
{
@@ -1343,8 +1246,8 @@
{
int result;
- config_gmemsize(&drawctxt->context_gmem_shadow,
- adreno_dev->gmemspace.sizebytes);
+ calc_gmemsize(&drawctxt->context_gmem_shadow,
+ adreno_dev->gmemspace.sizebytes);
tmp_ctx.gmem_base = adreno_dev->gmemspace.gpu_base;
result = kgsl_allocate(&drawctxt->context_gmem_shadow.gmemshadow,
@@ -1361,7 +1264,8 @@
drawctxt->context_gmem_shadow.size);
/* build quad vertex buffer */
- build_quad_vtxbuff(drawctxt, &drawctxt->context_gmem_shadow);
+ build_quad_vtxbuff(drawctxt, &drawctxt->context_gmem_shadow,
+ &tmp_ctx.cmd);
/* build TP0_CHICKEN register restore command buffer */
tmp_ctx.cmd = build_chicken_restore_cmds(drawctxt);
diff --git a/drivers/gpu/msm/adreno_drawctxt.c b/drivers/gpu/msm/adreno_drawctxt.c
index 3349e35..b7b0ea4 100644
--- a/drivers/gpu/msm/adreno_drawctxt.c
+++ b/drivers/gpu/msm/adreno_drawctxt.c
@@ -17,6 +17,25 @@
#include "kgsl_sharedmem.h"
#include "adreno.h"
+/* quad for copying GMEM to context shadow */
+#define QUAD_LEN 12
+
+static unsigned int gmem_copy_quad[QUAD_LEN] = {
+ 0x00000000, 0x00000000, 0x3f800000,
+ 0x00000000, 0x00000000, 0x3f800000,
+ 0x00000000, 0x00000000, 0x3f800000,
+ 0x00000000, 0x00000000, 0x3f800000
+};
+
+#define TEXCOORD_LEN 8
+
+static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = {
+ 0x00000000, 0x3f800000,
+ 0x3f800000, 0x3f800000,
+ 0x00000000, 0x00000000,
+ 0x3f800000, 0x00000000
+};
+
/*
* Helper functions
* These are global helper functions used by the GPUs during context switch
@@ -46,6 +65,54 @@
return exp | frac;
}
+static void set_gmem_copy_quad(struct gmem_shadow_t *shadow)
+{
+ /* set vertex buffer values */
+ gmem_copy_quad[1] = uint2float(shadow->height);
+ gmem_copy_quad[3] = uint2float(shadow->width);
+ gmem_copy_quad[4] = uint2float(shadow->height);
+ gmem_copy_quad[9] = uint2float(shadow->width);
+
+ gmem_copy_quad[0] = 0;
+ gmem_copy_quad[6] = 0;
+ gmem_copy_quad[7] = 0;
+ gmem_copy_quad[10] = 0;
+
+ memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2);
+
+ memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord,
+ TEXCOORD_LEN << 2);
+}
+
+/**
+ * build_quad_vtxbuff - Create a quad for saving/restoring GMEM
+ * @ context - Pointer to the context being created
+ * @ shadow - Pointer to the GMEM shadow structure
+ * @ incmd - Pointer to pointer to the temporary command buffer
+ */
+
+/* quad for saving/restoring gmem */
+void build_quad_vtxbuff(struct adreno_context *drawctxt,
+ struct gmem_shadow_t *shadow, unsigned int **incmd)
+{
+ unsigned int *cmd = *incmd;
+
+ /* quad vertex buffer location (in GPU space) */
+ shadow->quad_vertices.hostptr = cmd;
+ shadow->quad_vertices.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
+
+ cmd += QUAD_LEN;
+
+ /* tex coord buffer location (in GPU space) */
+ shadow->quad_texcoords.hostptr = cmd;
+ shadow->quad_texcoords.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
+
+ cmd += TEXCOORD_LEN;
+
+ set_gmem_copy_quad(shadow);
+ *incmd = cmd;
+}
+
/**
* adreno_drawctxt_create - create a new adreno draw context
* @device - KGSL device to create the context on
diff --git a/drivers/gpu/msm/adreno_drawctxt.h b/drivers/gpu/msm/adreno_drawctxt.h
index 717805f..c62d6c7 100644
--- a/drivers/gpu/msm/adreno_drawctxt.h
+++ b/drivers/gpu/msm/adreno_drawctxt.h
@@ -97,6 +97,9 @@
/* GPU context switch helper functions */
+void build_quad_vtxbuff(struct adreno_context *drawctxt,
+ struct gmem_shadow_t *shadow, unsigned int **incmd);
+
unsigned int uint2float(unsigned int);
static inline unsigned int virt2gpu(unsigned int *cmd,
@@ -115,4 +118,35 @@
cmd[2] = end - start;
}
+
+static inline unsigned int *reg_range(unsigned int *cmd, unsigned int start,
+ unsigned int end)
+{
+ *cmd++ = CP_REG(start); /* h/w regs, start addr */
+ *cmd++ = end - start + 1; /* count */
+ return cmd;
+}
+
+static inline void calc_gmemsize(struct gmem_shadow_t *shadow, int gmem_size)
+{
+ int w = 64, h = 64;
+
+ shadow->format = COLORX_8_8_8_8;
+
+ /* convert from bytes to 32-bit words */
+ gmem_size = (gmem_size + 3) / 4;
+
+ while ((w * h) < gmem_size) {
+ if (w < h)
+ w *= 2;
+ else
+ h *= 2;
+ }
+
+ shadow->pitch = shadow->width = w;
+ shadow->height = h;
+ shadow->gmem_pitch = shadow->pitch;
+ shadow->size = shadow->pitch * shadow->height * 4;
+}
+
#endif /* __ADRENO_DRAWCTXT_H */
diff --git a/drivers/gpu/msm/adreno_pm4types.h b/drivers/gpu/msm/adreno_pm4types.h
index 4d6f70a..772cd28 100644
--- a/drivers/gpu/msm/adreno_pm4types.h
+++ b/drivers/gpu/msm/adreno_pm4types.h
@@ -184,4 +184,10 @@
#define PM4_HDR_INDIRECT_BUFFER_PFD pm4_type3_packet(PM4_INDIRECT_BUFFER_PFD, 2)
#define PM4_HDR_INDIRECT_BUFFER pm4_type3_packet(PM4_INDIRECT_BUFFER, 2)
+/* dword base address of the GFX decode space */
+#define SUBBLOCK_OFFSET(reg) ((unsigned int)((reg) - (0x2000)))
+
+/* gmem command buffer length */
+#define CP_REG(reg) ((0x4 << 16) | (SUBBLOCK_OFFSET(reg)))
+
#endif /* __ADRENO_PM4TYPES_H */
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 892012c..1d44d20 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -361,21 +361,21 @@
GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO));
+ SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO));
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET));
+ SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET));
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX));
+ SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX));
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL));
+ SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL));
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL));
+ SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL));
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE));
+ SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE));
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL));
+ SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL));
GSL_RB_WRITE(cmds, cmds_gpu,
- GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE));
+ SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE));
/* Vertex and Pixel Shader Start Addresses in instructions
* (3 DWORDS per instruction) */
diff --git a/drivers/gpu/msm/adreno_ringbuffer.h b/drivers/gpu/msm/adreno_ringbuffer.h
index 04432fe..487a748 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.h
+++ b/drivers/gpu/msm/adreno_ringbuffer.h
@@ -61,8 +61,6 @@
uint32_t timestamp;
};
-/* dword base address of the GFX decode space */
-#define GSL_HAL_SUBBLOCK_OFFSET(reg) ((unsigned int)((reg) - (0x2000)))
#define GSL_RB_WRITE(ring, gpuaddr, data) \
do { \