arm: log readl/writel accesses
Log readl/writel accesses in the small uncached buffer.
readl/writel are typically used for reading from memory
mapped registers, which can cause hangs if accessed
unclocked. Log this information in a buffer to aid in
debugging.
Change-Id: Id72da6b028a3faf5d0d8e069e14d90e4671e3564
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
diff --git a/arch/arm/mach-msm/include/mach/msm_rtb.h b/arch/arm/mach-msm/include/mach/msm_rtb.h
index 2831428..a24e892 100644
--- a/arch/arm/mach-msm/include/mach/msm_rtb.h
+++ b/arch/arm/mach-msm/include/mach/msm_rtb.h
@@ -32,6 +32,22 @@
*/
int uncached_logk(enum logk_event_type log_type, void *data);
+#define ETB_WAYPOINT do { \
+ BRANCH_TO_NEXT_ISTR; \
+ nop(); \
+ BRANCH_TO_NEXT_ISTR; \
+ nop(); \
+ } while (0)
+
+#define BRANCH_TO_NEXT_ISTR asm volatile("b .+4\n" : : : "memory")
+/*
+ * both the mb and the isb are needed to ensure enough waypoints for
+ * etb tracing
+ */
+#define LOG_BARRIER do { \
+ mb(); \
+ isb();\
+ } while (0)
#else
static inline int uncached_logk_pc(enum logk_event_type log_type,
@@ -40,5 +56,13 @@
static inline int uncached_logk(enum logk_event_type log_type,
void *data) { return 0; }
+
+#define ETB_WAYPOINT
+#define BRANCH_TO_NEXT_ISTR
+/*
+ * Due to a GCC bug, we need to have a nop here in order to prevent an extra
+ * read from being generated after the write.
+ */
+#define LOG_BARRIER nop()
#endif
#endif
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index 7560dc2..d46bd77 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -1,6 +1,7 @@
/* arch/arm/mach-msm/include/mach/uncompress.h
*
* Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -34,18 +35,18 @@
* Wait for TX_READY to be set; but skip it if we have a
* TX underrun.
*/
- if (!(__raw_readl(base + UARTDM_SR_OFFSET) & 0x08))
- while (!(__raw_readl(base + UARTDM_ISR_OFFSET) & 0x80))
+ if (!(__raw_readl_no_log(base + UARTDM_SR_OFFSET) & 0x08))
+ while (!(__raw_readl_no_log(base + UARTDM_ISR_OFFSET) & 0x80))
cpu_relax();
- __raw_writel(0x300, base + UARTDM_CR_OFFSET);
- __raw_writel(0x1, base + UARTDM_NCF_TX_OFFSET);
- __raw_writel(c, base + UARTDM_TF_OFFSET);
+ __raw_writel_no_log(0x300, base + UARTDM_CR_OFFSET);
+ __raw_writel_no_log(0x1, base + UARTDM_NCF_TX_OFFSET);
+ __raw_writel_no_log(c, base + UARTDM_TF_OFFSET);
#else
/* Wait for TX_READY to be set */
- while (!(__raw_readl(base + 0x08) & 0x04))
+ while (!(__raw_readl_no_log(base + 0x08) & 0x04))
cpu_relax();
- __raw_writel(c, base + 0x0c);
+ __raw_writel_no_log(c, base + 0x0c);
#endif
#endif
}