Merge "msm: audio_slimbus: Register device with clock driver and rename clocks" into msm-3.0
diff --git a/Documentation/devicetree/bindings/mmc/msm_sdcc.txt b/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
index 4fb653e..084050e 100644
--- a/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
+++ b/Documentation/devicetree/bindings/mmc/msm_sdcc.txt
@@ -24,13 +24,13 @@
Example:
- qcom,sdcc@F9600000 {
+ qcom,sdcc@f9600000 {
/* SDC1 used as eMMC slot */
cell-index = <1>;
compatible = "qcom,msm-sdcc";
- reg = <0xF9600000 0x800 // SDCC register interface
- 0xF9600800 0x1800 // DML register interface
- 0xF9602000 0x2000> // BAM register interface
+ reg = <0xf9600000 0x800 // SDCC register interface
+ 0xf9600800 0x1800 // DML register interface
+ 0xf9602000 0x2000> // BAM register interface
interrupts = <123>;
qcom,sdcc-clk-rates = <400000 24000000 48000000>;
diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index c1399ae..95ddf34 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -35,16 +35,16 @@
- qcom,hsusb-otg-pmic-id-irq: ID, routed to PMIC IRQ number
Example HSUSB OTG controller device node :
- usb@F9690000 {
+ usb@f9690000 {
compatible = "qcom,hsusb-otg";
- reg = <0xF9690000 0x400>;
+ reg = <0xf9690000 0x400>;
interrupts = <134>;
qcom,hsusb-otg-phy-type = <2>;
qcom,hsusb-otg-mode = <1>;
qcom,hsusb-otg-otg-control = <1>;
qcom,hsusb-otg-default-mode = <2>;
- qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xFFFFFFFF>;
+ qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xffffffff>;
qcom,hsusb-otg-power-budget = <500>;
qcom,hsusb-otg-pclk-src-name = "dfab_usb_clk";
qcom,hsusb-otg-pmic-id-irq = <47>
diff --git a/arch/arm/boot/dts/msmcopper.dts b/arch/arm/boot/dts/msmcopper.dts
index 57ad77a..08c16fa 100644
--- a/arch/arm/boot/dts/msmcopper.dts
+++ b/arch/arm/boot/dts/msmcopper.dts
@@ -27,15 +27,15 @@
interrupts = <1 2 0>;
};
- serial@F991F000 {
+ serial@f991f000 {
compatible = "qcom,msm-lsuart-v14";
- reg = <0xF991F000 0x1000>;
+ reg = <0xf991f000 0x1000>;
interrupts = <0 109 0>;
};
- usb@F9A55000 {
+ usb@f9a55000 {
compatible = "qcom,hsusb-otg";
- reg = <0xF9A55000 0x400>;
+ reg = <0xf9a55000 0x400>;
interrupts = <0 134 0>;
qcom,hsusb-otg-phy-type = <2>;
@@ -43,10 +43,10 @@
qcom,hsusb-otg-otg-control = <1>;
};
- qcom,sdcc@F980B000 {
+ qcom,sdcc@f980b000 {
cell-index = <1>;
compatible = "qcom,msm-sdcc";
- reg = <0xF980B000 0x1000>;
+ reg = <0xf980b000 0x1000>;
interrupts = <0 123 0>;
qcom,sdcc-clk-rates = <400000 24000000 48000000>;
@@ -56,10 +56,10 @@
qcom,sdcc-disable_cmd23;
};
- qcom,sdcc@F984B000 {
+ qcom,sdcc@f984b000 {
cell-index = <3>;
compatible = "qcom,msm-sdcc";
- reg = <0xF984B000 0x1000>;
+ reg = <0xf984b000 0x1000>;
interrupts = <0 127 0>;
qcom,sdcc-clk-rates = <400000 24000000 48000000>;
@@ -68,10 +68,10 @@
qcom,sdcc-disable_cmd23;
};
- qcom,sps@F9980000 {
+ qcom,sps@f9980000 {
compatible = "qcom,msm_sps";
- reg = <0xF9984000 0x15000>,
- <0xF9999000 0xB000>;
+ reg = <0xf9984000 0x15000>,
+ <0xf9999000 0xb000>;
interrupts = <0 94 0>;
qcom,bam-dma-res-pipes = <6>;
diff --git a/arch/arm/mach-msm/board-8960-display.c b/arch/arm/mach-msm/board-8960-display.c
index aa8477e..1f6d04f 100644
--- a/arch/arm/mach-msm/board-8960-display.c
+++ b/arch/arm/mach-msm/board-8960-display.c
@@ -68,6 +68,7 @@
#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME "mipi_cmd_novatek_qhd"
#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME "mipi_video_novatek_qhd"
#define MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME "mipi_video_toshiba_wsvga"
+#define MIPI_VIDEO_ASUS_WUXGA_PANEL_NAME "mipi_video_asus_wuxga"
#define MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME "mipi_video_chimei_wxga"
#define MIPI_VIDEO_CHIMEI_WUXGA_PANEL_NAME "mipi_video_chimei_wuxga"
#define MIPI_VIDEO_SIMULATOR_VGA_PANEL_NAME "mipi_video_simulator_vga"
@@ -81,7 +82,7 @@
}
};
-static void set_mdp_clocks_for_liquid_wuxga(void);
+static void set_mdp_clocks_for_wuxga(void);
static int msm_fb_detect_panel(const char *name)
{
@@ -91,7 +92,7 @@
if (!strncmp(name, MIPI_VIDEO_CHIMEI_WUXGA_PANEL_NAME,
strnlen(MIPI_VIDEO_CHIMEI_WUXGA_PANEL_NAME,
PANEL_NAME_MAX_LEN))) {
- set_mdp_clocks_for_liquid_wuxga();
+ set_mdp_clocks_for_wuxga();
return 0;
}
} else {
@@ -126,6 +127,13 @@
strnlen(MIPI_CMD_RENESAS_FWVGA_PANEL_NAME,
PANEL_NAME_MAX_LEN)))
return 0;
+
+ if (!strncmp(name, MIPI_VIDEO_ASUS_WUXGA_PANEL_NAME,
+ strnlen(MIPI_VIDEO_ASUS_WUXGA_PANEL_NAME,
+ PANEL_NAME_MAX_LEN))) {
+ set_mdp_clocks_for_wuxga();
+ return 0;
+ }
#endif
}
@@ -649,9 +657,9 @@
/**
* Set MDP clocks to high frequency to avoid DSI underflow
- * when using high resolution 1200x1920 WUXGA panel.
+ * when using high resolution 1200x1920 WUXGA panels
*/
-static void set_mdp_clocks_for_liquid_wuxga(void)
+static void set_mdp_clocks_for_wuxga(void)
{
int i;
diff --git a/arch/arm/mach-msm/cp14.h b/arch/arm/mach-msm/cp14.h
index 9f7241e..d640412 100644
--- a/arch/arm/mach-msm/cp14.h
+++ b/arch/arm/mach-msm/cp14.h
@@ -325,21 +325,21 @@
#define RCP14_ETMACTR14() MRC14(1, c0, c14, 2)
#define RCP14_ETMACTR15() MRC14(1, c0, c15, 2)
#define RCP14_ETMDCVR0() MRC14(1, c0, c0, 3)
-#define RCP14_ETMDCVR1() MRC14(1, c0, c1, 3)
#define RCP14_ETMDCVR2() MRC14(1, c0, c2, 3)
-#define RCP14_ETMDCVR3() MRC14(1, c0, c3, 3)
#define RCP14_ETMDCVR4() MRC14(1, c0, c4, 3)
-#define RCP14_ETMDCVR5() MRC14(1, c0, c5, 3)
#define RCP14_ETMDCVR6() MRC14(1, c0, c6, 3)
-#define RCP14_ETMDCVR7() MRC14(1, c0, c7, 3)
+#define RCP14_ETMDCVR8() MRC14(1, c0, c8, 3)
+#define RCP14_ETMDCVR10() MRC14(1, c0, c10, 3)
+#define RCP14_ETMDCVR12() MRC14(1, c0, c12, 3)
+#define RCP14_ETMDCVR14() MRC14(1, c0, c14, 3)
#define RCP14_ETMDCMR0() MRC14(1, c0, c0, 4)
-#define RCP14_ETMDCMR1() MRC14(1, c0, c1, 4)
#define RCP14_ETMDCMR2() MRC14(1, c0, c2, 4)
-#define RCP14_ETMDCMR3() MRC14(1, c0, c3, 4)
#define RCP14_ETMDCMR4() MRC14(1, c0, c4, 4)
-#define RCP14_ETMDCMR5() MRC14(1, c0, c5, 4)
#define RCP14_ETMDCMR6() MRC14(1, c0, c6, 4)
-#define RCP14_ETMDCMR7() MRC14(1, c0, c7, 4)
+#define RCP14_ETMDCMR8() MRC14(1, c0, c8, 4)
+#define RCP14_ETMDCMR10() MRC14(1, c0, c10, 4)
+#define RCP14_ETMDCMR12() MRC14(1, c0, c12, 4)
+#define RCP14_ETMDCMR14() MRC14(1, c0, c14, 4)
#define RCP14_ETMCNTRLDVR0() MRC14(1, c0, c0, 5)
#define RCP14_ETMCNTRLDVR1() MRC14(1, c0, c1, 5)
#define RCP14_ETMCNTRLDVR2() MRC14(1, c0, c2, 5)
@@ -389,7 +389,7 @@
#define RCP14_ETMAUXCR() MRC14(1, c0, c15, 7)
#define RCP14_ETMTRACEIDR() MRC14(1, c1, c0, 0)
#define RCP14_ETMIDR2() MRC14(1, c1, c2, 0)
-#define RCP14_ETMVMIDCVR() MRC14(1, c1, c1, 0)
+#define RCP14_ETMVMIDCVR() MRC14(1, c1, c0, 1)
#define RCP14_ETMOSLSR() MRC14(1, c1, c1, 4)
/* not available in PFTv1.1 */
#define RCP14_ETMOSSRR() MRC14(1, c1, c2, 4)
@@ -462,21 +462,21 @@
#define WCP14_ETMACTR14(val) MCR14(val, 1, c0, c14, 2)
#define WCP14_ETMACTR15(val) MCR14(val, 1, c0, c15, 2)
#define WCP14_ETMDCVR0(val) MCR14(val, 1, c0, c0, 3)
-#define WCP14_ETMDCVR1(val) MCR14(val, 1, c0, c1, 3)
#define WCP14_ETMDCVR2(val) MCR14(val, 1, c0, c2, 3)
-#define WCP14_ETMDCVR3(val) MCR14(val, 1, c0, c3, 3)
#define WCP14_ETMDCVR4(val) MCR14(val, 1, c0, c4, 3)
-#define WCP14_ETMDCVR5(val) MCR14(val, 1, c0, c5, 3)
#define WCP14_ETMDCVR6(val) MCR14(val, 1, c0, c6, 3)
-#define WCP14_ETMDCVR7(val) MCR14(val, 1, c0, c7, 3)
+#define WCP14_ETMDCVR8(val) MCR14(val, 1, c0, c8, 3)
+#define WCP14_ETMDCVR10(val) MCR14(val, 1, c0, c10, 3)
+#define WCP14_ETMDCVR12(val) MCR14(val, 1, c0, c12, 3)
+#define WCP14_ETMDCVR14(val) MCR14(val, 1, c0, c14, 3)
#define WCP14_ETMDCMR0(val) MCR14(val, 1, c0, c0, 4)
-#define WCP14_ETMDCMR1(val) MCR14(val, 1, c0, c1, 4)
#define WCP14_ETMDCMR2(val) MCR14(val, 1, c0, c2, 4)
-#define WCP14_ETMDCMR3(val) MCR14(val, 1, c0, c3, 4)
#define WCP14_ETMDCMR4(val) MCR14(val, 1, c0, c4, 4)
-#define WCP14_ETMDCMR5(val) MCR14(val, 1, c0, c5, 4)
#define WCP14_ETMDCMR6(val) MCR14(val, 1, c0, c6, 4)
-#define WCP14_ETMDCMR7(val) MCR14(val, 1, c0, c7, 4)
+#define WCP14_ETMDCMR8(val) MCR14(val, 1, c0, c8, 4)
+#define WCP14_ETMDCMR10(val) MCR14(val, 1, c0, c10, 4)
+#define WCP14_ETMDCMR12(val) MCR14(val, 1, c0, c12, 4)
+#define WCP14_ETMDCMR14(val) MCR14(val, 1, c0, c14, 4)
#define WCP14_ETMCNTRLDVR0(val) MCR14(val, 1, c0, c0, 5)
#define WCP14_ETMCNTRLDVR1(val) MCR14(val, 1, c0, c1, 5)
#define WCP14_ETMCNTRLDVR2(val) MCR14(val, 1, c0, c2, 5)
@@ -525,7 +525,7 @@
#define WCP14_ETMAUXCR(val) MCR14(val, 1, c0, c15, 7)
#define WCP14_ETMTRACEIDR(val) MCR14(val, 1, c1, c0, 0)
#define WCP14_ETMIDR2(val) MCR14(val, 1, c1, c2, 0)
-#define WCP14_ETMVMIDCVR(val) MCR14(val, 1, c1, c1, 0)
+#define WCP14_ETMVMIDCVR(val) MCR14(val, 1, c1, c0, 1)
#define WCP14_ETMOSLAR(val) MCR14(val, 1, c1, c0, 4)
/* not available in PFTv1.1 */
#define WCP14_ETMOSSRR(val) MCR14(val, 1, c1, c2, 4)
diff --git a/arch/arm/mach-msm/etm.c b/arch/arm/mach-msm/etm.c
index bee0975..9d04a58 100644
--- a/arch/arm/mach-msm/etm.c
+++ b/arch/arm/mach-msm/etm.c
@@ -377,9 +377,9 @@
etm_write(etm_config.etm_addr_access_type[6], ETMACTR6);
etm_write(etm_config.etm_addr_access_type[7], ETMACTR7);
etm_write(etm_config.etm_data_comp_value[0], ETMDCVR0);
- etm_write(etm_config.etm_data_comp_value[1], ETMDCVR1);
+ etm_write(etm_config.etm_data_comp_value[1], ETMDCVR2);
etm_write(etm_config.etm_data_comp_mask[0], ETMDCMR0);
- etm_write(etm_config.etm_data_comp_mask[1], ETMDCMR1);
+ etm_write(etm_config.etm_data_comp_mask[1], ETMDCMR2);
etm_write(etm_config.etm_counter_reload_value[0], ETMCNTRLDVR0);
etm_write(etm_config.etm_counter_reload_value[1], ETMCNTRLDVR1);
etm_write(etm_config.etm_counter_enable[0], ETMCNTENR0);
@@ -564,9 +564,9 @@
emit_log_word(etm_read(ETMACTR6));
emit_log_word(etm_read(ETMACTR7));
emit_log_word(etm_read(ETMDCVR0));
- emit_log_word(etm_read(ETMDCVR1));
+ emit_log_word(etm_read(ETMDCVR2));
emit_log_word(etm_read(ETMDCMR0));
- emit_log_word(etm_read(ETMDCMR1));
+ emit_log_word(etm_read(ETMDCMR2));
emit_log_word(etm_read(ETMCNTRLDVR0));
emit_log_word(etm_read(ETMCNTRLDVR1));
emit_log_word(etm_read(ETMCNTENR0));
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 26adec6..616763c 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -49,6 +49,9 @@
/*
* OK, proper wakeup, we're done
*/
+ pen_release = -1;
+ dmac_flush_range((void *)&pen_release,
+ (void *)(&pen_release + sizeof(pen_release)));
break;
}
@@ -60,6 +63,8 @@
* possible, since we are currently running incoherently, and
* therefore cannot safely call printk() or anything else
*/
+ dmac_inv_range((void *)&pen_release,
+ (void *)(&pen_release + sizeof(pen_release)));
pr_debug("CPU%u: spurious wakeup call\n", cpu);
}
}
diff --git a/arch/arm/mach-msm/include/mach/camera.h b/arch/arm/mach-msm/include/mach/camera.h
index 530d2c1..700e28c 100644
--- a/arch/arm/mach-msm/include/mach/camera.h
+++ b/arch/arm/mach-msm/include/mach/camera.h
@@ -52,6 +52,7 @@
VFE_MODE_OF_OPERATION_VIDEO,
VFE_MODE_OF_OPERATION_RAW_SNAPSHOT,
VFE_MODE_OF_OPERATION_ZSL,
+ VFE_MODE_OF_OPERATION_JPEG_SNAPSHOT,
VFE_LAST_MODE_OF_OPERATION_ENUM
};
@@ -87,6 +88,7 @@
VFE_MSG_V32_START,
VFE_MSG_V32_START_RECORDING, /* 20 */
VFE_MSG_V32_CAPTURE,
+ VFE_MSG_V32_JPEG_CAPTURE,
VFE_MSG_OUTPUT_IRQ,
VFE_MSG_V2X_PREVIEW,
VFE_MSG_V2X_CAPTURE,
diff --git a/arch/arm/mach-msm/jtag.c b/arch/arm/mach-msm/jtag.c
index f720fa9..b75fb38 100644
--- a/arch/arm/mach-msm/jtag.c
+++ b/arch/arm/mach-msm/jtag.c
@@ -22,8 +22,10 @@
#include "qdss.h"
#include "cp14.h"
+ /* no of dbg regs + 1 (for storing the reg count) */
#define MAX_DBG_REGS (90)
#define MAX_DBG_STATE_SIZE (MAX_DBG_REGS * num_possible_cpus())
+ /* no of etm regs + 1 (for storing the reg count) */
#define MAX_ETM_REGS (78)
#define MAX_ETM_STATE_SIZE (MAX_ETM_REGS * num_possible_cpus())
@@ -70,7 +72,7 @@
break;
case 3:
state[i++] = dbg_read(DBGBVR3);
- state[i++] = dbg_read(DBGBVR3);
+ state[i++] = dbg_read(DBGBCR3);
break;
case 4:
state[i++] = dbg_read(DBGBVR4);
@@ -78,7 +80,7 @@
break;
case 5:
state[i++] = dbg_read(DBGBVR5);
- state[i++] = dbg_read(DBGBVR5);
+ state[i++] = dbg_read(DBGBCR5);
break;
case 6:
state[i++] = dbg_read(DBGBVR6);
@@ -143,7 +145,7 @@
break;
case 3:
dbg_write(state[i++], DBGBVR3);
- dbg_write(state[i++], DBGBVR3);
+ dbg_write(state[i++], DBGBCR3);
break;
case 4:
dbg_write(state[i++], DBGBVR4);
@@ -151,7 +153,7 @@
break;
case 5:
dbg_write(state[i++], DBGBVR5);
- dbg_write(state[i++], DBGBVR5);
+ dbg_write(state[i++], DBGBCR5);
break;
case 6:
dbg_write(state[i++], DBGBVR6);
@@ -937,9 +939,9 @@
etm_write(etm.state[i++], ETMSQ12EVR);
etm_write(etm.state[i++], ETMSQ21EVR);
etm_write(etm.state[i++], ETMSQ23EVR);
+ etm_write(etm.state[i++], ETMSQ31EVR);
etm_write(etm.state[i++], ETMSQ32EVR);
etm_write(etm.state[i++], ETMSQ13EVR);
- etm_write(etm.state[i++], ETMSQ31EVR);
etm_write(etm.state[i++], ETMSQR);
for (j = 0; j < etm.nr_ext_out; j++)
i = etm_write_extoutevr(etm.state, i, j);
@@ -1046,9 +1048,9 @@
pr_info("dbg arch %u not supported\n", dbg.arch);
goto dbg_out;
}
- dbg.nr_ctx_cmp = BMVAL(dbgdidr, 20, 23);
- dbg.nr_bp = BMVAL(dbgdidr, 24, 27);
- dbg.nr_wp = BMVAL(dbgdidr, 28, 31);
+ dbg.nr_ctx_cmp = BMVAL(dbgdidr, 20, 23) + 1;
+ dbg.nr_bp = BMVAL(dbgdidr, 24, 27) + 1;
+ dbg.nr_wp = BMVAL(dbgdidr, 28, 31) + 1;
/* Allocate dbg state save space */
dbg.state = kzalloc(MAX_DBG_STATE_SIZE * sizeof(uint32_t), GFP_KERNEL);
diff --git a/arch/arm/mach-msm/qdss-ptm.c b/arch/arm/mach-msm/qdss-ptm.c
index 96a727a..c0dc58e 100644
--- a/arch/arm/mach-msm/qdss-ptm.c
+++ b/arch/arm/mach-msm/qdss-ptm.c
@@ -67,9 +67,9 @@
#define ETMSQ12EVR (0x180)
#define ETMSQ21EVR (0x184)
#define ETMSQ23EVR (0x188)
-#define ETMSQ32EVR (0x18C)
-#define ETMSQ13EVR (0x190)
-#define ETMSQ31EVR (0x194)
+#define ETMSQ31EVR (0x18C)
+#define ETMSQ32EVR (0x190)
+#define ETMSQ13EVR (0x194)
#define ETMSQR (0x19C)
#define ETMEXTOUTEVRn(n) (0x1A0 + (n * 4))
#define ETMCIDCVRn(n) (0x1B0 + (n * 4))
@@ -91,7 +91,7 @@
#define ETMTSEVR (0x1F8)
#define ETMAUXCR (0x1FC)
#define ETMTRACEIDR (0x200)
-#define ETMVMIDCVR (0x204)
+#define ETMVMIDCVR (0x240)
/* Management registers (0x300-0x314) */
#define ETMOSLAR (0x300)
#define ETMOSLSR (0x304)
diff --git a/drivers/media/video/msm/msm_isp.c b/drivers/media/video/msm/msm_isp.c
index c9a9f1b..16964b2 100644
--- a/drivers/media/video/msm/msm_isp.c
+++ b/drivers/media/video/msm/msm_isp.c
@@ -199,6 +199,19 @@
vfe_params.data = (void *)&free_buf;
rc = v4l2_subdev_call(sd, core, ioctl, 0, &vfe_params);
break;
+ case VFE_MSG_V32_JPEG_CAPTURE:
+ free_buf.num_planes = 1;
+ free_buf.ch_paddr[0] = IMEM_Y_OFFSET;
+ free_buf.ch_paddr[1] = IMEM_CBCR_OFFSET;
+ cfgcmd.cmd_type = CMD_CONFIG_PING_ADDR;
+ cfgcmd.value = &vfe_id;
+ vfe_params.vfe_cfg = &cfgcmd;
+ vfe_params.data = (void *)&free_buf;
+ rc = v4l2_subdev_call(sd, core, ioctl, 0, &vfe_params);
+ /* Write the same buffer into PONG */
+ cfgcmd.cmd_type = CMD_CONFIG_PONG_ADDR;
+ rc = v4l2_subdev_call(sd, core, ioctl, 0, &vfe_params);
+ break;
case VFE_MSG_OUTPUT_IRQ:
D("%s Got OUTPUT_IRQ: Getting free buf id = %d",
__func__, vfe_id);
diff --git a/drivers/media/video/msm/msm_vfe32.c b/drivers/media/video/msm/msm_vfe32.c
index 99d9911..89bdf0f 100644
--- a/drivers/media/video/msm/msm_vfe32.c
+++ b/drivers/media/video/msm/msm_vfe32.c
@@ -702,8 +702,6 @@
msm_io_w(VFE_IMASK_WHILE_STOPPING_1,
vfe32_ctrl->vfebase + VFE_IRQ_MASK_1);
- msm_io_dump(vfe32_ctrl->vfebase, vfe32_ctrl->register_total * 4);
-
/* Ensure the write order while writing
to the command register using the barrier */
msm_io_w_mb(1, vfe32_ctrl->vfebase + VFE_REG_UPDATE_CMD);
@@ -851,7 +849,9 @@
/* capture command is valid for both idle and active state. */
vfe32_ctrl->outpath.out1.capture_cnt = num_frames_capture;
if (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
- vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN) {
+ vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN ||
+ vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
+ vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG) {
vfe32_ctrl->outpath.out0.capture_cnt =
num_frames_capture;
}
@@ -887,6 +887,9 @@
vfe32_AXI_WM_CFG[vfe32_ctrl->outpath.out1.ch1]);
}
}
+
+ vfe32_ctrl->vfe_capture_count = num_frames_capture;
+
msm_io_w(irq_comp_mask, vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_io_r(vfe32_ctrl->vfebase + VFE_IRQ_COMP_MASK);
msm_camio_bus_scale_cfg(
@@ -1286,16 +1289,31 @@
rc = vfe32_capture_raw(snapshot_cnt);
break;
case VFE_CMD_CAPTURE:
- pr_info("vfe32_proc_general: cmdID = %s\n",
- vfe32_general_cmd[cmd->id]);
+ CDBG("vfe32_proc_general: cmdID = %s op mode = %d\n",
+ vfe32_general_cmd[cmd->id], vfe32_ctrl->operation_mode);
if (copy_from_user(&snapshot_cnt, (void __user *)(cmd->value),
sizeof(uint32_t))) {
rc = -EFAULT;
goto proc_general_done;
}
- /* Configure primary channel */
- rc = vfe32_configure_pingpong_buffers(VFE_MSG_V32_CAPTURE,
- VFE_MSG_OUTPUT_PRIMARY);
+
+ if (vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
+ vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG) {
+ if (snapshot_cnt != 1) {
+ pr_err("only support 1 inline snapshot\n");
+ rc = -EINVAL;
+ goto proc_general_done;
+ }
+ /* Configure primary channel for JPEG */
+ rc = vfe32_configure_pingpong_buffers(
+ VFE_MSG_V32_JPEG_CAPTURE,
+ VFE_MSG_OUTPUT_PRIMARY);
+ } else {
+ /* Configure primary channel */
+ rc = vfe32_configure_pingpong_buffers(
+ VFE_MSG_V32_CAPTURE,
+ VFE_MSG_OUTPUT_PRIMARY);
+ }
if (rc < 0) {
pr_err("%s error configuring pingpong buffers"
" for primary output", __func__);
@@ -2610,7 +2628,9 @@
}
if ((vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN) ||
- (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB)) {
+ (vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB) ||
+ (vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG) ||
+ (vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB)) {
/* in snapshot mode */
/* later we need to add check for live snapshot mode. */
if (vfe32_ctrl->frame_skip_pattern & (0x1 <<
@@ -2858,6 +2878,8 @@
*/
out_bool = ((vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_MAIN ||
vfe32_ctrl->operation_mode == VFE_OUTPUTS_MAIN_AND_THUMB ||
+ vfe32_ctrl->operation_mode == VFE_OUTPUTS_THUMB_AND_JPEG ||
+ vfe32_ctrl->operation_mode == VFE_OUTPUTS_JPEG_AND_THUMB ||
vfe32_ctrl->operation_mode == VFE_OUTPUTS_RAW ||
vfe32_ctrl->liveshot_state == VFE_STATE_STARTED ||
vfe32_ctrl->liveshot_state == VFE_STATE_STOP_REQUESTED ||
@@ -2899,6 +2921,10 @@
vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_MAIN_AND_THUMB ||
vfe32_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_JPEG ||
+ vfe32_ctrl->operation_mode ==
+ VFE_OUTPUTS_JPEG_AND_THUMB ||
+ vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_RAW ||
vfe32_ctrl->liveshot_state == VFE_STATE_STOPPED)
vfe32_ctrl->outpath.out0.capture_cnt--;
@@ -3392,6 +3418,10 @@
vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_MAIN_AND_THUMB ||
vfe32_ctrl->operation_mode ==
+ VFE_OUTPUTS_THUMB_AND_JPEG ||
+ vfe32_ctrl->operation_mode ==
+ VFE_OUTPUTS_JPEG_AND_THUMB ||
+ vfe32_ctrl->operation_mode ==
VFE_OUTPUTS_RAW) {
if ((vfe32_ctrl->outpath.out0.capture_cnt == 0)
&& (vfe32_ctrl->outpath.out1.
diff --git a/drivers/thermal/msm_thermal.c b/drivers/thermal/msm_thermal.c
index ed80b1b..ef28844 100644
--- a/drivers/thermal/msm_thermal.c
+++ b/drivers/thermal/msm_thermal.c
@@ -51,10 +51,7 @@
cpu_policy->user_policy.max = max_freq;
ret = cpufreq_update_policy(cpu);
- if (ret)
- pr_err("msm_thermal: cpufreq update to core%d %d err:%d\n",
- cpu, max_freq, ret);
- else
+ if (!ret)
pr_info("msm_thermal: Limiting core%d max frequency to %d\n",
cpu, max_freq);
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index bf53c73..8299202 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -370,17 +370,18 @@
static uint32 mdp4_scale_phase_step(int f_num, uint32 src, uint32 dst)
{
- uint32 val;
+ uint32 val, s;
int n;
n = mdp4_leading_0(src);
if (n > f_num)
n = f_num;
- val = src << n; /* maximum to reduce lose of resolution */
- val /= dst;
+ s = src << n; /* maximum to reduce lose of resolution */
+ val = s / dst;
if (n < f_num) {
n = f_num - n;
val <<= n;
+ val |= ((s % dst) << n) / dst;
}
return val;
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index 3a1a9aa..f417110 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -527,7 +527,7 @@
*/
temp_src_format = inpdw(rgb_base + 0x0050);
MDP_OUTP(rgb_base + 0x0050, temp_src_format | BIT(22));
- mdp4_mixer_stage_up(pipe);
+ mdp4_mixer_stage_up(dtv_pipe);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
#endif
diff --git a/drivers/video/msm/vidc/common/init/vidc_init.c b/drivers/video/msm/vidc/common/init/vidc_init.c
index cd3f954..bf1c112 100644
--- a/drivers/video/msm/vidc/common/init/vidc_init.c
+++ b/drivers/video/msm/vidc/common/init/vidc_init.c
@@ -540,9 +540,10 @@
client_ctx->user_ion_client,
buff_ion_handle,
ionflag);
- if (!(*kernel_vaddr)) {
+ if (IS_ERR_OR_NULL((void *)*kernel_vaddr)) {
ERR("%s():ION virtual addr fail\n",
__func__);
+ *kernel_vaddr = (unsigned long)NULL;
goto ion_error;
}
if (ion_phys(client_ctx->user_ion_client,
@@ -587,7 +588,7 @@
mutex_unlock(&client_ctx->enrty_queue_lock);
return true;
ion_error:
- if (*kernel_vaddr)
+ if (*kernel_vaddr && buff_ion_handle)
ion_unmap_kernel(client_ctx->user_ion_client, buff_ion_handle);
if (!IS_ERR_OR_NULL(buff_ion_handle))
ion_free(client_ctx->user_ion_client, buff_ion_handle);
diff --git a/include/media/msm_camera.h b/include/media/msm_camera.h
index 87fbbd2..1a6f68f 100644
--- a/include/media/msm_camera.h
+++ b/include/media/msm_camera.h
@@ -693,6 +693,9 @@
#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT+4)
/* camera operation mode for raw snapshot - one frame output queue */
#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT+5)
+/* camera operation mode for jpeg snapshot - one frame output queue */
+#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6)
+
#define MSM_V4L2_VID_CAP_TYPE 0
#define MSM_V4L2_STREAM_ON 1
diff --git a/include/media/msm_isp.h b/include/media/msm_isp.h
index 5dd1445..07784e2 100644
--- a/include/media/msm_isp.h
+++ b/include/media/msm_isp.h
@@ -241,6 +241,9 @@
#define VPE_SCALER_CONFIG_LEN 260
#define VPE_DIS_OFFSET_CFG_LEN 12
+#define IMEM_Y_OFFSET 0x2E000000
+#define IMEM_CBCR_OFFSET 0x2E00FA00
+
struct msm_vpe_op_mode_cfg {
uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
};
@@ -311,6 +314,8 @@
#define VFE_OUTPUTS_PREVIEW BIT(6)
#define VFE_OUTPUTS_VIDEO BIT(7)
#define VFE_OUTPUTS_RAW BIT(8)
+#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
+#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
#endif /*__MSM_ISP_H__*/
diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c
index 94cacde..468f86c 100644
--- a/net/bluetooth/l2cap_sock.c
+++ b/net/bluetooth/l2cap_sock.c
@@ -611,8 +611,16 @@
case L2CAP_MODE_BASIC:
l2cap_pi(sk)->conf_state &= ~L2CAP_CONF_STATE2_DEVICE;
break;
- case L2CAP_MODE_ERTM:
case L2CAP_MODE_STREAMING:
+ if (!disable_ertm) {
+ /* No fallback to ERTM or Basic mode */
+ l2cap_pi(sk)->conf_state |=
+ L2CAP_CONF_STATE2_DEVICE;
+ break;
+ }
+ err = -EINVAL;
+ break;
+ case L2CAP_MODE_ERTM:
if (!disable_ertm)
break;
/* fall through */