| commit | 11c07e2e1bd805a554714a2039cd803886d5593c | [log] [tgz] |
|---|---|---|
| author | Matt Wagantall <mattw@codeaurora.org> | Thu Aug 09 16:14:07 2012 -0700 |
| committer | Matt Wagantall <mattw@codeaurora.org> | Fri Aug 10 00:17:23 2012 -0700 |
| tree | 5d85791638b507cedc9774bf134a17dd6364560b | |
| parent | b76f190d3b3c6ce9a07a483b5e85df449c7f5366 [diff] |
msm: pil-q6v5: Update QDSP6SS RESET and PWR_CTL registers Hardware documentation has been corrected, changing the bit positions and reset states for this register. Update software accordingly. Change-Id: I35ef0e38e9fb64574c74d1082a11af760340f982 Signed-off-by: Matt Wagantall <mattw@codeaurora.org>