| commit | 8b459cc5de14738e16582335a6e0d95edde625f9 | [log] [tgz] |
|---|---|---|
| author | Ashwin Chaugule <ashwinc@codeaurora.org> | Mon Nov 26 15:20:54 2012 -0500 |
| committer | Ashwin Chaugule <ashwinc@codeaurora.org> | Fri Dec 21 13:01:59 2012 -0500 |
| tree | 6c67e9eed3ed34519873bc5ccb16b4ec34ed7cc0 | |
| parent | 11451f463b73469b8c1abfbb6b92c228209b915e [diff] |
msm: Perf: Add 9625 L2 PMU support Enable the L2 cache controller performance monitoring unit on the 9625, so that its counters can be controlled via the perfevents framework. Change-Id: I22f6b1fd1e3e8c57cbbd419d724ec7b81f910b0a Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>