[ARM] 3751/1: i.MX/MX1 SD/MMC use 512 bytes request for SCR read
Patch from Pavel Pisa
This is another approach to SDHC deficiency workaround.
It seems, that previous solution based on 16 bytes (FIFO length size)
read is still timing sensitive on genirq and fully preemptive kernels.
The new solution is backuped by M9328 UM statement, that only 512 byte
block are working properly and by 2.4.26 FreeScale's SDHC code.
Jay Monkman reports significant improvement on code based
on this driver after applying this change on MX21 as well.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 file changed