| commit | 162b96e63e518aa6ff029ce23de12d7f027483bf | [log] [tgz] |
|---|---|---|
| author | Dan Williams <dan.j.williams@intel.com> | Tue Sep 08 17:53:04 2009 -0700 |
| committer | Dan Williams <dan.j.williams@intel.com> | Tue Sep 08 17:53:04 2009 -0700 |
| tree | 532191d0cef7cf975b70a07b1c69a293d6f552f7 | |
| parent | 0803172778901e24a75ab074798d98c2b7411559 [diff] |
ioat2,3: cacheline align software descriptor allocations All the necessary fields for handling an ioat2,3 ring entry can fit into one cacheline. Move ->len prior to ->txd in struct ioat_ring_ent, and move allocation of these entries to a hw-cache-aligned kmem cache to reduce the number of cachelines dirtied for descriptor management. Signed-off-by: Dan Williams <dan.j.williams@intel.com>