| commit | 16d95e648c752ed7706f929aa19717b60b06c061 | [log] [tgz] |
|---|---|---|
| author | Venkat Sudhir <vsudhir@codeaurora.org> | Mon Feb 04 16:57:33 2013 -0800 |
| committer | Venkat Sudhir <vsudhir@codeaurora.org> | Tue Feb 05 17:21:07 2013 -0800 |
| tree | 89cea70a58cdeeb116d40a2660f5c93ee02d0986 | |
| parent | 49c81343653ba942be523d43d907bf9f89354487 [diff] |
ASoC: wcd9xxx: Fix mclk bit setting in codec probe WCD9320 supports different master clock rates. Modify the bits required for master clock alone. This is required to avoid overwriting other bits in chip control register set in default register settings. Change-Id: Id14cce2a404ca2d03121dad8c3eac2ebec433e47 Signed-off-by: Venkat Sudhir <vsudhir@codeaurora.org>