msm: platsmp-8625: Mask mpcore_ipc1 irq before clear
Before clearing the mpcore_ipc1 IRQ which brings core1
out of GDFS need to mask the irq, otherwise we would
see the below warning
4>[ 435.474016] [<c0048778>] (unwind_backtrace+0x0/0x12c) from
[<c00c6b50>] (warn_slowpath_common+0x4c/0x64)
<4>[ 435.474034] [<c00c6b50>] (warn_slowpath_common+0x4c/0x64) from
[<c00c6b80>] (warn_slowpath_null+0x18/0x1c)
<4>[ 435.474051] [<c00c6b80>] (warn_slowpath_null+0x18/0x1c) from
[<c004fa78>] (gic_clear_spi_pending+0x68/0xb0)
<4>[ 435.474073] [<c004fa78>] (gic_clear_spi_pending+0x68/0xb0) from
[<c057e660>] (platform_secondary_init+0xc4/0x10c)
<4>[ 435.474093] [<c057e660>] (platform_secondary_init+0xc4/0x10c) from
[<c057db1c>] (secondary_start_kernel+0xe8/0x188)
We do not need to unmask it, as when we return to bring core-1 out
of reset, we will reconfigure the mpcore_ipc1.
CRs-Fixed: 357455
Change-Id: Ib026fc9072c3cd05911ee342034cf7d389ab36eb
Signed-off-by: Taniya Das <tdas@codeaurora.org>
diff --git a/arch/arm/mach-msm/platsmp-8625.c b/arch/arm/mach-msm/platsmp-8625.c
index beab205..393f1bd 100644
--- a/arch/arm/mach-msm/platsmp-8625.c
+++ b/arch/arm/mach-msm/platsmp-8625.c
@@ -80,8 +80,12 @@
static void clear_pending_spi(unsigned int irq)
{
- /* Clear the IRQ from the ENABLE_SET */
+ struct irq_data *d = irq_get_irq_data(irq);
+ struct irq_chip *c = irq_data_get_irq_chip(d);
+
+ c->irq_mask(d);
local_irq_disable();
+ /* Clear the IRQ from the ENABLE_SET */
gic_clear_spi_pending(irq);
local_irq_enable();
}