| commit | 1da42fa1747c34a814d52eff27a8d8cc356e73e5 | [log] [tgz] |
|---|---|---|
| author | Pushkar Joshi <pushkarj@codeaurora.org> | Wed Jul 10 10:08:16 2013 -0700 |
| committer | Pushkar Joshi <pushkarj@codeaurora.org> | Thu Jul 18 15:28:37 2013 -0700 |
| tree | a7a774f1bc31871f89d29a1e5c4003587b550f98 | |
| parent | ffbac9000939c4b7b48de6589e2f58a1e2943556 [diff] |
ARM: dts: msm: Add CoreSight byte counter interrupt for 9625 The CoreSight block can produce an interrupt on transfer of programmed number of bytes to ETR-memory. Add device tree entry to support this feature. Also, disable the feature on v1 as it does not support it. Change-Id: Id7c6d94efe0a6f30c9773f607625acdb5f1d90a4 Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>