msm: Fix correct topology for qseecom bus scaling.
Currently, bus scaling topology for qseecom is incorrect.
-Added the correct topology paths for accessing Crypto
Engine which is controlled by QSEE.
-Removed setting the clock frequency of DFAB. This is
done by the bus driver.
-Removed references to the dfab clock instance defined
in clocks file.
Change-Id: Ib6953ea3bf5721d458bfe2aa06c54be329a8fdb9
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index f1143de..63f9652 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -1631,10 +1631,16 @@
/* qseecom bus scaling */
static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
{
- .src = MSM_BUS_MASTER_SPS,
+ .src = MSM_BUS_MASTER_ADM_PORT0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ib = 0,
.ab = 0,
+ .ib = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_ADM_PORT1,
+ .dst = MSM_BUS_SLAVE_GSBI1_UART,
+ .ab = 0,
+ .ib = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
@@ -1646,10 +1652,16 @@
static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
{
- .src = MSM_BUS_MASTER_SPS,
+ .src = MSM_BUS_MASTER_ADM_PORT0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ib = (492 * 8) * 1000000UL,
- .ab = (492 * 8) * 100000UL,
+ .ab = 70000000UL,
+ .ib = 70000000UL,
+ },
+ {
+ .src = MSM_BUS_MASTER_ADM_PORT1,
+ .dst = MSM_BUS_SLAVE_GSBI1_UART,
+ .ab = 2480000000UL,
+ .ib = 2480000000UL,
},
{
.src = MSM_BUS_MASTER_SPDM,
@@ -1661,10 +1673,16 @@
static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
{
- .src = MSM_BUS_MASTER_SPS,
+ .src = MSM_BUS_MASTER_ADM_PORT0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ib = 0,
.ab = 0,
+ .ib = 0,
+ },
+ {
+ .src = MSM_BUS_MASTER_ADM_PORT1,
+ .dst = MSM_BUS_SLAVE_GSBI1_UART,
+ .ab = 0,
+ .ib = 0,
},
{
.src = MSM_BUS_MASTER_SPDM,
@@ -1681,7 +1699,7 @@
},
{
ARRAY_SIZE(qseecom_enable_dfab_vectors),
- qseecom_enable_sfpb_vectors,
+ qseecom_enable_dfab_vectors,
},
{
ARRAY_SIZE(qseecom_enable_sfpb_vectors),