Revert "msm: idle-v7: Fix for the issue of lost barrier during reset."
This reverts commit 9850bfdb54b2632b7970f14f9cb99abf1475df50.
Signed-off-by: Patrick Cain <pcain@codeaurora.org>
diff --git a/arch/arm/mach-msm/idle-v7.S b/arch/arm/mach-msm/idle-v7.S
index 2cef87c..98a6354 100644
--- a/arch/arm/mach-msm/idle-v7.S
+++ b/arch/arm/mach-msm/idle-v7.S
@@ -26,7 +26,6 @@
/* 11 general purpose registers (r4-r14), 10 cp15 registers */
#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10)
#endif
-#define TZ_ENTER_POWER_COLLAPSE_CMD 0x00402000
ENTRY(msm_arch_idle)
stmfd sp!, {lr}
@@ -96,19 +95,16 @@
#endif
bl v7_flush_dcache_all
- mrc p15, 0, r4, c1, c0, 0 /* read current CR */
- bic r0, r4, #(1 << 2) /* clear dcache bit */
+ mrc p15, 0, r1, c1, c0, 0 /* read current CR */
+ bic r0, r1, #(1 << 2) /* clear dcache bit */
bic r0, r0, #(1 << 12) /* clear icache bit */
mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
dsb
-#ifdef CONFIG_ARCH_MSM_KRAIT
- ldr r0, =TZ_ENTER_POWER_COLLAPSE_CMD
- smc 0x0
-#else
+
wfi
-#endif
- mcr p15, 0, r4, c1, c0, 0 /* restore d/i cache */
+
+ mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
isb
#if defined(CONFIG_MSM_FIQ_SUPPORT)
@@ -253,3 +249,4 @@
msm_pm_boot_vector:
.space 4 * NR_CPUS
+