| commit | 20a0945951705246278f43641bb13611c030e112 | [log] [tgz] |
|---|---|---|
| author | Chris Wilson <chris@chris-wilson.co.uk> | Sat Aug 07 11:01:29 2010 +0100 |
| committer | Eric Anholt <eric@anholt.net> | Mon Aug 09 11:24:34 2010 -0700 |
| tree | 89c998fd588361566b3a6ff60c1111dab165c7f9 | |
| parent | 1d8e1c75ffa84400758aef9cc59298920b8801f9 [diff] |
drm/i915: Write to display base last. Writing to the DSPBASE register triggers the double-buffered update to all the control registers, so always write it last in the update sequence. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>