EHCI: HSIC: Implement new reset sequence to workaround PHY lockup issue
commit 8e6edcb (usb: ehci: Avoid phy lockup due to SOFs during port
reset) implements a workaround for PHY lockup issue during port reset.
The workaround relies on a hardware debug feature which allows driving
strobe and data lines to reset using ULPI interface. This is not
working some times for unknown reason.
This patch implements a new reset sequence to workaround the PHY lockup
issue. The controller drive reset signaling for ~50 msec when reset bit
is set in PORTSC register. The controller automatically clears this bit
after finishing the reset signaling. The software can also finish the
reset signaling any time by clearing the reset bit.
According to USB2 spec, Host controller should drive reset signaling for
50 msec for root hub ports. But HSIC spec allows shorter reset signaling
time (20 msec). Clear the reset bit in PORTSC register after 20 msec and
start controller immediately to send SOF. Use controller internal timers
to achieve this. If reset bit is not cleared in time, perform the sequence
in a loop with interrupts disabled.
CRs-Fixed: 445659
Change-Id: I884cfcd8a53b111bc9434e47ef483dde64fcc1ed
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
diff --git a/drivers/usb/host/ehci-msm-hsic.c b/drivers/usb/host/ehci-msm-hsic.c
index d06b21b..b1562b8 100644
--- a/drivers/usb/host/ehci-msm-hsic.c
+++ b/drivers/usb/host/ehci-msm-hsic.c
@@ -99,6 +99,8 @@
struct completion rt_completion;
int resume_status;
int resume_again;
+ int bus_reset;
+ int reset_again;
struct pm_qos_request pm_qos_req_dma;
};
@@ -428,7 +430,7 @@
}
-static int ulpi_read(struct msm_hsic_hcd *mehci, u32 reg)
+static int __maybe_unused ulpi_read(struct msm_hsic_hcd *mehci, u32 reg)
{
struct usb_hcd *hcd = hsic_to_hcd(mehci);
int cnt = 0;
@@ -499,37 +501,6 @@
return 0;
}
-#define HSIC_DBG1 0X38
-#define ULPI_MANUAL_ENABLE BIT(4)
-#define ULPI_LINESTATE_DATA BIT(5)
-#define ULPI_LINESTATE_STROBE BIT(6)
-static void ehci_msm_enable_ulpi_control(struct usb_hcd *hcd, u32 linestate)
-{
- struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
- int val;
-
- switch (linestate) {
- case PORT_RESET:
- val = ulpi_read(mehci, HSIC_DBG1);
- val |= ULPI_MANUAL_ENABLE;
- val &= ~(ULPI_LINESTATE_DATA | ULPI_LINESTATE_STROBE);
- ulpi_write(mehci, val, HSIC_DBG1);
- break;
- default:
- pr_info("%s: Unknown linestate:%0x\n", __func__, linestate);
- }
-}
-
-static void ehci_msm_disable_ulpi_control(struct usb_hcd *hcd)
-{
- struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
- int val;
-
- val = ulpi_read(mehci, HSIC_DBG1);
- val &= ~ULPI_MANUAL_ENABLE;
- ulpi_write(mehci, val, HSIC_DBG1);
-}
-
static int msm_hsic_config_gpios(struct msm_hsic_hcd *mehci, int gpio_en)
{
int rc = 0;
@@ -949,6 +920,26 @@
__func__, ret);
}
+static int msm_hsic_reset_done(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ u32 __iomem *status_reg = &ehci->regs->port_status[0];
+ int ret;
+
+ ehci_writel(ehci, ehci_readl(ehci, status_reg) & ~(PORT_RWC_BITS |
+ PORT_RESET), status_reg);
+
+ ret = handshake(ehci, status_reg, PORT_RESET, 0, 1 * 1000);
+
+ if (ret)
+ pr_err("reset handshake failed in %s\n", __func__);
+ else
+ ehci_writel(ehci, ehci_readl(ehci, &ehci->regs->command) |
+ CMD_RUN, &ehci->regs->command);
+
+ return ret;
+}
+
#define STS_GPTIMER0_INTERRUPT BIT(24)
static irqreturn_t msm_hsic_irq(struct usb_hcd *hcd)
{
@@ -976,16 +967,28 @@
if (status & STS_GPTIMER0_INTERRUPT) {
int timeleft;
- dbg_log_event(NULL, "FPR: gpt0_isr", 0);
+ dbg_log_event(NULL, "FPR: gpt0_isr", mehci->bus_reset);
timeleft = GPT_CNT(ehci_readl(ehci,
&mehci->timer->gptimer1_ctrl));
if (timeleft) {
- ehci_writel(ehci, ehci_readl(ehci,
- &ehci->regs->command) | CMD_RUN,
- &ehci->regs->command);
- } else
- mehci->resume_again = 1;
+ if (mehci->bus_reset) {
+ ret = msm_hsic_reset_done(hcd);
+ if (ret) {
+ mehci->reset_again = 1;
+ dbg_log_event(NULL, "RESET: fail", 0);
+ }
+ } else {
+ ehci_writel(ehci, ehci_readl(ehci,
+ &ehci->regs->command) | CMD_RUN,
+ &ehci->regs->command);
+ }
+ } else {
+ if (mehci->bus_reset)
+ mehci->reset_again = 1;
+ else
+ mehci->resume_again = 1;
+ }
dbg_log_event(NULL, "FPR: timeleft", timeleft);
@@ -1041,6 +1044,83 @@
#ifdef CONFIG_PM
+#define RESET_RETRY_LIMIT 3
+#define RESET_SIGNAL_TIME_SOF_USEC (50 * 1000)
+#define RESET_SIGNAL_TIME_USEC (20 * 1000)
+static void ehci_hsic_reset_sof_bug_handler(struct usb_hcd *hcd, u32 val)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
+ struct msm_hsic_host_platform_data *pdata = mehci->dev->platform_data;
+ u32 __iomem *status_reg = &ehci->regs->port_status[0];
+ unsigned long flags;
+ int retries = 0, ret, cnt = RESET_SIGNAL_TIME_USEC;
+
+ if (pdata && pdata->swfi_latency)
+ pm_qos_update_request(&mehci->pm_qos_req_dma,
+ pdata->swfi_latency + 1);
+
+ mehci->bus_reset = 1;
+retry:
+ retries++;
+ dbg_log_event(NULL, "RESET: start", retries);
+ pr_debug("reset begin %d\n", retries);
+ mehci->reset_again = 0;
+ spin_lock_irqsave(&ehci->lock, flags);
+ ehci_writel(ehci, val, status_reg);
+ ehci_writel(ehci, GPT_LD(RESET_SIGNAL_TIME_USEC - 1),
+ &mehci->timer->gptimer0_ld);
+ ehci_writel(ehci, GPT_RESET | GPT_RUN,
+ &mehci->timer->gptimer0_ctrl);
+ ehci_writel(ehci, INTR_MASK | STS_GPTIMER0_INTERRUPT,
+ &ehci->regs->intr_enable);
+
+ ehci_writel(ehci, GPT_LD(RESET_SIGNAL_TIME_SOF_USEC - 1),
+ &mehci->timer->gptimer1_ld);
+ ehci_writel(ehci, GPT_RESET | GPT_RUN,
+ &mehci->timer->gptimer1_ctrl);
+
+ spin_unlock_irqrestore(&ehci->lock, flags);
+ wait_for_completion(&mehci->gpt0_completion);
+
+ if (!mehci->reset_again)
+ goto done;
+
+ if (handshake(ehci, status_reg, PORT_RESET, 0, 10 * 1000)) {
+ pr_err("reset handshake fatal error\n");
+ dbg_log_event(NULL, "RESET: fatal", retries);
+ goto fail;
+ }
+
+ if (retries < RESET_RETRY_LIMIT)
+ goto retry;
+
+ /* complete reset in tight loop */
+ pr_info("RESET in tight loop\n");
+ dbg_log_event(NULL, "RESET: tight", 0);
+
+ spin_lock_irqsave(&ehci->lock, flags);
+ ehci_writel(ehci, val, status_reg);
+ while (cnt--)
+ udelay(1);
+ ret = msm_hsic_reset_done(hcd);
+ spin_unlock_irqrestore(&ehci->lock, flags);
+ if (ret) {
+ pr_err("RESET in tight loop failed\n");
+ dbg_log_event(NULL, "RESET: tight failed", 0);
+ goto fail;
+ }
+
+done:
+ dbg_log_event(NULL, "RESET: done", retries);
+ pr_debug("reset completed\n");
+fail:
+ mehci->bus_reset = 0;
+ if (pdata && pdata->swfi_latency)
+ pm_qos_update_request(&mehci->pm_qos_req_dma,
+ PM_QOS_DEFAULT_VALUE);
+}
+
static int ehci_hsic_bus_suspend(struct usb_hcd *hcd)
{
struct msm_hsic_hcd *mehci = hcd_to_hsic(hcd);
@@ -1313,10 +1393,8 @@
.log_urb = dbg_log_event,
.dump_regs = dump_hsic_regs,
- .enable_ulpi_control = ehci_msm_enable_ulpi_control,
- .disable_ulpi_control = ehci_msm_disable_ulpi_control,
-
.set_autosuspend_delay = ehci_msm_set_autosuspend_delay,
+ .reset_sof_bug_handler = ehci_hsic_reset_sof_bug_handler,
};
static int msm_hsic_init_clocks(struct msm_hsic_hcd *mehci, u32 init)