ARM: Align with upstream
Undo our diff from upstream where upstreamed patches were
slightly different or merges introduced duplicate symbols, etc.
Change-Id: Iab263aa3d85b7b8b414b43afd6d70be358e6b7c9
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4678337..6839263 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1465,17 +1465,6 @@
on systems with an outer cache, the store buffer is drained
explicitly.
-config PL310_ERRATA_727915
- bool "Background Clean & Invalidate by Way operation can cause data corruption"
- depends on CACHE_L2X0
- help
- PL310 implements the Clean & Invalidate by Way L2 cache maintenance
- operation (offset 0x7FC). This operation runs in background so that
- PL310 can handle normal accesses while it is in progress. Under very
- rare circumstances, due to this erratum, write data can be lost when
- PL310 treats a cacheable write transaction during a Clean &
- Invalidate by Way operation.
-
config KSAPI
tristate "KSAPI support (EXPERIMENTAL)"
depends on ARCH_MSM_SCORPION || ARCH_MSM_KRAIT
@@ -1552,32 +1541,6 @@
source "drivers/pcmcia/Kconfig"
-config ARM_ERRATA_764369
- bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
- depends on CPU_V7 && SMP
- help
- This option enables the workaround for erratum 764369
- affecting Cortex-A9 MPCore with two or more processors (all
- current revisions). Under certain timing circumstances, a data
- cache line maintenance operation by MVA targeting an Inner
- Shareable memory region may fail to proceed up to either the
- Point of Coherency or to the Point of Unification of the
- system. This workaround adds a DSB instruction before the
- relevant cache maintenance functions and sets a specific bit
- in the diagnostic control register of the SCU.
-
-config PL310_ERRATA_769419
- bool "PL310 errata: no automatic Store Buffer drain"
- depends on CACHE_L2X0
- help
- On revisions of the PL310 prior to r3p2, the Store Buffer does
- not automatically drain. This can cause normal, non-cacheable
- writes to be retained when the memory system is idle, leading
- to suboptimal I/O performance for drivers using coherent DMA.
- This option adds a write barrier to the cpu_idle loop so that,
- on systems with an outer cache, the store buffer is drained
- explicitly.
-
endmenu
menu "Kernel Features"
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 27ecb3a..ac56f53 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -107,10 +107,6 @@
#define REV_PL310_R2P0 4
-#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
-#define L2X0_LATENCY_CTRL_RD_SHIFT 4
-#define L2X0_LATENCY_CTRL_WR_SHIFT 8
-
#define L2X0_PREFETCH_CTRL_OFFSET_SHIFT 0
#define L2X0_PREFETCH_CTRL_WRAP8_INC_SHIFT 23
#define L2X0_PREFETCH_CTRL_WRAP8_SHIFT 30
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 72c3c27..11a6f40 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -58,7 +58,6 @@
{
gic_init_bases(nr, start, dist, cpu, 0, NULL);
}
-void gic_set_irq_secure(unsigned int irq);
void msm_gic_save(void);
void msm_gic_restore(void);
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index f705388..e51c32b 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -9,8 +9,8 @@
*
* Page table mapping constructs and function prototypes
*/
-#ifndef __ASM_ARM_MACH_MAP_H
-#define __ASM_ARM_MACH_MAP_H
+#ifndef __ASM_MACH_MAP_H
+#define __ASM_MACH_MAP_H
#include <asm/io.h>
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index d1f9709..2a46914 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -222,18 +222,6 @@
extern void early_print(const char *str, ...);
extern void dump_machine_table(void);
-/*
- * Early command line parameters.
- */
-struct early_params {
- const char *arg;
- void (*fn)(char **p);
-};
-
-#define __early_param(name,fn) \
-static struct early_params __early_##fn __used \
-__attribute__((__section__(".early_param.init"))) = { name, fn }
-
#endif /* __KERNEL__ */
#endif
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 7d767c3..ae59e5a 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -239,7 +239,7 @@
/*
* The exception fixup table (might need resorting at runtime)
*/
- . = ALIGN(L1_CACHE_BYTES);
+ . = ALIGN(4);
__start___ex_table = .;
#ifdef CONFIG_MMU
*(__ex_table)
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 63b75df..c562f64 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -351,7 +351,7 @@
#endif
-ENTRY(Ldiv0)
+Ldiv0:
UNWIND(.fnstart)
UNWIND(.pad #4)
UNWIND(.save {lr})
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 21653f2..87fa3f2 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -70,7 +70,6 @@
#define arm_dma_limit ((phys_addr_t)~0)
#endif
-struct map_desc;
extern phys_addr_t arm_lowmem_limit;
void __init bootmem_init(void);