Merge changes I10e7c171,I784ffca6 into msm-3.0
* changes:
usb: rmnet: Add timestamps for SKB life cycle in UL and DL directions
usb: mdm_bridge: Reduce number of interrupts in TX Data Path
diff --git a/AndroidKernel.mk b/AndroidKernel.mk
index dcb81d7..97aa85d 100644
--- a/AndroidKernel.mk
+++ b/AndroidKernel.mk
@@ -8,6 +8,29 @@
KERNEL_HEADERS_INSTALL := $(KERNEL_OUT)/usr
KERNEL_MODULES_INSTALL := system
KERNEL_MODULES_OUT := $(TARGET_OUT)/lib/modules
+KERNEL_IMG=$(KERNEL_OUT)/arch/arm/boot/Image
+
+MSM_ARCH ?= $(shell $(PERL) -e 'while (<>) {$$a = $$1 if /CONFIG_ARCH_((?:MSM|QSD)[a-zA-Z0-9]+)=y/; $$r = $$1 if /CONFIG_MSM_SOC_REV_(?!NONE)(\w+)=y/;} print lc("$$a$$r\n");' $(KERNEL_CONFIG))
+KERNEL_USE_OF ?= $(shell $(PERL) -e '$$of = "n"; while (<>) { if (/CONFIG_USE_OF=y/) { $$of = "y"; break; } } print $$of;' kernel/arch/arm/configs/$(KERNEL_DEFCONFIG))
+
+ifeq "$(KERNEL_USE_OF)" "y"
+KERNEL_ZIMG = $(KERNEL_OUT)/arch/arm/boot/zImage
+DTB_FILE = $(KERNEL_OUT)/arch/arm/boot/$(MSM_ARCH).dtb
+DTS_FILE = $(KERNEL_OUT)/../../../../../../kernel/arch/arm/boot/dts/$(MSM_ARCH).dts
+FULL_KERNEL = $(KERNEL_OUT)/arch/arm/boot/$(MSM_ARCH)-zImage
+DTC = $(KERNEL_OUT)/scripts/dtc/dtc
+
+define append-dtb
+md $(KERNEL_OUT)/arch/arm/boot;\
+$(DTC) -p 1024 -O dtb -o $(DTB_FILE) $(DTS_FILE);\
+cat $(KERNEL_ZIMG) $(DTB_FILE) > $(FULL_KERNEL)
+endef
+else
+FULL_KERNEL = $(KERNEL_IMG)
+
+define append-dtb
+endef
+endif
ifeq ($(TARGET_USES_UNCOMPRESSED_KERNEL),true)
$(info Using uncompressed kernel)
@@ -47,6 +70,7 @@
$(MAKE) -C kernel O=../$(KERNEL_OUT) INSTALL_MOD_PATH=../../$(KERNEL_MODULES_INSTALL) ARCH=arm CROSS_COMPILE=arm-eabi- modules_install
$(mv-modules)
$(clean-module-folder)
+ $(append-dtb)
$(KERNEL_HEADERS_INSTALL): $(KERNEL_OUT) $(KERNEL_CONFIG)
$(MAKE) -C kernel O=../$(KERNEL_OUT) ARCH=arm CROSS_COMPILE=arm-eabi- headers_install
diff --git a/arch/arm/configs/msm8960-perf_defconfig b/arch/arm/configs/msm8960-perf_defconfig
index 90c83d4..da8b9df 100644
--- a/arch/arm/configs/msm8960-perf_defconfig
+++ b/arch/arm/configs/msm8960-perf_defconfig
@@ -49,6 +49,9 @@
CONFIG_MACH_MSM8627_MTP=y
CONFIG_MACH_APQ8064_SIM=y
CONFIG_MACH_APQ8064_RUMI3=y
+CONFIG_MACH_APQ8064_CDP=y
+CONFIG_MACH_APQ8064_MTP=y
+CONFIG_MACH_APQ8064_LIQUID=y
# CONFIG_MSM_STACKED_MEMORY is not set
CONFIG_KERNEL_PMEM_EBI_REGION=y
# CONFIG_MSM_FIQ_SUPPORT is not set
@@ -188,6 +191,8 @@
CONFIG_IP6_NF_MANGLE=y
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=y
@@ -320,9 +325,9 @@
CONFIG_FB_MSM_MDP40=y
CONFIG_FB_MSM_OVERLAY=y
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
+CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
-CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a698d43..32b4a99 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -170,6 +170,7 @@
select MSM_SCM if SMP
select MSM_DIRECT_SCLK_ACCESS
select REGULATOR
+ select MSM_RPM_REGULATOR
select MSM_RPM
select MSM_XO
select MSM_QDSP6_APR
@@ -246,6 +247,14 @@
select MSM_RPM_REGULATOR
select MULTI_IRQ_HANDLER
+config ARCH_MSM8625
+ bool "MSM8625"
+ select ARCH_MSM_CORTEX_A5
+ select CPU_V7
+ select MSM_GPIOMUX
+ select ARM_GIC
+ select ARCH_MSM_CORTEXMP
+ select MULTI_IRQ_HANDLER
endmenu
choice
@@ -295,6 +304,10 @@
select MSM_SMP
bool
+config ARCH_MSM_CORTEXMP
+ select MSM_SMP
+ bool
+
config ARCH_MSM_CORTEX_A5
bool
select HAVE_HW_BRKPT_RESERVED_RW_ACCESS
@@ -304,6 +317,8 @@
select MSM_DALRPC
select MSM_PROC_COMM_REGULATOR
select MULTI_IRQ_HANDLER
+ select ARM_GIC
+ select ARCH_MSM_CORTEXMP
config MSM_VIC
bool
@@ -433,6 +448,14 @@
help
Support for the Qualcomm MSM7627A Reference Design.
+config MACH_MSM8625_RUMI3
+ depends on ARCH_MSM8625
+ depends on !MSM_STACKED_MEMORY
+ default y
+ bool "MSM8625 RUMI3"
+ help
+ Support for the Qualcomm MSM8625 RUMI3 Emulation Platform.
+
config MACH_MSM7X30_SURF
depends on ARCH_MSM7X30
depends on !MSM_STACKED_MEMORY
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index eb02ac3..0b7e230 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -180,6 +180,7 @@
obj-$(CONFIG_ARCH_MSM8X60) += rpm-regulator-8660.o
obj-$(CONFIG_ARCH_MSM8960) += rpm-regulator-8960.o
obj-$(CONFIG_ARCH_MSM9615) += rpm-regulator-9615.o
+obj-$(CONFIG_ARCH_MSM8930) += rpm-regulator-8930.o
endif
ifdef CONFIG_MSM_SUBSYSTEM_RESTART
@@ -226,6 +227,8 @@
obj-$(CONFIG_MACH_MSM7X27A_FFA) += board-msm7x27a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
obj-$(CONFIG_MACH_MSM7627A_QRD1) += board-qrd7627a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
obj-$(CONFIG_MACH_MSM7627A_EVB) += board-qrd7627a.o board-msm7627a-storage.o board-msm7627a-bt.o board-msm7627a-camera.o board-msm7627a-display.o
+obj-$(CONFIG_ARCH_MSM8625) += devices-msm7x27a.o clock-pcom-lookup.o
+obj-$(CONFIG_MACH_MSM8625_RUMI3) += board-msm7x27a.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o memory_topology.o
obj-$(CONFIG_ARCH_MSM7X30) += clock-local.o clock-7x30.o acpuclock-7x30.o
obj-$(CONFIG_MACH_MSM7X25_SURF) += board-msm7x27.o devices-msm7x25.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index bc15a01..7ac2d9f 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -17,6 +17,10 @@
zreladdr-$(CONFIG_ARCH_MSM7X27A) := 0x00208000
params_phys-$(CONFIG_ARCH_MSM7X27A) := 0x00200100
+# MSM8625
+ zreladdr-$(CONFIG_ARCH_MSM8625) := 0x00208000
+params_phys-$(CONFIG_ARCH_MSM8625) := 0x00200100
+
# MSM7x30
zreladdr-$(CONFIG_ARCH_MSM7X30) := 0x00208000
params_phys-$(CONFIG_ARCH_MSM7X30) := 0x00200100
diff --git a/arch/arm/mach-msm/board-8930-regulator.c b/arch/arm/mach-msm/board-8930-regulator.c
index 765bd45..989fde3 100644
--- a/arch/arm/mach-msm/board-8930-regulator.c
+++ b/arch/arm/mach-msm/board-8930-regulator.c
@@ -257,6 +257,97 @@
.pin_ctrl = _pin_ctrl, \
}
+#define RPM_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, _default_uV, \
+ _peak_uA, _avg_uA, _pull_down, _pin_ctrl, _freq, _pin_fn, \
+ _force_mode, _power_mode, _state, _sleep_selectable, \
+ _always_on, _supply_regulator, _system_uA) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_modes_mask = _modes, \
+ .valid_ops_mask = _ops, \
+ .min_uV = _min_uV, \
+ .max_uV = _max_uV, \
+ .input_uV = _min_uV, \
+ .apply_uV = _apply_uV, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id), \
+ .consumer_supplies = vreg_consumers_##_id, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .default_uV = _default_uV, \
+ .peak_uA = _peak_uA, \
+ .avg_uA = _avg_uA, \
+ .pull_down_enable = _pull_down, \
+ .pin_ctrl = _pin_ctrl, \
+ .freq = RPM_VREG_FREQ_##_freq, \
+ .pin_fn = _pin_fn, \
+ .force_mode = _force_mode, \
+ .power_mode = _power_mode, \
+ .state = _state, \
+ .sleep_selectable = _sleep_selectable, \
+ .system_uA = _system_uA, \
+ }
+
+#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _init_peak_uA) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _init_peak_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _system_uA, _freq) \
+ RPM_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL \
+ | REGULATOR_MODE_IDLE, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE \
+ | REGULATOR_CHANGE_DRMS, 0, _max_uV, _system_uA, 0, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, _system_uA)
+
+#define RPM_VS(_id, _always_on, _pd, _sleep_selectable, _supply_regulator) \
+ RPM_INIT(_id, 0, 0, 0, REGULATOR_CHANGE_STATUS, 0, 0, 1000, 1000, _pd, \
+ RPM_VREG_PIN_CTRL_NONE, NONE, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, 0)
+
+#define RPM_NCP(_id, _always_on, _sleep_selectable, _min_uV, _max_uV, \
+ _supply_regulator, _freq) \
+ RPM_INIT(_id, _min_uV, _max_uV, 0, REGULATOR_CHANGE_VOLTAGE \
+ | REGULATOR_CHANGE_STATUS, 0, _max_uV, 1000, 1000, 0, \
+ RPM_VREG_PIN_CTRL_NONE, _freq, RPM_VREG_PIN_FN_8930_NONE, \
+ RPM_VREG_FORCE_MODE_8930_NONE, RPM_VREG_POWER_MODE_8930_PWM, \
+ RPM_VREG_STATE_OFF, _sleep_selectable, _always_on, \
+ _supply_regulator, 0)
+
+/* Pin control initialization */
+#define RPM_PC_INIT(_id, _always_on, _pin_fn, _pin_ctrl, _supply_regulator) \
+ { \
+ .init_data = { \
+ .constraints = { \
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
+ .always_on = _always_on, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(vreg_consumers_##_id##_PC), \
+ .consumer_supplies = vreg_consumers_##_id##_PC, \
+ .supply_regulator = _supply_regulator, \
+ }, \
+ .id = RPM_VREG_ID_PM8038_##_id##_PC, \
+ .pin_fn = RPM_VREG_PIN_FN_8930_##_pin_fn, \
+ .pin_ctrl = _pin_ctrl, \
+ }
+
#define GPIO_VREG(_id, _reg_name, _gpio_label, _gpio, _supply_regulator) \
[MSM8930_GPIO_VREG_ID_##_id] = { \
.init_data = { \
@@ -307,60 +398,58 @@
* ID name always_on pd min_uV max_uV en_t supply
* system_uA reg_ID
*/
- PM8XXX_SMPS(S1, "8038_s1", 1, 1, 1150000, 1150000, 500, NULL, 100000,
- 26),
- PM8XXX_SMPS(S2, "8038_s2", 1, 1, 1400000, 1400000, 500, NULL, 100000,
- 27),
- PM8XXX_SMPS(S3, "8038_s3", 0, 1, 1150000, 1150000, 500, NULL, 0, 28),
- PM8XXX_SMPS(S4, "8038_s4", 1, 1, 2200000, 2200000, 500, NULL, 100000,
- 29),
-
- PM8XXX_NLDO1200(L1, "8038_l1", 0, 1, 1300000, 1300000, 200, "8038_s2",
- 0, 1),
- PM8XXX_LDO(L2, "8038_l2", 0, 1, 1200000, 1200000, 200, "8038_s2", 0,
- 2),
- PM8XXX_LDO(L3, "8038_l3", 0, 1, 3075000, 3075000, 200, NULL, 0, 3),
- PM8XXX_LDO(L4, "8038_l4", 1, 1, 1800000, 1800000, 200, NULL, 10000,
- 4),
- PM8XXX_LDO(L5, "8038_l5", 0, 1, 2950000, 2950000, 200, NULL, 0, 5),
- PM8XXX_LDO(L6, "8038_l6", 0, 1, 2950000, 2950000, 200, NULL, 0, 6),
- PM8XXX_LDO(L7, "8038_l7", 0, 1, 2050000, 2050000, 200, "8038_s4", 0,
- 7),
- PM8XXX_LDO(L8, "8038_l8", 0, 1, 2800000, 2800000, 200, NULL, 0, 8),
- PM8XXX_LDO(L9, "8038_l9", 0, 1, 2850000, 2850000, 200, NULL, 0, 9),
- PM8XXX_LDO(L10, "8038_l10", 0, 1, 2900000, 2900000, 200, NULL, 0, 10),
- PM8XXX_LDO(L11, "8038_l11", 1, 1, 1800000, 1800000, 200, "8038_s4",
- 10000, 11),
- PM8XXX_LDO(L12, "8038_l12", 0, 1, 1200000, 1200000, 200, "8038_s2", 0,
- 12),
- PM8XXX_LDO(L14, "8038_l14", 0, 1, 1800000, 1800000, 200, NULL, 0, 13),
- PM8XXX_LDO(L15, "8038_l15", 0, 1, 1800000, 2950000, 200, NULL, 0, 14),
PM8XXX_NLDO1200(L16, "8038_l16", 0, 1, 1050000, 1050000, 200, "8038_s3",
- 0, 15),
- PM8XXX_LDO(L17, "8038_l17", 0, 1, 1800000, 2950000, 200, NULL, 0, 16),
- PM8XXX_LDO(L18, "8038_l18", 0, 1, 1800000, 1800000, 200, NULL, 0, 17),
+ 0, 0),
PM8XXX_NLDO1200(L19, "8038_l19", 0, 1, 1050000, 1050000, 200, "8038_s3",
- 0, 18),
- PM8XXX_NLDO1200(L20, "8038_l20", 1, 1, 1200000, 1200000, 200, "8038_s2",
- 10000, 19),
- PM8XXX_LDO(L21, "8038_l21", 0, 1, 1900000, 1900000, 200, "8038_s4", 0,
- 20),
- PM8XXX_LDO(L22, "8038_l22", 1, 1, 2950000, 2950000, 200, NULL, 10000,
- 21),
- PM8XXX_LDO(L23, "8038_l23", 0, 1, 1800000, 1800000, 200, "8038_s4", 0,
- 22),
- PM8XXX_NLDO1200(L24, "8038_l24", 1, 1, 1150000, 1150000, 200, "8038_s2",
- 10000, 23),
- PM8XXX_LDO(L26, "8038_l26", 1, 1, 1050000, 1050000, 200, "8038_s2",
- 10000, 24),
+ 0, 1),
PM8XXX_NLDO1200(L27, "8038_l27", 0, 1, 1050000, 1050000, 200, "8038_s3",
- 0, 25),
+ 0, 2),
+};
- /* ID name always_on pd en_t supply reg_ID */
- PM8XXX_VS(LVS1, "8038_lvs1", 0, 1, 0, "8038_l11", 32),
- PM8XXX_VS(LVS2, "8038_lvs2", 0, 1, 0, "8038_l11", 33),
+static struct rpm_regulator_init_data
+msm8930_rpm_regulator_init_data[] __devinitdata = {
+ /* ID a_on pd ss min_uV max_uV supply sys_uA freq */
+ RPM_SMPS(S1, 1, 1, 1, 500000, 1150000, NULL, 100000, 4p80),
+ RPM_SMPS(S2, 1, 1, 0, 1400000, 1400000, NULL, 100000, 1p60),
+ RPM_SMPS(S3, 0, 1, 0, 1150000, 1150000, NULL, 100000, 3p20),
+ RPM_SMPS(S4, 1, 1, 0, 2200000, 2200000, NULL, 100000, 1p60),
+ /* ID a_on pd ss min_uV max_uV supply sys_uA init_ip */
+ RPM_LDO(L1, 0, 1, 0, 1300000, 1300000, "8038_s2", 0, 0),
+ RPM_LDO(L2, 0, 1, 0, 1200000, 1200000, "8038_s2", 0, 0),
+ RPM_LDO(L3, 0, 1, 0, 3075000, 3075000, NULL, 0, 0),
+ RPM_LDO(L4, 1, 1, 0, 1800000, 1800000, NULL, 10000, 10000),
+ RPM_LDO(L5, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
+ RPM_LDO(L6, 0, 1, 0, 2950000, 2950000, NULL, 0, 0),
+ RPM_LDO(L7, 0, 1, 0, 2050000, 2050000, "8038_s4", 0, 0),
+ RPM_LDO(L8, 0, 1, 0, 2800000, 2800000, NULL, 0, 0),
+ RPM_LDO(L9, 0, 1, 0, 2850000, 2850000, NULL, 0, 0),
+ RPM_LDO(L10, 0, 1, 0, 2900000, 2900000, NULL, 0, 0),
+ RPM_LDO(L11, 1, 1, 0, 1800000, 1800000, "8038_s4", 10000, 10000),
+ RPM_LDO(L12, 0, 1, 0, 1200000, 1200000, "8038_s2", 0, 0),
+ RPM_LDO(L14, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
+ RPM_LDO(L15, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
+ RPM_LDO(L17, 0, 1, 0, 1800000, 2950000, NULL, 0, 0),
+ RPM_LDO(L18, 0, 1, 0, 1800000, 1800000, NULL, 0, 0),
+ RPM_LDO(L20, 1, 1, 0, 1200000, 1200000, "8038_s2", 10000, 10000),
+ RPM_LDO(L21, 0, 1, 0, 1900000, 1900000, "8038_s4", 0, 0),
+ RPM_LDO(L22, 1, 1, 0, 1850000, 2950000, NULL, 10000, 10000),
+ RPM_LDO(L23, 1, 1, 1, 1800000, 1800000, "8038_s4", 0, 0),
+ RPM_LDO(L24, 1, 1, 1, 500000, 1150000, "8038_s2", 10000, 10000),
+ RPM_LDO(L26, 1, 1, 0, 1050000, 1050000, "8038_s2", 10000, 10000),
+
+ /* ID a_on pd ss supply */
+ RPM_VS(LVS1, 0, 1, 0, "8038_l11"),
+ RPM_VS(LVS2, 0, 1, 0, "8038_l11"),
};
int msm8930_pm8038_regulator_pdata_len __devinitdata =
ARRAY_SIZE(msm8930_pm8038_regulator_pdata);
+
+struct rpm_regulator_platform_data msm8930_rpm_regulator_pdata __devinitdata = {
+ .init_data = msm8930_rpm_regulator_init_data,
+ .num_regulators = ARRAY_SIZE(msm8930_rpm_regulator_init_data),
+ .version = RPM_VREG_VERSION_8930,
+ .vreg_id_vdd_mem = RPM_VREG_ID_PM8038_L24,
+ .vreg_id_vdd_dig = RPM_VREG_ID_PM8038_S1,
+};
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index cd51397..75d0fb2 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -1761,14 +1761,10 @@
.name = "rpm-regulator",
.id = -1,
.dev = {
- /*
- * TODO: When physical 8930/PM8038 hardware becomes
- * available, replace msm_rpm_regulator_pdata
- * with 8930 rpm regulator object.
- */
-#if !defined(MSM8930_PHASE_2)
-
+#ifndef MSM8930_PHASE_2
.platform_data = &msm_rpm_regulator_pdata,
+#else
+ .platform_data = &msm8930_rpm_regulator_pdata,
#endif
},
};
diff --git a/arch/arm/mach-msm/board-8930.h b/arch/arm/mach-msm/board-8930.h
index 8e20903..1feb5b8 100644
--- a/arch/arm/mach-msm/board-8930.h
+++ b/arch/arm/mach-msm/board-8930.h
@@ -75,6 +75,9 @@
extern struct gpio_regulator_platform_data
msm8930_gpio_regulator_pdata[] __devinitdata;
+extern struct rpm_regulator_platform_data
+ msm8930_rpm_regulator_pdata __devinitdata;
+
#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
enum {
GPIO_EXPANDER_IRQ_BASE = (PM8038_IRQ_BASE + PM8038_NR_IRQS),
diff --git a/arch/arm/mach-msm/board-8960-storage.c b/arch/arm/mach-msm/board-8960-storage.c
index 8b43d38..4e4d26ef 100644
--- a/arch/arm/mach-msm/board-8960-storage.c
+++ b/arch/arm/mach-msm/board-8960-storage.c
@@ -121,8 +121,8 @@
static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = {
{TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
- {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_DOWN},
- {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_DOWN}
+ {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
+ {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
};
/* SDC3 pad data */
diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c
index e1ff3dd..700d165 100644
--- a/arch/arm/mach-msm/board-9615.c
+++ b/arch/arm/mach-msm/board-9615.c
@@ -245,10 +245,9 @@
#define USB_5V_EN 3
#define PM_USB_5V_EN PM8018_GPIO_PM_TO_SYS(USB_5V_EN)
-static void msm_hsusb_vbus_power(bool on)
+static int msm_hsusb_vbus_power(bool on)
{
- int rc;
- static bool vbus_is_on;
+ int rc = 0;
struct pm_gpio usb_vbus = {
.direction = PM_GPIO_DIR_OUT,
.pull = PM_GPIO_PULL_NO,
@@ -260,21 +259,18 @@
.inv_int_pol = 0,
};
- if (vbus_is_on == on)
- return;
-
if (on) {
rc = pm8xxx_gpio_config(PM_USB_5V_EN, &usb_vbus);
if (rc) {
pr_err("failed to config usb_5v_en gpio\n");
- return;
+ return rc;
}
rc = gpio_request(PM_USB_5V_EN,
"usb_5v_en");
if (rc < 0) {
pr_err("failed to request usb_5v_en gpio\n");
- return;
+ return rc;
}
rc = gpio_direction_output(PM_USB_5V_EN, 1);
@@ -284,13 +280,12 @@
goto free_usb_5v_en;
}
- vbus_is_on = true;
- return;
+ return rc;
}
gpio_set_value(PM_USB_5V_EN, 0);
free_usb_5v_en:
gpio_free(PM_USB_5V_EN);
- vbus_is_on = false;
+ return rc;
}
static int shelby_phy_init_seq[] = {
diff --git a/arch/arm/mach-msm/board-msm7x27a.c b/arch/arm/mach-msm/board-msm7x27a.c
index 77db796..8b50c53 100644
--- a/arch/arm/mach-msm/board-msm7x27a.c
+++ b/arch/arm/mach-msm/board-msm7x27a.c
@@ -14,6 +14,7 @@
#include <linux/gpio_event.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <mach/msm_hsusb.h>
@@ -677,6 +678,11 @@
&msm_gsbi1_qup_i2c_device,
};
+static struct platform_device *msm8625_rumi3_devices[] __initdata = {
+ &msm8625_device_dmov,
+ &msm8625_device_uart1,
+};
+
static struct platform_device *surf_ffa_devices[] __initdata = {
&msm_device_dmov,
&msm_device_smd,
@@ -1052,6 +1058,13 @@
ARRAY_SIZE(rumi_sim_devices));
}
+static void __init msm8625_rumi3_init(void)
+{
+ msm7x2x_misc_init();
+ platform_add_devices(msm8625_rumi3_devices,
+ ARRAY_SIZE(msm8625_rumi3_devices));
+}
+
#define LED_GPIO_PDM 96
#define UART1DM_RX_GPIO 45
@@ -1210,3 +1223,11 @@
.init_early = msm7x2x_init_early,
.handle_irq = vic_handle_irq,
MACHINE_END
+MACHINE_START(MSM8625_RUMI3, "QCT MSM8625 RUMI3")
+ .boot_params = PHYS_OFFSET + 0x100,
+ .map_io = msm8625_map_io,
+ .init_irq = msm8625_init_irq,
+ .init_machine = msm8625_rumi3_init,
+ .timer = &msm_timer,
+ .handle_irq = gic_handle_irq,
+MACHINE_END
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index 9170842..508a496 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -120,11 +120,8 @@
#define SRC_SEL_gnd 7 /* No clock */
/* Clock declaration macros. */
-#define MN_MODE_DUAL_EDGE 0x2
-#define MD8(m, n) (BVAL(15, 8, m) | BVAL(7, 0, ~(n)))
#define N8(msb, lsb, m, n) (BVAL(msb, lsb, ~(n-m)) | BVAL(6, 5, \
(MN_MODE_DUAL_EDGE * !!(n))))
-#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
#define N16(m, n) (BVAL(31, 16, ~(n-m)) | BVAL(6, 5, \
(MN_MODE_DUAL_EDGE * !!(n))))
#define SPDIV(s, d) (BVAL(4, 3, d-1) | BVAL(2, 0, s))
@@ -156,7 +153,7 @@
{ \
.freq_hz = f, \
.src_clk = &s##_clk.c, \
- .md_val = MD8(m, n), \
+ .md_val = MD8(8, m, 0, n), \
.ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
.mnd_en_mask = BIT(8) * !!(n), \
}
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index 09f70f1..8e8a966 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -353,57 +353,6 @@
#define MN_MODE_DUAL_EDGE 0x2
-/* MD Registers */
-#define MD4(m_lsb, m, n_lsb, n) \
- (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
-#define MD8(m_lsb, m, n_lsb, n) \
- (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
-#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
-
-/* NS Registers */
-#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(n_msb, n_lsb, ~(n-m)) \
- | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
- | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
-
-#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
- | BVAL(s_msb, s_lsb, s))
-
-#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
-
-#define NS_DIV(d_msb , d_lsb, d) \
- BVAL(d_msb, d_lsb, (d-1))
-
-#define NS_SRC_SEL(s_msb, s_lsb, s) \
- BVAL(s_msb, s_lsb, s)
-
-#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
- (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
- | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
- | BVAL((s0_lsb+2), s0_lsb, s) \
- | BVAL((s1_lsb+2), s1_lsb, s))
-
-#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
- (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
- | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
- | BVAL((s0_lsb+2), s0_lsb, s) \
- | BVAL((s1_lsb+2), s1_lsb, s))
-
-#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
- s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
- (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
- | BVAL(s0_msb, s0_lsb, s) \
- | BVAL(s1_msb, s1_lsb, s))
-
-/* CC Registers */
-#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
-#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
- ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
- | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
- * !!(n))
-
struct pll_rate {
const uint32_t l_val;
const uint32_t m_val;
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index d61547fa..94fafda 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -262,58 +262,6 @@
/*
* Clock frequency definitions and macros
*/
-#define MN_MODE_DUAL_EDGE 0x2
-
-/* MD Registers */
-#define MD4(m_lsb, m, n_lsb, n) \
- (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
-#define MD8(m_lsb, m, n_lsb, n) \
- (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
-#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
-
-/* NS Registers */
-#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(n_msb, n_lsb, ~(n-m)) \
- | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
- | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
-
-#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
- | BVAL(s_msb, s_lsb, s))
-
-#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
-
-#define NS_DIV(d_msb , d_lsb, d) \
- BVAL(d_msb, d_lsb, (d-1))
-
-#define NS_SRC_SEL(s_msb, s_lsb, s) \
- BVAL(s_msb, s_lsb, s)
-
-#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
- (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
- | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
- | BVAL((s0_lsb+2), s0_lsb, s) \
- | BVAL((s1_lsb+2), s1_lsb, s))
-
-#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
- (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
- | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
- | BVAL((s0_lsb+2), s0_lsb, s) \
- | BVAL((s1_lsb+2), s1_lsb, s))
-
-#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
- s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
- (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
- | BVAL(s0_msb, s0_lsb, s) \
- | BVAL(s1_msb, s1_lsb, s))
-
-/* CC Registers */
-#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
-#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
- ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
- | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
- * !!(n))
enum vdd_dig_levels {
VDD_DIG_NONE,
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 3e57ebc..5ddeef9 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -174,22 +174,6 @@
#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
-#define MN_MODE_DUAL_EDGE 0x2
-
-/* MD Registers */
-#define MD8(m_lsb, m, n_lsb, n) \
- (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
-#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
-
-/* NS Registers */
-#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
- (BVAL(n_msb, n_lsb, ~(n-m)) \
- | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
- | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
-
-#define NS_SRC_SEL(s_msb, s_lsb, s) \
- BVAL(s_msb, s_lsb, s)
-
enum vdd_dig_levels {
VDD_DIG_NONE,
VDD_DIG_LOW,
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index 2a1c013..050ec41 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -648,7 +648,7 @@
ns_val = readl_relaxed(clk->ns_reg) & ns_mask;
for (freq = clk->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
if ((freq->ns_val & ns_mask) == ns_val &&
- (freq->mnd_en_mask || freq->md_val == md_val)) {
+ (!freq->mnd_en_mask || freq->md_val == md_val)) {
pr_info("%s rate=%d\n", clk->c.dbg_name, freq->freq_hz);
break;
}
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index a561802d..9195fea 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -23,6 +23,59 @@
#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
+#define MN_MODE_DUAL_EDGE 0x2
+
+/* MD Registers */
+#define MD4(m_lsb, m, n_lsb, n) \
+ (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
+#define MD8(m_lsb, m, n_lsb, n) \
+ (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
+#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
+
+/* NS Registers */
+#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
+ (BVAL(n_msb, n_lsb, ~(n-m)) \
+ | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
+ | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
+
+#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
+ (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
+ | BVAL(s_msb, s_lsb, s))
+
+#define NS_DIVSRC(d_msb, d_lsb, d, s_msb, s_lsb, s) \
+ (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
+
+#define NS_DIV(d_msb, d_lsb, d) \
+ BVAL(d_msb, d_lsb, (d-1))
+
+#define NS_SRC_SEL(s_msb, s_lsb, s) \
+ BVAL(s_msb, s_lsb, s)
+
+#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
+ (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
+ | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
+ | BVAL((s0_lsb+2), s0_lsb, s) \
+ | BVAL((s1_lsb+2), s1_lsb, s))
+
+#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
+ (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
+ | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
+ | BVAL((s0_lsb+2), s0_lsb, s) \
+ | BVAL((s1_lsb+2), s1_lsb, s))
+
+#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
+ s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
+ (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
+ | BVAL(s0_msb, s0_lsb, s) \
+ | BVAL(s1_msb, s1_lsb, s))
+
+/* CC Registers */
+#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
+#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
+ ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
+ | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
+ * !!(n))
+
/*
* Halt/Status Checking Mode Macros
*/
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 91121e6..5a9b199 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -1,7 +1,7 @@
/* arch/arm/mach-msm/clock.h
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -136,6 +136,7 @@
extern struct clock_init_data msm8960_dummy_clock_init_data;
extern struct clock_init_data msm8x60_clock_init_data;
extern struct clock_init_data qds8x50_clock_init_data;
+extern struct clock_init_data msm8625_dummy_clock_init_data;
void msm_clock_init(struct clock_init_data *data);
int vote_vdd_level(struct clk_vdd_class *vdd_class, int level);
diff --git a/arch/arm/mach-msm/devices-msm7x27a.c b/arch/arm/mach-msm/devices-msm7x27a.c
index 104b2e0..6a59b08 100644
--- a/arch/arm/mach-msm/devices-msm7x27a.c
+++ b/arch/arm/mach-msm/devices-msm7x27a.c
@@ -16,12 +16,14 @@
#include <linux/msm_kgsl.h>
#include <linux/regulator/machine.h>
#include <linux/init.h>
+#include <linux/irq.h>
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include <mach/board.h>
#include <mach/dma.h>
#include <mach/dal_axi.h>
#include <asm/mach/flash.h>
+#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/mmc.h>
#include <mach/rpc_hsusb.h>
@@ -786,15 +788,129 @@
.num_resources = ARRAY_SIZE(gpio_resources),
};
-static int msm7627a_init_gpio(void)
-{
- platform_device_register(&msm_device_gpio);
- return 0;
-}
-postcore_initcall(msm7627a_init_gpio);
+struct platform_device *msm_footswitch_devices[] = {
+ FS_PCOM(FS_GFX3D, "fs_gfx3d"),
+};
+unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
+
+/* MSM8625 Devices */
+
+static struct resource msm8625_resources_uart1[] = {
+ {
+ .start = MSM8625_INT_UART1,
+ .end = MSM8625_INT_UART1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MSM_UART1_PHYS,
+ .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device msm8625_device_uart1 = {
+ .name = "msm_serial",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(msm8625_resources_uart1),
+ .resource = msm8625_resources_uart1,
+};
+
+static struct resource msm8625_dmov_resource[] = {
+ {
+ .start = MSM8625_INT_ADM_AARM,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = 0xA9700000,
+ .end = 0xA9700000 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device msm8625_device_dmov = {
+ .name = "msm_dmov",
+ .id = -1,
+ .resource = msm8625_dmov_resource,
+ .num_resources = ARRAY_SIZE(msm8625_dmov_resource),
+ .dev = {
+ .platform_data = &msm_dmov_pdata,
+ },
+};
+
+static struct clk_lookup msm_clock_8625_dummy[] = {
+ CLK_DUMMY("core_clk", adm_clk.c, "msm_dmov", 0),
+ CLK_DUMMY("adsp_clk", adsp_clk.c, NULL, 0),
+ CLK_DUMMY("ahb_m_clk", ahb_m_clk.c, NULL, 0),
+ CLK_DUMMY("ahb_s_clk", ahb_s_clk.c, NULL, 0),
+ CLK_DUMMY("cam_m_clk", cam_m_clk.c, NULL, 0),
+ CLK_DUMMY("csi_clk", csi1_clk.c, NULL, 0),
+ CLK_DUMMY("csi_pclk", csi1_p_clk.c, NULL, 0),
+ CLK_DUMMY("csi_vfe_clk", csi1_vfe_clk.c, NULL, 0),
+ CLK_DUMMY("dsi_byte_clk", dsi_byte_clk.c, NULL, 0),
+ CLK_DUMMY("dsi_clk", dsi_clk.c, NULL, 0),
+ CLK_DUMMY("dsi_esc_clk", dsi_esc_clk.c, NULL, 0),
+ CLK_DUMMY("dsi_pixel_clk", dsi_pixel_clk.c, NULL, 0),
+ CLK_DUMMY("dsi_ref_clk", dsi_ref_clk.c, NULL, 0),
+ CLK_DUMMY("ebi1_clk", ebi1_clk.c, NULL, 0),
+ CLK_DUMMY("ebi2_clk", ebi2_clk.c, NULL, 0),
+ CLK_DUMMY("ecodec_clk", ecodec_clk.c, NULL, 0),
+ CLK_DUMMY("gp_clk", gp_clk.c, NULL, 0),
+ CLK_DUMMY("core_clk", gsbi1_qup_clk.c, "qup_i2c.0", 0),
+ CLK_DUMMY("core_clk", gsbi2_qup_clk.c, "qup_i2c.1", 0),
+ CLK_DUMMY("iface_clk", gsbi1_qup_p_clk.c, "qup_i2c.0", 0),
+ CLK_DUMMY("iface_clk", gsbi2_qup_p_clk.c, "qup_i2c.1", 0),
+ CLK_DUMMY("icodec_rx_clk", icodec_rx_clk.c, NULL, 0),
+ CLK_DUMMY("icodec_tx_clk", icodec_tx_clk.c, NULL, 0),
+ CLK_DUMMY("mem_clk", imem_clk.c, NULL, 0),
+ CLK_DUMMY("mddi_clk", pmdh_clk.c, NULL, 0),
+ CLK_DUMMY("mdp_clk", mdp_clk.c, NULL, 0),
+ CLK_DUMMY("mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk.c, NULL, 0),
+ CLK_DUMMY("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL, 0),
+ CLK_DUMMY("mdp_vsync_clk", mdp_vsync_clk.c, NULL, 0),
+ CLK_DUMMY("mdp_dsi_pclk", mdp_dsi_p_clk.c, NULL, 0),
+ CLK_DUMMY("pbus_clk", pbus_clk.c, NULL, 0),
+ CLK_DUMMY("pcm_clk", pcm_clk.c, NULL, 0),
+ CLK_DUMMY("sdac_clk", sdac_clk.c, NULL, 0),
+ CLK_DUMMY("core_clk", sdc1_clk.c, "msm_sdcc.1", 0),
+ CLK_DUMMY("iface_clk", sdc1_p_clk.c, "msm_sdcc.1", 0),
+ CLK_DUMMY("core_clk", sdc2_clk.c, "msm_sdcc.2", 0),
+ CLK_DUMMY("iface_clk", sdc2_p_clk.c, "msm_sdcc.2", 0),
+ CLK_DUMMY("core_clk", sdc3_clk.c, "msm_sdcc.3", 0),
+ CLK_DUMMY("iface_clk", sdc3_p_clk.c, "msm_sdcc.3", 0),
+ CLK_DUMMY("core_clk", sdc4_clk.c, "msm_sdcc.4", 0),
+ CLK_DUMMY("iface_clk", sdc4_p_clk.c, "msm_sdcc.4", 0),
+ CLK_DUMMY("ref_clk", tsif_ref_clk.c, "msm_tsif.0", 0),
+ CLK_DUMMY("iface_clk", tsif_p_clk.c, "msm_tsif.0", 0),
+ CLK_DUMMY("core_clk", uart1_clk.c, "msm_serial.0", 0),
+ CLK_DUMMY("core_clk", uart2_clk.c, "msm_serial.1", 0),
+ CLK_DUMMY("core_clk", uart1dm_clk.c, "msm_serial_hs.0", 0),
+ CLK_DUMMY("core_clk", uart2dm_clk.c, "msm_serial_hsl.0", 0),
+ CLK_DUMMY("usb_hs_core_clk", usb_hs_core_clk.c, NULL, 0),
+ CLK_DUMMY("usb_hs2_clk", usb_hs2_clk.c, NULL, 0),
+ CLK_DUMMY("usb_hs_clk", usb_hs_clk.c, NULL, 0),
+ CLK_DUMMY("usb_hs_pclk", usb_hs_p_clk.c, NULL, 0),
+ CLK_DUMMY("usb_phy_clk", usb_phy_clk.c, NULL, 0),
+ CLK_DUMMY("vdc_clk", vdc_clk.c, NULL, 0),
+ CLK_DUMMY("ebi1_acpu_clk", ebi_acpu_clk.c, NULL, 0),
+ CLK_DUMMY("ebi1_lcdc_clk", ebi_lcdc_clk.c, NULL, 0),
+ CLK_DUMMY("ebi1_mddi_clk", ebi_mddi_clk.c, NULL, 0),
+ CLK_DUMMY("ebi1_usb_clk", ebi_usb_clk.c, NULL, 0),
+ CLK_DUMMY("ebi1_vfe_clk", ebi_vfe_clk.c, NULL, 0),
+ CLK_DUMMY("mem_clk", ebi_adm_clk.c, "msm_dmov", 0),
+};
+
+struct clock_init_data msm8625_dummy_clock_init_data __initdata = {
+ .table = msm_clock_8625_dummy,
+ .size = ARRAY_SIZE(msm_clock_8625_dummy),
+};
int __init msm7x2x_misc_init(void)
{
+ if (machine_is_msm8625_rumi3()) {
+ msm_clock_init(&msm8625_dummy_clock_init_data);
+ return 0;
+ }
+
msm_clock_init(&msm7x27a_clock_init_data);
if (cpu_is_msm7x27aa())
acpuclk_init(&acpuclk_7x27aa_soc_data);
@@ -826,13 +942,37 @@
void __init msm_common_io_init(void)
{
msm_map_common_io();
+ if (socinfo_init() < 0)
+ pr_err("%s: socinfo_init() failed!\n", __func__);
msm7x27x_cache_init();
+}
+
+void __init msm8625_init_irq(void)
+{
+ gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+ (void *)MSM_QGIC_CPU_BASE);
+
+ /* Edge trigger PPIs
+ */
+ writel_relaxed(0x555555F5, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+ writel_relaxed(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+ mb();
+}
+
+void __init msm8625_map_io(void)
+{
+ msm_map_msm8625_io();
+
if (socinfo_init() < 0)
pr_err("%s: socinfo_init() failed!\n", __func__);
}
-struct platform_device *msm_footswitch_devices[] = {
- FS_PCOM(FS_GFX3D, "fs_gfx3d"),
-};
-unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
+static int msm7627a_init_gpio(void)
+{
+ platform_device_register(&msm_device_gpio);
+ return 0;
+}
+postcore_initcall(msm7627a_init_gpio);
+
diff --git a/arch/arm/mach-msm/devices-msm7x2xa.h b/arch/arm/mach-msm/devices-msm7x2xa.h
index a9c87ba..a59ade3 100644
--- a/arch/arm/mach-msm/devices-msm7x2xa.h
+++ b/arch/arm/mach-msm/devices-msm7x2xa.h
@@ -23,4 +23,6 @@
extern struct platform_device msm7x27a_device_csic0;
extern struct platform_device msm7x27a_device_csic1;
extern struct platform_device msm7x27a_device_clkctl;
+void __init msm8625_init_irq(void);
+void __init msm8625_map_io(void);
#endif
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index bbb815e..176d14a 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -41,6 +41,7 @@
extern struct platform_device msm_device_uart1;
extern struct platform_device msm_device_uart2;
extern struct platform_device msm_device_uart3;
+extern struct platform_device msm8625_device_uart1;
extern struct platform_device msm_device_uart_dm1;
extern struct platform_device msm_device_uart_dm2;
@@ -128,6 +129,7 @@
extern struct platform_device msm8960_device_dmov;
extern struct platform_device apq8064_device_dmov;
extern struct platform_device msm9615_device_dmov;
+extern struct platform_device msm8625_device_dmov;
extern struct platform_device msm_device_dmov_adm0;
extern struct platform_device msm_device_dmov_adm1;
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 7ada69a..b716a6c 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -20,6 +20,8 @@
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
#include <asm/mach/irq.h>
@@ -165,6 +167,7 @@
DECLARE_BITMAP(enabled_irqs, NR_MSM_GPIOS);
DECLARE_BITMAP(wake_irqs, NR_MSM_GPIOS);
DECLARE_BITMAP(dual_edge_irqs, NR_MSM_GPIOS);
+ struct irq_domain domain;
};
static DEFINE_SPINLOCK(tlmm_lock);
@@ -223,6 +226,21 @@
return 0;
}
+#ifdef CONFIG_OF
+static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct msm_gpio_dev *g_dev = to_msm_gpio_dev(chip);
+ struct irq_domain *domain = &g_dev->domain;
+ return domain->irq_base + (offset - chip->base);
+}
+
+static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
+{
+ struct msm_gpio_dev *g_dev = to_msm_gpio_dev(chip);
+ struct irq_domain *domain = &g_dev->domain;
+ return irq - domain->irq_base;
+}
+#else
static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
return MSM_GPIO_TO_INT(offset - chip->base);
@@ -232,6 +250,7 @@
{
return irq - MSM_GPIO_TO_INT(chip->base);
}
+#endif
static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
{
@@ -673,6 +692,48 @@
}
EXPORT_SYMBOL(msm_gpio_install_direct_irq);
+#ifdef CONFIG_OF
+static int msm_gpio_domain_dt_translate(struct irq_domain *d,
+ struct device_node *controller,
+ const u32 *intspec,
+ unsigned int intsize,
+ unsigned long *out_hwirq,
+ unsigned int *out_type)
+{
+ if (d->of_node != controller)
+ return -EINVAL;
+ if (intsize != 2)
+ return -EINVAL;
+
+ /* hwirq value */
+ *out_hwirq = intspec[0];
+
+ /* irq flags */
+ *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
+ return 0;
+}
+
+static struct irq_domain_ops msm_gpio_irq_domain_ops = {
+ .dt_translate = msm_gpio_domain_dt_translate,
+};
+
+int __init msm_gpio_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_domain *domain = &msm_gpio.domain;
+
+ domain->irq_base = irq_domain_find_free_range(0, NR_MSM_GPIOS);
+ domain->nr_irq = NR_MSM_GPIOS;
+ domain->of_node = of_node_get(node);
+ domain->priv = &msm_gpio;
+ domain->ops = &msm_gpio_irq_domain_ops;
+ irq_domain_add(domain);
+ pr_debug("%s: irq_base = %u\n", __func__, domain->irq_base);
+
+ return 0;
+}
+#endif
+
MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 0eee135..d9bc654 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -448,6 +448,7 @@
void msm_map_msm7x30_io(void);
void msm_map_fsm9xxx_io(void);
void msm_map_copper_io(void);
+void msm_map_msm8625_io(void);
void msm_init_irq(void);
void msm_copper_init_irq(void);
void vic_handle_irq(struct pt_regs *regs);
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index fa69b9f..5385f35 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
* Author: Mike Lockwood <lockwood@android.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -238,4 +238,9 @@
}
#endif
+#ifdef CONFIG_OF
+int __init msm_gpio_of_init(struct device_node *node,
+ struct device_node *parent);
+#endif
+
#endif /* __ASM_ARCH_MSM_GPIO_H */
diff --git a/arch/arm/mach-msm/include/mach/irqs-7xxx.h b/arch/arm/mach-msm/include/mach/irqs-7xxx.h
index 21ae436..c90b4ee 100644
--- a/arch/arm/mach-msm/include/mach/irqs-7xxx.h
+++ b/arch/arm/mach-msm/include/mach/irqs-7xxx.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*/
@@ -79,11 +79,5 @@
#define INT_CE_IRQ (32 + 24)
#endif
-/* 7x00A uses 122, but 7x25 has up to 132. */
-#define NR_GPIO_IRQS 133
-#define NR_MSM_IRQS 64
-#define NR_BOARD_IRQS 64
-#define NR_MSM_GPIOS NR_GPIO_IRQS
-
#define INT_ADSP_A11_SMSM INT_ADSP_A11
#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8625.h b/arch/arm/mach-msm/include/mach/irqs-8625.h
new file mode 100644
index 0000000..3ff73eb
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8625.h
@@ -0,0 +1,89 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MSM_IRQS_8625_H
+#define __ASM_ARCH_MSM_IRQS_8625_H
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+/* As per QGIC2 PPI 16 aka 0 is reserved */
+#define MSM8625_INT_A5_PMU_IRQ (GIC_PPI_START + 1)
+#define MSM8625_INT_DEBUG_TIMER_EXP (GIC_PPI_START + 2)
+#define MSM8625_INT_GP_TIMER_EXP (GIC_PPI_START + 3)
+#define MSM8625_INT_COMMRX (GIC_PPI_START + 4)
+#define MSM8625_INT_COMMTX (GIC_PPI_START + 5)
+
+/* rest of the PPI's not used
+ */
+
+#define MSM8625_INT_A9_M2A_0 (GIC_SPI_START + 0)
+#define MSM8625_INT_A9_M2A_1 (GIC_SPI_START + 1)
+#define MSM8625_INT_A9_M2A_2 (GIC_SPI_START + 2)
+#define MSM8625_INT_A9_M2A_3 (GIC_SPI_START + 3)
+#define MSM8625_INT_A9_M2A_4 (GIC_SPI_START + 4)
+#define MSM8625_INT_A9_M2A_5 (GIC_SPI_START + 5)
+#define MSM8625_INT_A9_M2A_6 (GIC_SPI_START + 6)
+#define MSM8625_INT_ACSR_MP_CORE_IPC0 (GIC_SPI_START + 7)
+#define MSM8625_INT_ACSR_MP_CORE_IPC1 (GIC_SPI_START + 8)
+#define MSM8625_INT_UART1 (GIC_SPI_START + 9)
+#define MSM8625_INT_UART2 (GIC_SPI_START + 10)
+#define MSM8625_INT_UART3 (GIC_SPI_START + 11)
+#define MSM8625_INT_UART1_RX (GIC_SPI_START + 12)
+#define MSM8625_INT_UART2_RX (GIC_SPI_START + 13)
+#define MSM8625_INT_UART3_RX (GIC_SPI_START + 14)
+#define MSM8625_INT_USB_OTG (GIC_SPI_START + 15)
+#define MSM8625_INT_DSI_IRQ (GIC_SPI_START + 16)
+#define MSM8625_INT_CSI_IRQ_1 (GIC_SPI_START + 17)
+#define MSM8625_INT_CSI_IRQ_0 (GIC_SPI_START + 18)
+#define MSM8625_INT_MDP (GIC_SPI_START + 19)
+#define MSM8625_INT_GRAPHICS (GIC_SPI_START + 20)
+#define MSM8625_INT_ADM_AARM (GIC_SPI_START + 21)
+#define MSM8625_INT_ADSP_A11 (GIC_SPI_START + 22)
+#define MSM8625_INT_ADSP_A9_A11 (GIC_SPI_START + 23)
+#define MSM8625_INT_SDC1_0 (GIC_SPI_START + 24)
+#define MSM8625_INT_SDC1_1 (GIC_SPI_START + 25)
+#define MSM8625_INT_SDC2_0 (GIC_SPI_START + 26)
+#define MSM8625_INT_SDC2_1 (GIC_SPI_START + 27)
+#define MSM8625_INT_KEYSENSE (GIC_SPI_START + 28)
+#define MSM8625_INT_TCHSCRN_SSBI (GIC_SPI_START + 29)
+#define MSM8625_INT_TCHSCRN1 (GIC_SPI_START + 30)
+#define MSM8625_INT_TCHSCRN2 (GIC_SPI_START + 31)
+
+#define MSM8625_INT_GPIO_GROUP1 (GIC_SPI_START + 32 + 0)
+#define MSM8625_INT_GPIO_GROUP2 (GIC_SPI_START + 32 + 1)
+#define MSM8625_INT_PWB_I2C (GIC_SPI_START + 32 + 2)
+#define MSM8625_INT_SOFTRESET (GIC_SPI_START + 32 + 3)
+#define MSM8625_INT_NAND_WR_ER_DONE (GIC_SPI_START + 32 + 4)
+#define MSM8625_INT_NAND_OP_DONE (GIC_SPI_START + 32 + 5)
+#define MSM8625_INT_PBUS_ARM11 (GIC_SPI_START + 32 + 6)
+#define MSM8625_INT_AXI_MPU_SMI (GIC_SPI_START + 32 + 7)
+#define MSM8625_INT_AXI_MPU_EBI1 (GIC_SPI_START + 32 + 8)
+#define MSM8625_INT_AD_HSSD (GIC_SPI_START + 32 + 9)
+#define MSM8625_INT_NOTUSED (GIC_SPI_START + 32 + 10)
+#define MSM8625_INT_ARM11_DMA (GIC_SPI_START + 32 + 11)
+#define MSM8625_INT_TSIF_IRQ (GIC_SPI_START + 32 + 12)
+#define MSM8625_INT_UART1DM_IRQ (GIC_SPI_START + 32 + 13)
+#define MSM8625_INT_UART1DM_RX (GIC_SPI_START + 32 + 14)
+#define MSM8625_INT_USB_HS (GIC_SPI_START + 32 + 15)
+#define MSM8625_INT_SDC3_0 (GIC_SPI_START + 32 + 16)
+#define MSM8625_INT_SDC3_1 (GIC_SPI_START + 32 + 17)
+#define MSM8625_INT_SDC4_0 (GIC_SPI_START + 32 + 18)
+#define MSM8625_INT_SDC4_1 (GIC_SPI_START + 32 + 19)
+#define MSM8625_INT_UART2DM_IRQ (GIC_SPI_START + 32 + 20)
+#define MSM8625_INT_UART2DM_RX (GIC_SPI_START + 32 + 21)
+#define MSM8625_INT_L2CC_EM (GIC_SPI_START + 32 + 22)
+#define MSM8625_INT_L2CC_INTR (GIC_SPI_START + 32 + 23)
+#define MSM8625_INT_CE_IRQ (GIC_SPI_START + 32 + 24)
+
+#define MSM8625_INT_ADSP_A11_SMSM MSM8625_INT_ADSP_A11
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8c1e4ff..954b673 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -19,6 +19,8 @@
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
+#include "irqs-8625.h"
+
#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064) || \
defined(CONFIG_ARCH_MSM8930)
@@ -63,6 +65,11 @@
#elif defined(CONFIG_ARCH_MSM7X01A) || defined(CONFIG_ARCH_MSM7X25) \
|| defined(CONFIG_ARCH_MSM7X27)
#include "irqs-7xxx.h"
+
+#define NR_GPIO_IRQS 133
+#define NR_MSM_IRQS 256
+#define NR_BOARD_IRQS 256
+#define NR_MSM_GPIOS NR_GPIO_IRQS
#elif defined(CONFIG_ARCH_FSM9XXX)
#include "irqs-fsm9xxx.h"
#include "sirc.h"
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
index d545a5f..ba50a30 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7xxx.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -49,8 +49,6 @@
#define MSM_TMR0_BASE MSM_TMR_BASE
-#define MSM_QGIC_DIST_BASE MSM_VIC_BASE
-
#define MSM_GPIO1_BASE IOMEM(0xFA003000)
#define MSM_GPIO1_PHYS 0xA9200000
#define MSM_GPIO1_SIZE SZ_4K
@@ -67,6 +65,30 @@
#define MSM_L2CC_PHYS 0xC0400000
#define MSM_L2CC_SIZE SZ_4K
+#define MSM_QGIC_DIST_BASE IOMEM(0xFA000000)
+#define MSM_QGIC_DIST_PHYS 0xC0000000
+#define MSM_QGIC_DIST_SIZE SZ_4K
+
+#define MSM_QGIC_CPU_BASE IOMEM(0xFA007000)
+#define MSM_QGIC_CPU_PHYS 0xC0002000
+#define MSM_QGIC_CPU_SIZE SZ_256
+
+#define MSM_SCU_BASE IOMEM(0xFA008000)
+#define MSM_SCU_PHYS 0xC0600000
+#define MSM_SCU_SIZE SZ_256
+
+#define MSM_SPM0_BASE IOMEM(0xFA009000)
+#define MSM_SPM0_PHYS 0xC0200000
+#define MSM_SPM0_SIZE SZ_4K
+
+#define MSM_SPM1_BASE IOMEM(0xFA00A000)
+#define MSM_SPM1_PHYS 0xC0700000
+#define MSM_SPM1_SIZE SZ_4K
+
+#define MSM_CFG_CTL_BASE IOMEM(0xFA00B000)
+#define MSM_CFG_CTL_PHYS 0xA9800000
+#define MSM_CFG_CTL_SIZE SZ_4K
+
#define MSM_SHARED_RAM_BASE IOMEM(0xFA100000)
#define MSM_SHARED_RAM_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator-8930.h b/arch/arm/mach-msm/include/mach/rpm-regulator-8930.h
new file mode 100644
index 0000000..9e654ed
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator-8930.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8930_H
+#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8930_H
+
+/* Pin control input signals. */
+#define RPM_VREG_PIN_CTRL_PM8038_D1 0x01
+#define RPM_VREG_PIN_CTRL_PM8038_A0 0x02
+#define RPM_VREG_PIN_CTRL_PM8038_A1 0x04
+#define RPM_VREG_PIN_CTRL_PM8038_A2 0x08
+
+/**
+ * enum rpm_vreg_pin_fn_8930 - RPM regulator pin function choices
+ * %RPM_VREG_PIN_FN_8930_DONT_CARE: do not care about pin control state of
+ * the regulator; allow another master
+ * processor to specify pin control
+ * %RPM_VREG_PIN_FN_8930_ENABLE: pin control switches between disable and
+ * enable
+ * %RPM_VREG_PIN_FN_8930_MODE: pin control switches between LPM and HPM
+ * %RPM_VREG_PIN_FN_8930_SLEEP_B: regulator is forced into LPM when
+ * sleep_b signal is asserted
+ * %RPM_VREG_PIN_FN_8930_NONE: do not use pin control for the regulator
+ * and do not allow another master to
+ * request pin control
+ *
+ * The pin function specified in platform data corresponds to the active state
+ * pin function value. Pin function will be NONE until a consumer requests
+ * pin control to be enabled.
+ */
+enum rpm_vreg_pin_fn_8930 {
+ RPM_VREG_PIN_FN_8930_DONT_CARE,
+ RPM_VREG_PIN_FN_8930_ENABLE,
+ RPM_VREG_PIN_FN_8930_MODE,
+ RPM_VREG_PIN_FN_8930_SLEEP_B,
+ RPM_VREG_PIN_FN_8930_NONE,
+};
+
+/**
+ * enum rpm_vreg_force_mode_8930 - RPM regulator force mode choices
+ * %RPM_VREG_FORCE_MODE_8930_PIN_CTRL: allow pin control usage
+ * %RPM_VREG_FORCE_MODE_8930_NONE: do not force any mode
+ * %RPM_VREG_FORCE_MODE_8930_LPM: force into low power mode
+ * %RPM_VREG_FORCE_MODE_8930_AUTO: allow regulator to automatically select
+ * its own mode based on realtime current
+ * draw (only available for SMPS
+ * regulators)
+ * %RPM_VREG_FORCE_MODE_8930_HPM: force into high power mode
+ * %RPM_VREG_FORCE_MODE_8930_BYPASS: set regulator to use bypass mode, i.e.
+ * to act as a switch and not regulate
+ * (only available for LDO regulators)
+ *
+ * Force mode is used to override aggregation with other masters and to set
+ * special operating modes.
+ */
+enum rpm_vreg_force_mode_8930 {
+ RPM_VREG_FORCE_MODE_8930_PIN_CTRL = 0,
+ RPM_VREG_FORCE_MODE_8930_NONE = 0,
+ RPM_VREG_FORCE_MODE_8930_LPM,
+ RPM_VREG_FORCE_MODE_8930_AUTO, /* SMPS only */
+ RPM_VREG_FORCE_MODE_8930_HPM,
+ RPM_VREG_FORCE_MODE_8930_BYPASS, /* LDO only */
+};
+
+/**
+ * enum rpm_vreg_power_mode_8930 - power mode for SMPS regulators
+ * %RPM_VREG_POWER_MODE_8930_HYSTERETIC: Use hysteretic mode for HPM and when
+ * usage goes high in AUTO
+ * %RPM_VREG_POWER_MODE_8930_PWM: Use PWM mode for HPM and when usage
+ * goes high in AUTO
+ */
+enum rpm_vreg_power_mode_8930 {
+ RPM_VREG_POWER_MODE_8930_HYSTERETIC,
+ RPM_VREG_POWER_MODE_8930_PWM,
+};
+
+/**
+ * enum rpm_vreg_id - RPM regulator ID numbers (both real and pin control)
+ */
+enum rpm_vreg_id_8930 {
+ RPM_VREG_ID_PM8038_L1,
+ RPM_VREG_ID_PM8038_L2,
+ RPM_VREG_ID_PM8038_L3,
+ RPM_VREG_ID_PM8038_L4,
+ RPM_VREG_ID_PM8038_L5,
+ RPM_VREG_ID_PM8038_L6,
+ RPM_VREG_ID_PM8038_L7,
+ RPM_VREG_ID_PM8038_L8,
+ RPM_VREG_ID_PM8038_L9,
+ RPM_VREG_ID_PM8038_L10,
+ RPM_VREG_ID_PM8038_L11,
+ RPM_VREG_ID_PM8038_L12,
+ RPM_VREG_ID_PM8038_L14,
+ RPM_VREG_ID_PM8038_L15,
+ RPM_VREG_ID_PM8038_L16,
+ RPM_VREG_ID_PM8038_L17,
+ RPM_VREG_ID_PM8038_L18,
+ RPM_VREG_ID_PM8038_L19,
+ RPM_VREG_ID_PM8038_L20,
+ RPM_VREG_ID_PM8038_L21,
+ RPM_VREG_ID_PM8038_L22,
+ RPM_VREG_ID_PM8038_L23,
+ RPM_VREG_ID_PM8038_L24,
+ RPM_VREG_ID_PM8038_L26,
+ RPM_VREG_ID_PM8038_L27,
+ RPM_VREG_ID_PM8038_S1,
+ RPM_VREG_ID_PM8038_S2,
+ RPM_VREG_ID_PM8038_S3,
+ RPM_VREG_ID_PM8038_S4,
+ RPM_VREG_ID_PM8038_S5,
+ RPM_VREG_ID_PM8038_S6,
+ RPM_VREG_ID_PM8038_LVS1,
+ RPM_VREG_ID_PM8038_LVS2,
+ RPM_VREG_ID_PM8038_MAX_REAL = RPM_VREG_ID_PM8038_LVS2,
+
+ /* The following are IDs for regulator devices to enable pin control. */
+ RPM_VREG_ID_PM8038_L2_PC,
+ RPM_VREG_ID_PM8038_L3_PC,
+ RPM_VREG_ID_PM8038_L4_PC,
+ RPM_VREG_ID_PM8038_L5_PC,
+ RPM_VREG_ID_PM8038_L6_PC,
+ RPM_VREG_ID_PM8038_L7_PC,
+ RPM_VREG_ID_PM8038_L8_PC,
+ RPM_VREG_ID_PM8038_L9_PC,
+ RPM_VREG_ID_PM8038_L10_PC,
+ RPM_VREG_ID_PM8038_L11_PC,
+ RPM_VREG_ID_PM8038_L12_PC,
+ RPM_VREG_ID_PM8038_L14_PC,
+ RPM_VREG_ID_PM8038_L15_PC,
+ RPM_VREG_ID_PM8038_L17_PC,
+ RPM_VREG_ID_PM8038_L18_PC,
+ RPM_VREG_ID_PM8038_L21_PC,
+ RPM_VREG_ID_PM8038_L22_PC,
+ RPM_VREG_ID_PM8038_L23_PC,
+ RPM_VREG_ID_PM8038_L26_PC,
+ RPM_VREG_ID_PM8038_S1_PC,
+ RPM_VREG_ID_PM8038_S2_PC,
+ RPM_VREG_ID_PM8038_S3_PC,
+ RPM_VREG_ID_PM8038_S4_PC,
+ RPM_VREG_ID_PM8038_LVS1_PC,
+ RPM_VREG_ID_PM8038_LVS2_PC,
+ RPM_VREG_ID_PM8038_MAX = RPM_VREG_ID_PM8038_LVS2_PC,
+};
+
+/* Minimum high power mode loads in uA. */
+#define RPM_VREG_8930_LDO_50_HPM_MIN_LOAD 5000
+#define RPM_VREG_8930_LDO_150_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_LDO_300_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_LDO_600_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_LDO_1200_HPM_MIN_LOAD 10000
+#define RPM_VREG_8930_SMPS_1500_HPM_MIN_LOAD 100000
+#define RPM_VREG_8930_SMPS_2000_HPM_MIN_LOAD 100000
+
+#endif
diff --git a/arch/arm/mach-msm/include/mach/rpm-regulator.h b/arch/arm/mach-msm/include/mach/rpm-regulator.h
index 1095078..0d113ac 100644
--- a/arch/arm/mach-msm/include/mach/rpm-regulator.h
+++ b/arch/arm/mach-msm/include/mach/rpm-regulator.h
@@ -21,6 +21,7 @@
#include <mach/rpm-regulator-8960.h>
#include <mach/rpm-regulator-9615.h>
#include <mach/rpm-regulator-copper.h>
+#include <mach/rpm-regulator-8930.h>
/**
* enum rpm_vreg_version - supported RPM regulator versions
@@ -29,7 +30,8 @@
RPM_VREG_VERSION_8660,
RPM_VREG_VERSION_8960,
RPM_VREG_VERSION_9615,
- RPM_VREG_VERSION_MAX = RPM_VREG_VERSION_9615,
+ RPM_VREG_VERSION_8930,
+ RPM_VREG_VERSION_MAX = RPM_VREG_VERSION_8930,
};
#define RPM_VREG_PIN_CTRL_NONE 0x00
diff --git a/arch/arm/mach-msm/include/mach/socinfo.h b/arch/arm/mach-msm/include/mach/socinfo.h
index a06b9ae..e1d4459 100644
--- a/arch/arm/mach-msm/include/mach/socinfo.h
+++ b/arch/arm/mach-msm/include/mach/socinfo.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -62,6 +62,7 @@
MSM_CPU_9615,
MSM_CPU_COPPER,
MSM_CPU_8627,
+ MSM_CPU_8625,
};
enum msm_cpu socinfo_get_msm_cpu(void);
@@ -266,4 +267,17 @@
return 0;
#endif
}
+
+static inline int cpu_is_msm8625(void)
+{
+#ifdef CONFIG_ARCH_MSM8625
+ enum msm_cpu cpu = socinfo_get_msm_cpu();
+
+ BUG_ON(cpu == MSM_CPU_UNKNOWN);
+ return cpu == MSM_CPU_8625;
+#else
+ return 0;
+#endif
+}
+
#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 0f9d707..79c9aed 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -3,7 +3,7 @@
* MSM7K, QSD io support
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2012, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@@ -397,6 +397,47 @@
}
#endif /* CONFIG_ARCH_MSM9615 */
+#ifdef CONFIG_ARCH_MSM8625
+static struct map_desc msm8625_io_desc[] __initdata = {
+ MSM_DEVICE(QGIC_DIST),
+ MSM_DEVICE(QGIC_CPU),
+ MSM_DEVICE(TMR),
+ MSM_DEVICE(TMR0),
+ MSM_DEVICE(CSR),
+ MSM_DEVICE(SCU),
+ MSM_DEVICE(CFG_CTL),
+ MSM_DEVICE(GPIO1),
+ MSM_DEVICE(GPIO2),
+ MSM_DEVICE(CLK_CTL),
+ MSM_DEVICE(SPM0),
+ MSM_DEVICE(SPM1),
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+ defined(CONFIG_DEBUG_MSM_UART3)
+ MSM_DEVICE(DEBUG_UART),
+#endif
+#ifdef CONFIG_CACHE_L2X0
+ {
+ .virtual = (unsigned long) MSM_L2CC_BASE,
+ .pfn = __phys_to_pfn(MSM_L2CC_PHYS),
+ .length = MSM_L2CC_SIZE,
+ .type = MT_DEVICE,
+ },
+#endif
+ {
+ .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
+ .length = MSM_SHARED_RAM_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init msm_map_msm8625_io(void)
+{
+ msm_map_io(msm8625_io_desc, ARRAY_SIZE(msm8625_io_desc));
+}
+#else
+void __init msm_map_msm8625_io(void) { return; }
+#endif /* CONFIG_ARCH_MSM8625 */
+
void __iomem *
__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{
diff --git a/arch/arm/mach-msm/rpm-regulator-8930.c b/arch/arm/mach-msm/rpm-regulator-8930.c
new file mode 100644
index 0000000..22595ec
--- /dev/null
+++ b/arch/arm/mach-msm/rpm-regulator-8930.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include "rpm-regulator-private.h"
+
+/* RPM regulator request formats */
+static struct rpm_vreg_parts ldo_parts = {
+ .request_len = 2,
+ .uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
+ .pd = REQUEST_MEMBER(0, 0x00800000, 23),
+ .pc = REQUEST_MEMBER(0, 0x0F000000, 24),
+ .pf = REQUEST_MEMBER(0, 0xF0000000, 28),
+ .ip = REQUEST_MEMBER(1, 0x000003FF, 0),
+ .ia = REQUEST_MEMBER(1, 0x000FFC00, 10),
+ .fm = REQUEST_MEMBER(1, 0x00700000, 20),
+};
+
+static struct rpm_vreg_parts smps_parts = {
+ .request_len = 2,
+ .uV = REQUEST_MEMBER(0, 0x007FFFFF, 0),
+ .pd = REQUEST_MEMBER(0, 0x00800000, 23),
+ .pc = REQUEST_MEMBER(0, 0x0F000000, 24),
+ .pf = REQUEST_MEMBER(0, 0xF0000000, 28),
+ .ip = REQUEST_MEMBER(1, 0x000003FF, 0),
+ .ia = REQUEST_MEMBER(1, 0x000FFC00, 10),
+ .fm = REQUEST_MEMBER(1, 0x00700000, 20),
+ .pm = REQUEST_MEMBER(1, 0x00800000, 23),
+ .freq = REQUEST_MEMBER(1, 0x1F000000, 24),
+ .freq_clk_src = REQUEST_MEMBER(1, 0x60000000, 29),
+};
+
+static struct rpm_vreg_parts switch_parts = {
+ .request_len = 1,
+ .enable_state = REQUEST_MEMBER(0, 0x00000001, 0),
+ .pd = REQUEST_MEMBER(0, 0x00000002, 1),
+ .pc = REQUEST_MEMBER(0, 0x0000003C, 2),
+ .pf = REQUEST_MEMBER(0, 0x000003C0, 6),
+ .hpm = REQUEST_MEMBER(0, 0x00000C00, 10),
+};
+
+/* Physically available PMIC regulator voltage setpoint ranges */
+static struct vreg_range pldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+ VOLTAGE_RANGE(3100000, 4900000, 50000),
+};
+
+static struct vreg_range nldo_ranges[] = {
+ VOLTAGE_RANGE( 750000, 1537500, 12500),
+};
+
+static struct vreg_range nldo1200_ranges[] = {
+ VOLTAGE_RANGE( 375000, 743750, 6250),
+ VOLTAGE_RANGE( 750000, 1537500, 12500),
+};
+
+static struct vreg_range smps_ranges[] = {
+ VOLTAGE_RANGE( 375000, 737500, 12500),
+ VOLTAGE_RANGE( 750000, 1487500, 12500),
+ VOLTAGE_RANGE(1500000, 3075000, 25000),
+};
+
+static struct vreg_range ftsmps_ranges[] = {
+ VOLTAGE_RANGE( 350000, 650000, 50000),
+ VOLTAGE_RANGE( 700000, 1400000, 12500),
+ VOLTAGE_RANGE(1500000, 3300000, 50000),
+};
+
+static struct vreg_set_points pldo_set_points = SET_POINTS(pldo_ranges);
+static struct vreg_set_points nldo_set_points = SET_POINTS(nldo_ranges);
+static struct vreg_set_points nldo1200_set_points = SET_POINTS(nldo1200_ranges);
+static struct vreg_set_points smps_set_points = SET_POINTS(smps_ranges);
+static struct vreg_set_points ftsmps_set_points = SET_POINTS(ftsmps_ranges);
+
+static struct vreg_set_points *all_set_points[] = {
+ &pldo_set_points,
+ &nldo_set_points,
+ &nldo1200_set_points,
+ &smps_set_points,
+ &ftsmps_set_points,
+};
+
+#define LDO(_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_PM8038_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8038_##_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_PM8038_##_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_8930_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_LDO, \
+ .set_points = &_ranges##_set_points, \
+ .part = &ldo_parts, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define SMPS(_id, _name, _name_pc, _ranges, _hpm_min_load) \
+ [RPM_VREG_ID_PM8038_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8038_##_id##_0, }, \
+ [1] = { .id = MSM_RPM_ID_PM8038_##_id##_1, }, \
+ }, \
+ .hpm_min_load = RPM_VREG_8930_##_hpm_min_load##_HPM_MIN_LOAD, \
+ .type = RPM_REGULATOR_TYPE_SMPS, \
+ .set_points = &_ranges##_set_points, \
+ .part = &smps_parts, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+#define LVS(_id, _name, _name_pc) \
+ [RPM_VREG_ID_PM8038_##_id] = { \
+ .req = { \
+ [0] = { .id = MSM_RPM_ID_PM8038_##_id, }, \
+ [1] = { .id = -1, }, \
+ }, \
+ .type = RPM_REGULATOR_TYPE_VS, \
+ .part = &switch_parts, \
+ .id = RPM_VREG_ID_PM8038_##_id, \
+ .rdesc.name = _name, \
+ .rdesc_pc.name = _name_pc, \
+ }
+
+static struct vreg vregs[] = {
+ LDO(L1, "8038_l1", NULL, nldo1200, LDO_1200),
+ LDO(L2, "8038_l2", "8038_l2_pc", nldo, LDO_150),
+ LDO(L3, "8038_l3", "8038_l3_pc", pldo, LDO_50),
+ LDO(L4, "8038_l4", "8038_l4_pc", pldo, LDO_50),
+ LDO(L5, "8038_l5", "8038_l5_pc", pldo, LDO_600),
+ LDO(L6, "8038_l6", "8038_l6_pc", pldo, LDO_600),
+ LDO(L7, "8038_l7", "8038_l7_pc", pldo, LDO_600),
+ LDO(L8, "8038_l8", "8038_l8_pc", pldo, LDO_300),
+ LDO(L9, "8038_l9", "8038_l9_pc", pldo, LDO_300),
+ LDO(L10, "8038_l10", "8038_l10_pc", pldo, LDO_600),
+ LDO(L11, "8038_l11", "8038_l11_pc", pldo, LDO_600),
+ LDO(L12, "8038_l12", "8038_l12_pc", nldo, LDO_300),
+ LDO(L14, "8038_l14", "8038_l14_pc", pldo, LDO_50),
+ LDO(L15, "8038_l15", "8038_l15_pc", pldo, LDO_150),
+ LDO(L16, "8038_l16", NULL, nldo1200, LDO_1200),
+ LDO(L17, "8038_l17", "8038_l17_pc", pldo, LDO_150),
+ LDO(L18, "8038_l18", "8038_l18_pc", pldo, LDO_50),
+ LDO(L19, "8038_l19", NULL, nldo1200, LDO_1200),
+ LDO(L20, "8038_l20", NULL, nldo1200, LDO_1200),
+ LDO(L21, "8038_l21", "8038_l21_pc", pldo, LDO_150),
+ LDO(L22, "8038_l22", "8038_l22_pc", pldo, LDO_50),
+ LDO(L23, "8038_l23", "8038_l23_pc", pldo, LDO_50),
+ LDO(L24, "8038_l24", NULL, nldo1200, LDO_1200),
+ LDO(L26, "8038_l26", "8038_l26_pc", nldo, LDO_150),
+ LDO(L27, "8038_l27", NULL, nldo1200, LDO_1200),
+
+ SMPS(S1, "8038_s1", "8038_s1_pc", smps, SMPS_1500),
+ SMPS(S2, "8038_s2", "8038_s2_pc", smps, SMPS_1500),
+ SMPS(S3, "8038_s3", "8038_s3_pc", smps, SMPS_1500),
+ SMPS(S4, "8038_s4", "8038_s4_pc", smps, SMPS_1500),
+ SMPS(S5, "8038_s5", NULL, ftsmps, SMPS_2000),
+ SMPS(S6, "8038_s6", NULL, ftsmps, SMPS_2000),
+
+ LVS(LVS1, "8038_lvs1", "8038_lvs1_pc"),
+ LVS(LVS2, "8038_lvs2", "8038_lvs2_pc"),
+};
+
+static const char *pin_func_label[] = {
+ [RPM_VREG_PIN_FN_8930_DONT_CARE] = "don't care",
+ [RPM_VREG_PIN_FN_8930_ENABLE] = "on/off",
+ [RPM_VREG_PIN_FN_8930_MODE] = "HPM/LPM",
+ [RPM_VREG_PIN_FN_8930_SLEEP_B] = "sleep_b",
+ [RPM_VREG_PIN_FN_8930_NONE] = "none",
+};
+
+static const char *force_mode_label[] = {
+ [RPM_VREG_FORCE_MODE_8930_NONE] = "none",
+ [RPM_VREG_FORCE_MODE_8930_LPM] = "LPM",
+ [RPM_VREG_FORCE_MODE_8930_AUTO] = "auto",
+ [RPM_VREG_FORCE_MODE_8930_HPM] = "HPM",
+ [RPM_VREG_FORCE_MODE_8930_BYPASS] = "BYP",
+};
+
+static const char *power_mode_label[] = {
+ [RPM_VREG_POWER_MODE_8930_HYSTERETIC] = "HYS",
+ [RPM_VREG_POWER_MODE_8930_PWM] = "PWM",
+};
+
+static const char *pin_control_label[] = {
+ " D1",
+ " A0",
+ " A1",
+ " A2",
+};
+
+static int is_real_id(int id)
+{
+ return (id >= 0) && (id <= RPM_VREG_ID_PM8038_MAX_REAL);
+}
+
+static int pc_id_to_real_id(int id)
+{
+ int real_id = 0;
+
+ if (id >= RPM_VREG_ID_PM8038_L2_PC && id <= RPM_VREG_ID_PM8038_L15_PC)
+ real_id = id - RPM_VREG_ID_PM8038_L2_PC;
+ else if (id >= RPM_VREG_ID_PM8038_L17_PC
+ && id <= RPM_VREG_ID_PM8038_L18_PC)
+ real_id = id - RPM_VREG_ID_PM8038_L17_PC
+ + RPM_VREG_ID_PM8038_L17;
+ else if (id >= RPM_VREG_ID_PM8038_L21_PC
+ && id <= RPM_VREG_ID_PM8038_L23_PC)
+ real_id = id - RPM_VREG_ID_PM8038_L21_PC
+ + RPM_VREG_ID_PM8038_L21;
+ else if (id == RPM_VREG_ID_PM8038_L26_PC)
+ real_id = RPM_VREG_ID_PM8038_L26;
+ else if (id >= RPM_VREG_ID_PM8038_S1_PC
+ && id <= RPM_VREG_ID_PM8038_S4_PC)
+ real_id = id - RPM_VREG_ID_PM8038_S1_PC
+ + RPM_VREG_ID_PM8038_S1;
+ else if (id >= RPM_VREG_ID_PM8038_LVS1_PC
+ && id <= RPM_VREG_ID_PM8038_LVS2_PC)
+ real_id = id - RPM_VREG_ID_PM8038_LVS1_PC
+ + RPM_VREG_ID_PM8038_LVS1;
+
+ return real_id;
+}
+
+static struct vreg_config config = {
+ .vregs = vregs,
+ .vregs_len = ARRAY_SIZE(vregs),
+
+ .vreg_id_min = RPM_VREG_ID_PM8038_L1,
+ .vreg_id_max = RPM_VREG_ID_PM8038_MAX,
+
+ .pin_func_none = RPM_VREG_PIN_FN_8930_NONE,
+ .pin_func_sleep_b = RPM_VREG_PIN_FN_8930_SLEEP_B,
+
+ .mode_lpm = REGULATOR_MODE_IDLE,
+ .mode_hpm = REGULATOR_MODE_NORMAL,
+
+ .set_points = all_set_points,
+ .set_points_len = ARRAY_SIZE(all_set_points),
+
+ .label_pin_ctrl = pin_control_label,
+ .label_pin_ctrl_len = ARRAY_SIZE(pin_control_label),
+ .label_pin_func = pin_func_label,
+ .label_pin_func_len = ARRAY_SIZE(pin_func_label),
+ .label_force_mode = force_mode_label,
+ .label_force_mode_len = ARRAY_SIZE(force_mode_label),
+ .label_power_mode = power_mode_label,
+ .label_power_mode_len = ARRAY_SIZE(power_mode_label),
+
+ .is_real_id = is_real_id,
+ .pc_id_to_real_id = pc_id_to_real_id,
+};
+
+struct vreg_config *get_config_8930(void)
+{
+ return &config;
+}
diff --git a/arch/arm/mach-msm/rpm-regulator-private.h b/arch/arm/mach-msm/rpm-regulator-private.h
index ff127d9..88b52ea 100644
--- a/arch/arm/mach-msm/rpm-regulator-private.h
+++ b/arch/arm/mach-msm/rpm-regulator-private.h
@@ -144,7 +144,7 @@
#define MICRO_TO_MILLI(uV) ((uV) / 1000)
#define MILLI_TO_MICRO(mV) ((mV) * 1000)
-#if defined(CONFIG_ARCH_MSM8X60)
+#if defined(CONFIG_MSM_RPM_REGULATOR) && defined(CONFIG_ARCH_MSM8X60)
struct vreg_config *get_config_8660(void);
#else
static inline struct vreg_config *get_config_8660(void)
@@ -153,7 +153,8 @@
}
#endif
-#if defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064)
+#if defined(CONFIG_MSM_RPM_REGULATOR) && \
+ (defined(CONFIG_ARCH_MSM8960) || defined(CONFIG_ARCH_APQ8064))
struct vreg_config *get_config_8960(void);
#else
static inline struct vreg_config *get_config_8960(void)
@@ -162,7 +163,7 @@
}
#endif
-#if defined(CONFIG_ARCH_MSM9615)
+#if defined(CONFIG_MSM_RPM_REGULATOR) && defined(CONFIG_ARCH_MSM9615)
struct vreg_config *get_config_9615(void);
#else
static inline struct vreg_config *get_config_9615(void)
@@ -171,4 +172,13 @@
}
#endif
+#if defined(CONFIG_MSM_RPM_REGULATOR) && defined(CONFIG_ARCH_MSM8930)
+struct vreg_config *get_config_8930(void);
+#else
+static inline struct vreg_config *get_config_8930(void)
+{
+ return NULL;
+}
+#endif
+
#endif
diff --git a/arch/arm/mach-msm/rpm-regulator.c b/arch/arm/mach-msm/rpm-regulator.c
index e2ebbd4..946d31b 100644
--- a/arch/arm/mach-msm/rpm-regulator.c
+++ b/arch/arm/mach-msm/rpm-regulator.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -46,6 +46,7 @@
[RPM_VREG_VERSION_8660] = get_config_8660,
[RPM_VREG_VERSION_8960] = get_config_8960,
[RPM_VREG_VERSION_9615] = get_config_9615,
+ [RPM_VREG_VERSION_8930] = get_config_8930,
};
#define SET_PART(_vreg, _part, _val) \
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 514f817..0bc3b0e 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -1459,18 +1459,16 @@
struct smd_channel *ch;
struct smd_channel *index;
+ mutex_lock(&smd_creation_mutex);
spin_lock_irqsave(&smd_lock, flags);
list_for_each_entry_safe(ch, index, &smd_ch_to_close_list, ch_list) {
list_del(&ch->ch_list);
- spin_unlock_irqrestore(&smd_lock, flags);
- mutex_lock(&smd_creation_mutex);
list_add(&ch->ch_list, &smd_ch_closed_list);
- mutex_unlock(&smd_creation_mutex);
ch->notify(ch->priv, SMD_EVENT_REOPEN_READY);
ch->notify = do_nothing_notify;
- spin_lock_irqsave(&smd_lock, flags);
}
spin_unlock_irqrestore(&smd_lock, flags);
+ mutex_unlock(&smd_creation_mutex);
}
struct smd_channel *smd_get_channel(const char *name, uint32_t type)
@@ -1506,8 +1504,37 @@
SMD_DBG("smd_open('%s', %p, %p)\n", name, priv, notify);
ch = smd_get_channel(name, edge);
- if (!ch)
- return -ENODEV;
+ if (!ch) {
+ unsigned long flags;
+ struct smd_channel *ch;
+
+ /* check closing list for port */
+ spin_lock_irqsave(&smd_lock, flags);
+ list_for_each_entry(ch, &smd_ch_closing_list, ch_list) {
+ if (!strncmp(name, ch->name, 20) &&
+ (edge == ch->type)) {
+ /* channel exists, but is being closed */
+ spin_unlock_irqrestore(&smd_lock, flags);
+ return -EAGAIN;
+ }
+ }
+
+ /* check closing workqueue list for port */
+ list_for_each_entry(ch, &smd_ch_to_close_list, ch_list) {
+ if (!strncmp(name, ch->name, 20) &&
+ (edge == ch->type)) {
+ /* channel exists, but is being closed */
+ spin_unlock_irqrestore(&smd_lock, flags);
+ return -EAGAIN;
+ }
+ }
+ spin_unlock_irqrestore(&smd_lock, flags);
+
+ /* one final check to handle closing->closed race condition */
+ ch = smd_get_channel(name, edge);
+ if (!ch)
+ return -ENODEV;
+ }
if (notify == 0)
notify = do_nothing_notify;
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index 9a8ab43..0ec88d5 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -241,6 +241,11 @@
/* Copper IDs */
[126] = MSM_CPU_COPPER,
+ /* 8625 IDs */
+ [127] = MSM_CPU_8625,
+ [128] = MSM_CPU_8625,
+ [129] = MSM_CPU_8625,
+
/* Uninitialized IDs are not known to run Linux.
MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are
considered as unknown CPU. */
@@ -609,6 +614,8 @@
dummy_socinfo.id = 104;
else if (early_machine_is_copper())
dummy_socinfo.id = 126;
+ else if (machine_is_msm8625_rumi3())
+ dummy_socinfo.id = 127;
return (void *) &dummy_socinfo;
}
diff --git a/arch/arm/mach-msm/tz_log.c b/arch/arm/mach-msm/tz_log.c
index 8d7196b..7426bb2 100644
--- a/arch/arm/mach-msm/tz_log.c
+++ b/arch/arm/mach-msm/tz_log.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -53,8 +53,10 @@
* Boot Info Table
*/
struct tzdbg_boot_info_t {
- uint32_t entry_cnt; /* Warmboot entry CPU Counter */
- uint32_t exit_cnt; /* Warmboot exit CPU Counter */
+ uint32_t wb_entry_cnt; /* Warmboot entry CPU Counter */
+ uint32_t wb_exit_cnt; /* Warmboot exit CPU Counter */
+ uint32_t pc_entry_cnt; /* Power Collapse entry CPU Counter */
+ uint32_t pc_exit_cnt; /* Power Collapse exit CPU counter */
uint32_t warm_jmp_addr; /* Last Warmboot Jump Address */
uint32_t spare; /* Reserved for future use. */
};
@@ -250,9 +252,12 @@
" CPU #: %d\n"
" Warmboot jump address : 0x%x\n"
" Warmboot entry CPU counter: 0x%x\n"
- " Warmboot exit CPU counter : 0x%x\n",
- i, ptr->warm_jmp_addr, ptr->entry_cnt,
- ptr->exit_cnt);
+ " Warmboot exit CPU counter : 0x%x\n"
+ " Power Collapse entry CPU counter: 0x%x\n"
+ " Power Collapse exit CPU counter : 0x%x\n",
+ i, ptr->warm_jmp_addr, ptr->wb_entry_cnt,
+ ptr->wb_exit_cnt, ptr->pc_entry_cnt,
+ ptr->pc_exit_cnt);
if (len > (DEBUG_MAX_RW_BUF - 1)) {
pr_warn("%s: Cannot fit all info into the buffer\n",
@@ -555,5 +560,5 @@
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TZ Log driver");
-MODULE_VERSION("1.0");
+MODULE_VERSION("1.1");
MODULE_ALIAS("platform:tz_log");
diff --git a/drivers/gpu/ion/ion.c b/drivers/gpu/ion/ion.c
index 386593f5..5e325e9 100644
--- a/drivers/gpu/ion/ion.c
+++ b/drivers/gpu/ion/ion.c
@@ -1044,14 +1044,13 @@
client->handles = RB_ROOT;
mutex_init(&client->lock);
- client->name = kzalloc(sizeof(name_len+1), GFP_KERNEL);
+ client->name = kzalloc(name_len+1, GFP_KERNEL);
if (!client->name) {
put_task_struct(current->group_leader);
kfree(client);
return ERR_PTR(-ENOMEM);
} else {
- strncpy(client->name, name, name_len);
- client->name[name_len] = '\0';
+ strlcpy(client->name, name, name_len+1);
}
client->heap_mask = heap_mask;
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 60bd232..1ef71a4 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -621,7 +621,7 @@
struct kgsl_device *device = (struct kgsl_device *) data;
KGSL_PWR_INFO(device, "idle timer expired device %d\n", device->id);
- if (device->requested_state == KGSL_STATE_NONE) {
+ if (device->requested_state != KGSL_STATE_SUSPEND) {
if (device->pwrctrl.restore_slumber)
kgsl_pwrctrl_request_state(device, KGSL_STATE_SLUMBER);
else
diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 7d4bbc2..57c418e 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -226,4 +226,13 @@
To compile this driver as a module, choose M here: the module will
be called rc_loopback.
+config IR_TSOP_CIR
+ tristate "TSOP IR remote control"
+ depends on RC_CORE
+ ---help---
+ Say Y if you want to use GPIO based TSOP IR Receiver.
+
+ To compile this driver as a module, choose M here: the module will
+ be called tsop-ir.
+
endif #RC_CORE
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index 52830e5..d5c1a33 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -23,3 +23,4 @@
obj-$(CONFIG_IR_STREAMZAP) += streamzap.o
obj-$(CONFIG_IR_WINBOND_CIR) += winbond-cir.o
obj-$(CONFIG_RC_LOOPBACK) += rc-loopback.o
+obj-$(CONFIG_IR_TSOP_CIR) += tsop-ir.o
diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
index b57fc83..45b0134 100644
--- a/drivers/media/rc/keymaps/Makefile
+++ b/drivers/media/rc/keymaps/Makefile
@@ -70,6 +70,7 @@
rc-hauppauge.o \
rc-rc6-mce.o \
rc-real-audio-220-32-keys.o \
+ rc-samsung-necx.o\
rc-streamzap.o \
rc-tbs-nec.o \
rc-technisat-usb2.o \
diff --git a/drivers/media/rc/keymaps/rc-samsung-necx.c b/drivers/media/rc/keymaps/rc-samsung-necx.c
new file mode 100644
index 0000000..e99c057
--- /dev/null
+++ b/drivers/media/rc/keymaps/rc-samsung-necx.c
@@ -0,0 +1,80 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <media/rc-map.h>
+
+static struct rc_map_table samsung_necx[] = {
+ { 0x70702, KEY_POWER}, /* power */
+ { 0x7070f, KEY_MUTE}, /* mute */
+ { 0x70704, KEY_1},
+ { 0x70705, KEY_2},
+ { 0x70706, KEY_3},
+ { 0x70708, KEY_4},
+ { 0x70709, KEY_5},
+ { 0x7070a, KEY_6},
+ { 0x7070c, KEY_7},
+ { 0x7070d, KEY_8},
+ { 0x7070e, KEY_9},
+ { 0x70711, KEY_0},
+ { 0x70712, KEY_CHANNELUP},
+ { 0x70710, KEY_CHANNELDOWN},
+ { 0x70707, KEY_VOLUMEUP},
+ { 0x7070b, KEY_VOLUMEDOWN},
+ { 0x70760, KEY_UP},
+ { 0x70768, KEY_ENTER}, /* ok */
+ { 0x70761, KEY_DOWN},
+ { 0x70765, KEY_LEFT},
+ { 0x70762, KEY_RIGHT},
+ { 0x7072d, KEY_EXIT},
+ { 0x70749, KEY_RECORD},
+ { 0x70747, KEY_PLAY},
+ { 0x70746, KEY_STOP},
+ { 0x70745, KEY_REWIND},
+ { 0x70748, KEY_FORWARD},
+ { 0x7074a, KEY_PAUSE},
+ { 0x70703, KEY_SLEEP},
+ { 0x7076c, KEY_A}, /* search */
+ { 0x70714, KEY_B}, /* camera */
+ { 0x70715, KEY_C},
+ { 0x70716, KEY_D},
+ { 0x70758, KEY_BACK},
+ { 0x7071a, KEY_MENU},
+ { 0x7076b, KEY_LIST},
+ { 0x70701, KEY_SCREENLOCK},
+ { 0x7071f, KEY_HOME},
+
+};
+
+static struct rc_map_list samsung_necx_map = {
+ .map = {
+ .scan = samsung_necx,
+ .size = ARRAY_SIZE(samsung_necx),
+ .rc_type = RC_TYPE_NEC,
+ .name = RC_MAP_SAMSUNG_NECX,
+ }
+};
+
+static int __init init_rc_map_samsung_necx(void)
+{
+ return rc_map_register(&samsung_necx_map);
+}
+
+static void __exit exit_rc_map_samsung_necx(void)
+{
+ rc_map_unregister(&samsung_necx_map);
+}
+
+module_init(init_rc_map_samsung_necx)
+module_exit(exit_rc_map_samsung_necx)
+
+MODULE_DESCRIPTION("SAMSUNG IR Remote Keymap");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/rc/tsop-ir.c b/drivers/media/rc/tsop-ir.c
new file mode 100644
index 0000000..ffffa9f
--- /dev/null
+++ b/drivers/media/rc/tsop-ir.c
@@ -0,0 +1,198 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <media/rc-core.h>
+#include <media/tsop-ir.h>
+
+#define TSOP_DRIVER_NAME "tsop-rc"
+#define TSOP_DEVICE_NAME "tsop_ir"
+
+struct tsop_remote {
+ struct rc_dev *rcdev;
+ struct mutex lock;
+ unsigned int gpio_nr;
+ bool active_low;
+ bool can_wakeup;
+ struct work_struct work;
+};
+
+static void ir_decoder_work(struct work_struct *work)
+{
+ struct tsop_remote *tsop_dev = container_of(work,
+ struct tsop_remote, work);
+ unsigned int gval;
+ int rc = 0;
+ enum raw_event_type type = IR_SPACE;
+
+ mutex_lock(&tsop_dev->lock);
+ gval = gpio_get_value_cansleep(tsop_dev->gpio_nr);
+
+ if (gval < 0)
+ goto err_get_value;
+
+ if (tsop_dev->active_low)
+ gval = !gval;
+
+ if (gval == 1)
+ type = IR_PULSE;
+
+ rc = ir_raw_event_store_edge(tsop_dev->rcdev, type);
+ if (rc < 0)
+ goto err_get_value;
+
+ ir_raw_event_handle(tsop_dev->rcdev);
+
+err_get_value:
+ mutex_unlock(&tsop_dev->lock);
+}
+
+static irqreturn_t tsop_irq_handler(int irq, void *data)
+{
+ struct tsop_remote *tsop_dev = data;
+
+ schedule_work(&tsop_dev->work);
+
+ return IRQ_HANDLED;
+}
+
+static int __devinit tsop_driver_probe(struct platform_device *pdev)
+{
+ struct tsop_remote *tsop_dev;
+ struct rc_dev *rcdev;
+ const struct tsop_platform_data *pdata = pdev->dev.platform_data;
+ int rc = 0;
+
+ if (!pdata)
+ return -EINVAL;
+
+ if (pdata->gpio_nr < 0)
+ return -EINVAL;
+
+ tsop_dev = kzalloc(sizeof(struct tsop_remote), GFP_KERNEL);
+ if (!tsop_dev)
+ return -ENOMEM;
+
+ mutex_init(&tsop_dev->lock);
+
+ rcdev = rc_allocate_device();
+ if (!rcdev) {
+ rc = -ENOMEM;
+ goto err_allocate_device;
+ }
+
+ rcdev->driver_type = RC_DRIVER_IR_RAW;
+ rcdev->allowed_protos = RC_TYPE_NEC;
+ rcdev->input_name = TSOP_DEVICE_NAME;
+ rcdev->input_id.bustype = BUS_HOST;
+ rcdev->driver_name = TSOP_DRIVER_NAME;
+ rcdev->map_name = RC_MAP_SAMSUNG_NECX;
+
+ tsop_dev->rcdev = rcdev;
+ tsop_dev->gpio_nr = pdata->gpio_nr;
+ tsop_dev->active_low = pdata->active_low;
+ tsop_dev->can_wakeup = pdata->can_wakeup;
+
+ INIT_WORK(&tsop_dev->work, ir_decoder_work);
+
+ rc = gpio_request(pdata->gpio_nr, "tsop-ir");
+ if (rc < 0)
+ goto err_gpio_request;
+ rc = gpio_direction_input(pdata->gpio_nr);
+ if (rc < 0)
+ goto err_gpio_direction_input;
+
+ rc = rc_register_device(rcdev);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "failed to register rc device\n");
+ goto err_register_rc_device;
+ }
+
+ platform_set_drvdata(pdev, tsop_dev);
+
+ rc = request_irq(gpio_to_irq(pdata->gpio_nr), tsop_irq_handler,
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+ "tsop-irq", tsop_dev);
+ if (rc < 0)
+ goto err_request_irq;
+
+ if (pdata->can_wakeup == true) {
+ rc = enable_irq_wake(gpio_to_irq(pdata->gpio_nr));
+ if (rc < 0)
+ goto err_enable_irq_wake;
+ }
+
+ return 0;
+
+err_enable_irq_wake:
+ free_irq(gpio_to_irq(tsop_dev->gpio_nr), tsop_dev);
+err_request_irq:
+ platform_set_drvdata(pdev, NULL);
+ rc_unregister_device(rcdev);
+err_register_rc_device:
+err_gpio_direction_input:
+ gpio_free(pdata->gpio_nr);
+err_gpio_request:
+ rc_free_device(rcdev);
+ rcdev = NULL;
+err_allocate_device:
+ mutex_destroy(&tsop_dev->lock);
+ kfree(tsop_dev);
+ return rc;
+}
+
+static int __devexit tsop_driver_remove(struct platform_device *pdev)
+{
+ struct tsop_remote *tsop_dev = platform_get_drvdata(pdev);
+
+ flush_work_sync(&tsop_dev->work);
+ disable_irq_wake(gpio_to_irq(tsop_dev->gpio_nr));
+ free_irq(gpio_to_irq(tsop_dev->gpio_nr), tsop_dev);
+ platform_set_drvdata(pdev, NULL);
+ rc_unregister_device(tsop_dev->rcdev);
+ gpio_free(tsop_dev->gpio_nr);
+ rc_free_device(tsop_dev->rcdev);
+ mutex_destroy(&tsop_dev->lock);
+ kfree(tsop_dev);
+ return 0;
+}
+
+static struct platform_driver tsop_driver = {
+ .probe = tsop_driver_probe,
+ .remove = __devexit_p(tsop_driver_remove),
+ .driver = {
+ .name = TSOP_DRIVER_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init tsop_init(void)
+{
+ return platform_driver_register(&tsop_driver);
+}
+module_init(tsop_init);
+
+static void __exit tsop_exit(void)
+{
+ platform_driver_unregister(&tsop_driver);
+}
+module_exit(tsop_exit);
+
+MODULE_DESCRIPTION("TSOP IR driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/msm/msm_camera.c b/drivers/media/video/msm/msm_camera.c
index dbf0eae..e609d6e 100644
--- a/drivers/media/video/msm/msm_camera.c
+++ b/drivers/media/video/msm/msm_camera.c
@@ -3652,6 +3652,7 @@
vdata->phy.output_id |= OUTPUT_TYPE_L;
sync->liveshot_enabled = false;
}
+ vdata->phy.p2_phy = vdata->phy.p0_phy;
if (sync->frame_q.len <= 100 && sync->event_q.len <= 100) {
CDBG("%s: enqueue to frame_q from VPE\n", __func__);
msm_enqueue(&sync->frame_q, &qcmd->list_frame);
diff --git a/drivers/platform/msm/ssbi.c b/drivers/platform/msm/ssbi.c
index 8a6dbf7..e2554f5 100644
--- a/drivers/platform/msm/ssbi.c
+++ b/drivers/platform/msm/ssbi.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
* Copyright (c) 2010, Google Inc.
*
* Original authors: Code Aurora Forum
@@ -25,6 +25,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/msm_ssbi.h>
+#include <linux/remote_spinlock.h>
/* SSBI 2.0 controller registers */
#define SSBI2_CMD 0x0008
@@ -75,7 +76,9 @@
struct device *dev;
struct device *slave;
void __iomem *base;
+ bool use_rlock;
spinlock_t lock;
+ remote_spinlock_t rspin_lock;
enum msm_ssbi_controller_type controller_type;
int (*read)(struct msm_ssbi *, u16 addr, u8 *buf, int len);
int (*write)(struct msm_ssbi *, u16 addr, u8 *buf, int len);
@@ -255,9 +258,15 @@
if (ssbi->dev != dev)
return -ENXIO;
- spin_lock_irqsave(&ssbi->lock, flags);
- ret = ssbi->read(ssbi, addr, buf, len);
- spin_unlock_irqrestore(&ssbi->lock, flags);
+ if (ssbi->use_rlock) {
+ remote_spin_lock_irqsave(&ssbi->rspin_lock, flags);
+ ret = ssbi->read(ssbi, addr, buf, len);
+ remote_spin_unlock_irqrestore(&ssbi->rspin_lock, flags);
+ } else {
+ spin_lock_irqsave(&ssbi->lock, flags);
+ ret = ssbi->read(ssbi, addr, buf, len);
+ spin_unlock_irqrestore(&ssbi->lock, flags);
+ }
return ret;
}
@@ -272,9 +281,15 @@
if (ssbi->dev != dev)
return -ENXIO;
- spin_lock_irqsave(&ssbi->lock, flags);
- ret = ssbi->write(ssbi, addr, buf, len);
- spin_unlock_irqrestore(&ssbi->lock, flags);
+ if (ssbi->use_rlock) {
+ remote_spin_lock_irqsave(&ssbi->rspin_lock, flags);
+ ret = ssbi->write(ssbi, addr, buf, len);
+ remote_spin_unlock_irqrestore(&ssbi->rspin_lock, flags);
+ } else {
+ spin_lock_irqsave(&ssbi->lock, flags);
+ ret = ssbi->write(ssbi, addr, buf, len);
+ spin_unlock_irqrestore(&ssbi->lock, flags);
+ }
return ret;
}
@@ -362,6 +377,15 @@
ssbi->write = msm_ssbi_write_bytes;
}
+ if (pdata->rsl_id) {
+ ret = remote_spin_lock_init(&ssbi->rspin_lock, pdata->rsl_id);
+ if (ret) {
+ dev_err(&pdev->dev, "remote spinlock init failed\n");
+ goto err_ssbi_add_slave;
+ }
+ ssbi->use_rlock = 1;
+ }
+
spin_lock_init(&ssbi->lock);
ret = msm_ssbi_add_slave(ssbi, &pdata->slave);
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 22d53e9..c0c398b 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -2541,12 +2541,98 @@
return -EINVAL;
}
+static void pm8921_chg_force_19p2mhz_clk(struct pm8921_chg_chip *chip)
+{
+ int err;
+ u8 temp;
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD3;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD5;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ udelay(183);
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD0;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+ udelay(32);
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD3;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+}
+
+static void pm8921_chg_set_hw_clk_switching(struct pm8921_chg_chip *chip)
+{
+ int err;
+ u8 temp;
+
+ temp = 0xD1;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+
+ temp = 0xD0;
+ err = pm8xxx_writeb(chip->dev->parent, CHG_TEST, temp);
+ if (err) {
+ pr_err("Error %d writing %d to addr %d\n", err, temp, CHG_TEST);
+ return;
+ }
+}
+
#define ENUM_TIMER_STOP_BIT BIT(1)
#define BOOT_DONE_BIT BIT(6)
#define CHG_BATFET_ON_BIT BIT(3)
#define CHG_VCP_EN BIT(0)
#define CHG_BAT_TEMP_DIS_BIT BIT(2)
#define SAFE_CURRENT_MA 1500
+#define VREF_BATT_THERM_FORCE_ON BIT(7)
static int __devinit pm8921_chg_hw_init(struct pm8921_chg_chip *chip)
{
int rc;
@@ -2736,6 +2822,13 @@
/* Disable EOC FSM processing */
pm8xxx_writeb(chip->dev->parent, CHG_BUCK_CTRL_TEST3, 0x91);
+ pm8921_chg_force_19p2mhz_clk(chip);
+
+ rc = pm_chg_masked_write(chip, CHG_CNTRL, VREF_BATT_THERM_FORCE_ON,
+ VREF_BATT_THERM_FORCE_ON);
+ if (rc)
+ pr_err("Failed to Force Vref therm rc=%d\n", rc);
+
rc = pm_chg_charge_dis(chip, charging_disabled);
if (rc) {
pr_err("Failed to disable CHG_CHARGE_DIS bit rc=%d\n", rc);
@@ -2918,6 +3011,32 @@
}
}
+static int pm8921_charger_suspend_noirq(struct device *dev)
+{
+ int rc;
+ struct pm8921_chg_chip *chip = dev_get_drvdata(dev);
+
+ rc = pm_chg_masked_write(chip, CHG_CNTRL, VREF_BATT_THERM_FORCE_ON, 0);
+ if (rc)
+ pr_err("Failed to Force Vref therm off rc=%d\n", rc);
+ pm8921_chg_set_hw_clk_switching(chip);
+ return 0;
+}
+
+static int pm8921_charger_resume_noirq(struct device *dev)
+{
+ int rc;
+ struct pm8921_chg_chip *chip = dev_get_drvdata(dev);
+
+ pm8921_chg_force_19p2mhz_clk(chip);
+
+ rc = pm_chg_masked_write(chip, CHG_CNTRL, VREF_BATT_THERM_FORCE_ON,
+ VREF_BATT_THERM_FORCE_ON);
+ if (rc)
+ pr_err("Failed to Force Vref therm on rc=%d\n", rc);
+ return 0;
+}
+
static int pm8921_charger_resume(struct device *dev)
{
int rc;
@@ -2956,6 +3075,7 @@
pm8921_chg_enable_irq(chip, LOOP_CHANGE_IRQ);
enable_irq_wake(chip->pmic_chg_irq[LOOP_CHANGE_IRQ]);
}
+
return 0;
}
static int __devinit pm8921_charger_probe(struct platform_device *pdev)
@@ -3116,6 +3236,8 @@
}
static const struct dev_pm_ops pm8921_pm_ops = {
.suspend = pm8921_charger_suspend,
+ .suspend_noirq = pm8921_charger_suspend_noirq,
+ .resume_noirq = pm8921_charger_resume_noirq,
.resume = pm8921_charger_resume,
};
static struct platform_driver pm8921_charger_driver = {
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index abc55d2..b39e81c 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -439,7 +439,10 @@
mdp_hist_frame_cnt = hist->frame_cnt;
mutex_unlock(&mdp_hist_mutex);
- wait_for_completion_killable(&mdp_hist_comp);
+ if (wait_for_completion_killable(&mdp_hist_comp)) {
+ pr_err("%s(): histogram bin collection killed", __func__);
+ return -EINVAL;
+ }
mutex_lock(&mdp_hist_mutex);
if (mdp_is_hist_data)
diff --git a/drivers/video/msm/mdp.h b/drivers/video/msm/mdp.h
index 7b67905..35a1453 100644
--- a/drivers/video/msm/mdp.h
+++ b/drivers/video/msm/mdp.h
@@ -42,6 +42,7 @@
extern ulong mdp4_display_intf;
extern spinlock_t mdp_spin_lock;
extern int mdp_rev;
+extern struct mdp_csc_cfg mdp_csc_convert[4];
#define MDP4_REVISION_V1 0
#define MDP4_REVISION_V2 1
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 7b5f464..eed9549 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -698,6 +698,8 @@
void mdp4_hsic_set(struct mdp4_overlay_pipe *pipe, struct dpp_ctrl *ctrl);
void mdp4_hsic_update(struct mdp4_overlay_pipe *pipe);
int mdp4_csc_config(struct mdp_csc_cfg_data *config);
+void mdp4_csc_write(struct mdp_csc_cfg *data, uint32_t base);
+int mdp4_csc_enable(struct mdp_csc_cfg_data *config);
u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num);
void mdp4_init_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num);
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index 1fd0766..1d1d5f1 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -546,7 +546,7 @@
char *vg_base;
uint32 frame_size, src_size, src_xy, dst_size, dst_xy;
uint32 format, pattern, luma_offset, chroma_offset;
- uint32 mask;
+ uint32 mask, curr;
int pnum, ptype;
pnum = pipe->pipe_num - OVERLAY_PIPE_VG1; /* start from 0 */
@@ -564,8 +564,9 @@
pattern = mdp4_overlay_unpack_pattern(pipe);
/* not RGB use VG pipe, pure VG pipe */
+ pipe->op_mode |= MDP4_OP_CSC_EN;
if (ptype != OVERLAY_TYPE_RGB)
- pipe->op_mode |= (MDP4_OP_CSC_EN | MDP4_OP_SRC_DATA_YCBCR);
+ pipe->op_mode |= MDP4_OP_SRC_DATA_YCBCR;
#ifdef MDP4_IGC_LUT_ENABLE
pipe->op_mode |= MDP4_OP_IGC_LUT_EN;
@@ -609,6 +610,17 @@
&chroma_offset);
}
+ /* Ensure proper covert matrix loaded when color space swaps */
+ curr = inpdw(vg_base + 0x0058);
+ mask = 0x600;
+ if ((curr & mask) != (pipe->op_mode & mask)) {
+ curr = ((uint32_t)vg_base) + 0x4000;
+ if (ptype != OVERLAY_TYPE_RGB)
+ mdp4_csc_write(&(mdp_csc_convert[1]), curr);
+ else
+ mdp4_csc_write(&(mdp_csc_convert[0]), curr);
+ }
+
/* luma component plane */
outpdw(vg_base + 0x0010, pipe->srcp0_addr + luma_offset);
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c
index ba6c746..40056f0 100644
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -1232,15 +1232,60 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
+struct mdp_csc_cfg mdp_csc_convert[4] = {
+ { /*RGB2RGB*/
+ 0,
+ {
+ 0x0200, 0x0000, 0x0000,
+ 0x0000, 0x0200, 0x0000,
+ 0x0000, 0x0000, 0x0200,
+ },
+ { 0x0, 0x0, 0x0, },
+ { 0x0, 0x0, 0x0, },
+ { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
+ { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
+ },
+ { /*YUV2RGB*/
+ 0,
+ {
+ 0x0254, 0x0000, 0x0331,
+ 0x0254, 0xff37, 0xfe60,
+ 0x0254, 0x0409, 0x0000,
+ },
+ { 0xfff0, 0xff80, 0xff80, },
+ { 0x0, 0x0, 0x0, },
+ { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
+ { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
+ },
+ { /*RGB2YUV*/
+ 0,
+ {
+ 0x0083, 0x0102, 0x0032,
+ 0x1fb5, 0x1f6c, 0x00e1,
+ 0x00e1, 0x1f45, 0x1fdc
+ },
+ { 0x0, 0x0, 0x0, },
+ { 0x0010, 0x0080, 0x0080, },
+ { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
+ { 0x0010, 0x00eb, 0x0010, 0x00f0, 0x0010, 0x00f0, },
+ },
+ { /*YUV2YUV ???*/
+ 0,
+ {
+ 0x0200, 0x0000, 0x0000,
+ 0x0000, 0x0200, 0x0000,
+ 0x0000, 0x0000, 0x0200,
+ },
+ { 0x0, 0x0, 0x0, },
+ { 0x0, 0x0, 0x0, },
+ { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
+ { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
+ },
+};
-struct mdp4_csc_matrix {
-uint32 csc_mv[9];
-uint32 csc_pre_bv[3];
-uint32 csc_post_bv[3];
-uint32 csc_pre_lv[6];
-uint32 csc_post_lv[6];
-} csc_matrix[3] = {
+struct mdp_csc_cfg csc_matrix[3] = {
{
+ (MDP_CSC_FLAG_YUV_OUT),
{
0x0254, 0x0000, 0x0331,
0x0254, 0xff37, 0xfe60,
@@ -1260,6 +1305,7 @@
},
},
{
+ (MDP_CSC_FLAG_YUV_OUT),
{
0x0254, 0x0000, 0x0331,
0x0254, 0xff37, 0xfe60,
@@ -1279,6 +1325,7 @@
},
},
{
+ (0),
{
0x0200, 0x0000, 0x0000,
0x0000, 0x0200, 0x0000,
@@ -1392,6 +1439,25 @@
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
+void mdp4_vg_csc_convert_setup(int vp_num)
+{
+ struct mdp_csc_cfg_data cfg;
+
+ switch (vp_num) {
+ case 0:
+ cfg.block = MDP_BLOCK_VG_1;
+ break;
+ case 1:
+ cfg.block = MDP_BLOCK_VG_2;
+ break;
+ default:
+ pr_err("%s - invalid vp_num = %d", __func__, vp_num);
+ return;
+ }
+ cfg.csc_data = csc_matrix[vp_num];
+ mdp4_csc_enable(&cfg);
+}
+
void mdp4_vg_csc_setup(int vp_num)
{
/* yuv2rgb */
@@ -1400,6 +1466,7 @@
mdp4_vg_csc_post_bv_setup(vp_num);
mdp4_vg_csc_pre_lv_setup(vp_num);
mdp4_vg_csc_post_lv_setup(vp_num);
+ mdp4_vg_csc_convert_setup(vp_num);
}
void mdp4_vg_csc_update(struct mdp_csc *p)
{
@@ -2347,13 +2414,15 @@
case MDP_BLOCK_DMA_P:
base = 0x93000;
break;
+ case MDP_BLOCK_DMA_S:
+ base = (mdp_rev >= MDP_REV_42) ? 0xA3000 : 0x0;
default:
break;
}
return base;
}
-static int mdp4_csc_enable(struct mdp_csc_cfg_data *config)
+int mdp4_csc_enable(struct mdp_csc_cfg_data *config)
{
uint32_t output, base, temp, mask;
@@ -2365,9 +2434,32 @@
output |= temp;
mask = 0x08 | 0x1800;
break;
+ case MDP_BLOCK_DMA_S:
+ base = 0xA0028;
+ output = (config->csc_data.flags << 3) & (0x08);
+ temp = (config->csc_data.flags << 10) & (0x1800);
+ output |= temp;
+ mask = 0x08 | 0x1800;
+ break;
case MDP_BLOCK_VG_1:
+ base = 0x20058;
+ output = (config->csc_data.flags << 11) & (0x800);
+ temp = (config->csc_data.flags << 8) & (0x600);
+ output |= temp;
+ mask = 0x800 | 0x600;
+ break;
case MDP_BLOCK_VG_2:
+ base = 0x30058;
+ output = (config->csc_data.flags << 11) & (0x800);
+ temp = (config->csc_data.flags << 8) & (0x600);
+ output |= temp;
+ mask = 0x800 | 0x600;
+ break;
case MDP_BLOCK_OVERLAY_1:
+ base = 0x18200;
+ output = config->csc_data.flags;
+ mask = 0x07;
+ break;
default:
pr_err("%s - CSC block does not exist on MDP_BLOCK = %d\n",
__func__, config->block);
@@ -2387,46 +2479,49 @@
#define CSC_LV_OFF 0x600
#define CSC_POST_OFF 0x80
-int mdp4_csc_config(struct mdp_csc_cfg_data *config)
+void mdp4_csc_write(struct mdp_csc_cfg *data, uint32_t base)
{
- int ret = 0;
int i;
- uint32_t base, *off;
-
- base = mdp4_csc_block2base(config->block);
- if (!base)
- return -EINVAL;
-
- /* TODO: implement other CSC block support */
- if (config->block != MDP_BLOCK_DMA_P) {
- pr_warn("%s: Only DMA_P currently supported by CSC.\n",
- __func__);
- return -EINVAL;
- }
+ uint32_t *off;
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
- off = (uint32_t *) (MDP_BASE + base + CSC_MV_OFF);
+ off = (uint32_t *) ((uint32_t) base + CSC_MV_OFF);
for (i = 0; i < 9; i++) {
- outpdw(off, config->csc_data.csc_mv[i]);
+ outpdw(off, data->csc_mv[i]);
off++;
}
- off = (uint32_t *) (MDP_BASE + base + CSC_BV_OFF);
+ off = (uint32_t *) ((uint32_t) base + CSC_BV_OFF);
for (i = 0; i < 3; i++) {
- outpdw(off, config->csc_data.csc_pre_bv[i]);
+ outpdw(off, data->csc_pre_bv[i]);
outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
- config->csc_data.csc_post_bv[i]);
+ data->csc_post_bv[i]);
off++;
}
- off = (uint32_t *) (MDP_BASE + base + CSC_LV_OFF);
+ off = (uint32_t *) ((uint32_t) base + CSC_LV_OFF);
for (i = 0; i < 6; i++) {
- outpdw(off, config->csc_data.csc_pre_lv[i]);
+ outpdw(off, data->csc_pre_lv[i]);
outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
- config->csc_data.csc_post_lv[i]);
+ data->csc_post_lv[i]);
off++;
}
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
+}
+
+int mdp4_csc_config(struct mdp_csc_cfg_data *config)
+{
+ int ret = 0;
+ uint32_t base;
+
+ base = mdp4_csc_block2base(config->block);
+ if (!base) {
+ pr_warn("%s: Block type %d isn't supported by CSC.\n",
+ __func__, config->block);
+ return -EINVAL;
+ }
+
+ mdp4_csc_write(&config->csc_data, (uint32_t) (MDP_BASE + base));
ret = mdp4_csc_enable(config);
diff --git a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
index 7c3325a..522ff16 100644
--- a/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
+++ b/drivers/video/msm/vidc/720p/resource_tracker/vcd_res_tracker.c
@@ -92,17 +92,17 @@
goto bail_out;
}
- if (clk_enable(resource_context.pclk)) {
+ if (clk_prepare_enable(resource_context.pclk)) {
VCDRES_MSG_ERROR("vidc pclk Enable failed\n");
goto bail_out;
}
- if (clk_enable(resource_context.hclk)) {
+ if (clk_prepare_enable(resource_context.hclk)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
goto disable_pclk;
}
- if (clk_enable(resource_context.hclk_div2)) {
+ if (clk_prepare_enable(resource_context.hclk_div2)) {
VCDRES_MSG_ERROR("vidc hclk_div2 Enable failed\n");
goto disable_hclk;
}
@@ -120,9 +120,9 @@
}
msleep(20);
- clk_disable(resource_context.pclk);
- clk_disable(resource_context.hclk);
- clk_disable(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.pclk);
+ clk_disable_unprepare(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk_div2);
clk_put(resource_context.hclk_div2);
clk_put(resource_context.hclk);
@@ -144,9 +144,9 @@
return true;
disable_hclk:
- clk_disable(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk);
disable_pclk:
- clk_disable(resource_context.pclk);
+ clk_disable_unprepare(resource_context.pclk);
bail_out:
if (resource_context.pclk) {
clk_put(resource_context.pclk);
@@ -175,7 +175,7 @@
VCDRES_MSG_LOW("%s(): Enabling the clocks ...\n", __func__);
- if (clk_enable(resource_context.pclk)) {
+ if (clk_prepare_enable(resource_context.pclk)) {
VCDRES_MSG_ERROR("vidc pclk Enable failed\n");
clk_put(resource_context.hclk);
@@ -184,7 +184,7 @@
return false;
}
- if (clk_enable(resource_context.hclk)) {
+ if (clk_prepare_enable(resource_context.hclk)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
clk_put(resource_context.pclk);
clk_put(resource_context.hclk_div2);
@@ -192,7 +192,7 @@
return false;
}
- if (clk_enable(resource_context.hclk_div2)) {
+ if (clk_prepare_enable(resource_context.hclk_div2)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
clk_put(resource_context.hclk);
clk_put(resource_context.pclk);
@@ -253,9 +253,9 @@
VCDRES_MSG_LOW("%s(): Disabling the clocks ...\n", __func__);
resource_context.clock_enabled = 0;
- clk_disable(resource_context.hclk);
- clk_disable(resource_context.hclk_div2);
- clk_disable(resource_context.pclk);
+ clk_disable_unprepare(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.pclk);
mutex_unlock(&resource_context.lock);
return true;
@@ -311,17 +311,17 @@
goto release_all_clks;
}
- if (clk_enable(resource_context.pclk)) {
+ if (clk_prepare_enable(resource_context.pclk)) {
VCDRES_MSG_ERROR("vidc pclk Enable failed\n");
goto release_all_clks;
}
- if (clk_enable(resource_context.hclk)) {
+ if (clk_prepare_enable(resource_context.hclk)) {
VCDRES_MSG_ERROR("vidc hclk Enable failed\n");
goto disable_pclk;
}
- if (clk_enable(resource_context.hclk_div2)) {
+ if (clk_prepare_enable(resource_context.hclk_div2)) {
VCDRES_MSG_ERROR("vidc hclk_div2 Enable failed\n");
goto disable_hclk_pclk;
}
@@ -333,9 +333,9 @@
}
msleep(20);
- clk_disable(resource_context.pclk);
- clk_disable(resource_context.hclk);
- clk_disable(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.pclk);
+ clk_disable_unprepare(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk_div2);
}
resource_context.rail_enabled = 1;
@@ -343,11 +343,11 @@
return true;
disable_and_release_all_clks:
- clk_disable(resource_context.hclk_div2);
+ clk_disable_unprepare(resource_context.hclk_div2);
disable_hclk_pclk:
- clk_disable(resource_context.hclk);
+ clk_disable_unprepare(resource_context.hclk);
disable_pclk:
- clk_disable(resource_context.pclk);
+ clk_disable_unprepare(resource_context.pclk);
release_all_clks:
clk_put(resource_context.hclk_div2);
resource_context.hclk_div2 = NULL;
@@ -412,7 +412,7 @@
VCDRES_MSG_ERROR("Request AXI bus QOS fails.");
return false;
}
- clk_enable(ebi1_clk);
+ clk_prepare_enable(ebi1_clk);
}
#endif
@@ -427,7 +427,7 @@
#ifdef AXI_CLK_SCALING
VCDRES_MSG_MED("\n res_trk_power_down()::"
"Calling AXI remove requirement\n");
- clk_disable(ebi1_clk);
+ clk_disable_unprepare(ebi1_clk);
clk_put(ebi1_clk);
#endif
VCDRES_MSG_MED("\n res_trk_power_down():: Calling "
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index cac7758..427465d 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -335,6 +335,10 @@
struct mdp_pcc_coeff r, g, b;
};
+#define MDP_CSC_FLAG_ENABLE 0x1
+#define MDP_CSC_FLAG_YUV_IN 0x2
+#define MDP_CSC_FLAG_YUV_OUT 0x4
+
struct mdp_csc_cfg {
/* flags for enable CSC, toggling RGB,YUV input/output */
uint32_t flags;
diff --git a/include/linux/msm_ssbi.h b/include/linux/msm_ssbi.h
index e90398a..647bc06 100644
--- a/include/linux/msm_ssbi.h
+++ b/include/linux/msm_ssbi.h
@@ -1,5 +1,5 @@
/* Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
* Author: Dima Zavin <dima@android.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -30,6 +30,7 @@
};
struct msm_ssbi_platform_data {
+ const char *rsl_id;
struct msm_ssbi_slave_info slave;
enum msm_ssbi_controller_type controller_type;
};
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index e03944d..664cc8f 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -149,7 +149,8 @@
* for msm_otg driver.
* @phy_init_seq: PHY configuration sequence. val, reg pairs
* terminated by -1.
- * @vbus_power: VBUS power on/off routine.
+ * @vbus_power: VBUS power on/off routine.It should return result
+ * as success(zero value) or failure(non-zero value).
* @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
* @mode: Supported mode (OTG/peripheral/host).
* @otg_control: OTG switch controlled by user/Id pin
@@ -166,7 +167,7 @@
*/
struct msm_otg_platform_data {
int *phy_init_seq;
- void (*vbus_power)(bool on);
+ int (*vbus_power)(bool on);
unsigned power_budget;
enum usb_mode_type mode;
enum otg_control_type otg_control;
diff --git a/include/media/rc-map.h b/include/media/rc-map.h
index 4e1409e..226ea68 100644
--- a/include/media/rc-map.h
+++ b/include/media/rc-map.h
@@ -129,6 +129,7 @@
#define RC_MAP_RC5_TV "rc-rc5-tv"
#define RC_MAP_RC6_MCE "rc-rc6-mce"
#define RC_MAP_REAL_AUDIO_220_32_KEYS "rc-real-audio-220-32-keys"
+#define RC_MAP_SAMSUNG_NECX "rc-samsung-necx"
#define RC_MAP_STREAMZAP "rc-streamzap"
#define RC_MAP_TBS_NEC "rc-tbs-nec"
#define RC_MAP_TECHNISAT_USB2 "rc-technisat-usb2"
diff --git a/include/media/tsop-ir.h b/include/media/tsop-ir.h
new file mode 100644
index 0000000..e94ccb1
--- /dev/null
+++ b/include/media/tsop-ir.h
@@ -0,0 +1,23 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __TSOP_IR_H__
+#define __TSOP_IR_H__
+
+struct tsop_platform_data {
+ unsigned int gpio_nr;
+ bool active_low;
+ bool can_wakeup;
+};
+
+#endif /* __TSOP_IR_H__ */
+
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index 70ea0df..f8cf37d 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -466,6 +466,7 @@
zone->present_pages += onlined_pages;
zone->zone_pgdat->node_present_pages += onlined_pages;
+ drain_all_pages();
if (need_zonelists_rebuild)
build_all_zonelists(zone);
else
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index 74b1d2d..2e4c47a 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -2040,10 +2040,13 @@
if (err < 0)
mgmt_pending_remove(cmd);
else if (lmp_le_capable(hdev)) {
+ cmd = mgmt_pending_find(MGMT_OP_STOP_DISCOVERY, index);
+ if (!cmd)
+ mgmt_pending_add(sk, MGMT_OP_STOP_DISCOVERY, index,
+ NULL, 0);
hdev->disco_int_phase = 1;
hdev->disco_int_count = 0;
hdev->disco_state = SCAN_BR;
- mgmt_pending_add(sk, MGMT_OP_STOP_DISCOVERY, index, NULL, 0);
del_timer(&hdev->disco_le_timer);
del_timer(&hdev->disco_timer);
mod_timer(&hdev->disco_timer,