commit 28959576b1fbdc18c4c972c1b8b744db73d81641
author Laxminath Kasam <lkasam@codeaurora.org> Tue Jul 02 16:20:18 2013 +0530
committer Laxminath Kasam <lkasam@codeaurora.org> Fri Jul 12 17:57:15 2013 +0530
tree 01b909d10a509f087095c01419a3eae2cc37d533
parent 502f45d3494393c49f8d0e5a4a61530977fa19d8

ASoC: wcd9310: Fix DMIC current leakage after disable

Observed after disabling DMIC path, some DMICs observe
power leakage of around 2mA and affecting power numbers.
This happens due to the DMIC clock runs off MCLK. 2 Stage
of Dividers are used to  generate various DMIC Clock Freq.
Since the SW Enable/Disabling is async to MCLK, the Divider
will either hold the last stage 0 or 1.
Manually force the digital mic clock pin to GPIO mode from
functional mode through the TLMM mux option and force the value
of DMIC voltage to 0V. This will avoid any current leakage.

Change-Id: Id2018aee27c4b31b0de8a9094613c1b07fa1112d
CRs-Fixed: 504468
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>

sound/soc/codecs/wcd9310.c

diff --git a/sound/soc/codecs/wcd9310.c b/sound/soc/codecs/wcd9310.c
index 69e4cca..212924fd 100644
--- a/sound/soc/codecs/wcd9310.c
+++ b/sound/soc/codecs/wcd9310.c
@@ -2639,17 +2639,31 @@
 	case SND_SOC_DAPM_PRE_PMU:
 
 		(*dmic_clk_cnt)++;
-		if (*dmic_clk_cnt == 1)
+		if (*dmic_clk_cnt == 1) {
+			snd_soc_update_bits(codec,
+					TABLA_A_CDC_DMIC_CLK0_MODE, 0x7, 0x0);
+			snd_soc_update_bits(codec,
+					TABLA_A_CDC_DMIC_CLK1_MODE, 0x7, 0x0);
+			snd_soc_update_bits(codec,
+					TABLA_A_CDC_DMIC_CLK2_MODE, 0x7, 0x0);
 			snd_soc_update_bits(codec, TABLA_A_CDC_CLK_DMIC_CTL,
 					dmic_clk_en, dmic_clk_en);
+		}
 
 		break;
 	case SND_SOC_DAPM_POST_PMD:
 
 		(*dmic_clk_cnt)--;
-		if (*dmic_clk_cnt  == 0)
+		if (*dmic_clk_cnt  == 0) {
 			snd_soc_update_bits(codec, TABLA_A_CDC_CLK_DMIC_CTL,
 					dmic_clk_en, 0);
+			snd_soc_update_bits(codec,
+					TABLA_A_CDC_DMIC_CLK0_MODE, 0x7, 0x4);
+			snd_soc_update_bits(codec,
+					TABLA_A_CDC_DMIC_CLK1_MODE, 0x7, 0x4);
+			snd_soc_update_bits(codec,
+					TABLA_A_CDC_DMIC_CLK2_MODE, 0x7, 0x4);
+		}
 		break;
 	}
 	return 0;
@@ -8772,6 +8786,13 @@
 				      tabla_2_higher_codec_reg_init_val[i].mask,
 				      tabla_2_higher_codec_reg_init_val[i].val);
 	}
+	snd_soc_update_bits(codec, TABLA_A_CDC_DMIC_CLK0_MODE, 0x7, 0x4);
+	snd_soc_update_bits(codec, TABLA_A_CDC_DMIC_CLK1_MODE, 0x7, 0x4);
+	snd_soc_update_bits(codec, TABLA_A_CDC_DMIC_CLK2_MODE, 0x7, 0x4);
+	snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE0, 0x90, 0x90);
+	snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE1, 0x8, 0x8);
+	snd_soc_update_bits(codec, TABLA_A_PIN_CTL_DATA0, 0x90, 0x0);
+	snd_soc_update_bits(codec, TABLA_A_PIN_CTL_DATA1, 0x8, 0x0);
 }
 
 static void tabla_update_reg_address(struct tabla_priv *priv)