commit 29081e17a8bddce7e43cd0446f4c74652337518e
author Mark Rutland <mark.rutland@arm.com> Wed Nov 21 17:02:51 2012 -0500
committer Ashwin Chaugule <ashwinc@codeaurora.org> Mon Dec 17 13:31:47 2012 -0500
tree 36f1620a8b5cdebcb7e7d07487ca4abc5288e119
parent 9d7b06a1167483244599c29527bc6b95063c7123

ARM: perf: add L2x0 PMU driver

This patch adds initial support for the PMU featured in the L2x0
series of Level 2 Cache Controllers, supporting L220 & PL310.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Change-Id: I04d54f5b2586264ac3325a0ed19c452d25f8fd4c
[ashwinc@codeaurora.org: Remove unused functions for passing compilation.]
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

arch/arm/include/asm/perf_event.h

diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index a40f81e..4f41fd6 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -22,6 +22,7 @@
 	ARM_PERF_PMU_ID_CA9,
 	ARM_PERF_PMU_ID_CA5,
 	ARM_PERF_PMU_ID_CA15,
+	ARM_PERF_PMU_ID_L2X0,
 	ARM_PERF_PMU_ID_CA7,
 	ARM_PERF_PMU_ID_SCORPION,
 	ARM_PERF_PMU_ID_SCORPIONMP,