msm: qdss: disable cycle accurate trace for Krait pass2 by default
To maximize the amount of trace that can fit in the ETB, default
cycle accurate tracing to off for Krait pass2.
Leave cycle accurate tracing on for Krait pass1 since it doesn't
support non-cycle accurate tracing. Also default Krait pass1 to
trace everything i.e. exclude nothing since include filtering is
also not supported on Krait pass1.
Change-Id: I4c3c160ff35899896f410cdeb274870f6f3f135a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
diff --git a/arch/arm/mach-msm/qdss-etm.c b/arch/arm/mach-msm/qdss-etm.c
index dbc1c10..4bc3f495 100644
--- a/arch/arm/mach-msm/qdss-etm.c
+++ b/arch/arm/mach-msm/qdss-etm.c
@@ -27,6 +27,7 @@
#include <linux/sysfs.h>
#include <linux/stat.h>
#include <asm/sections.h>
+#include <mach/socinfo.h>
#include "qdss.h"
@@ -196,8 +197,6 @@
};
static struct etm_ctx etm = {
- .mode = 0x2,
- .ctrl = 0x1000,
.trigger_event = 0x406F,
.enable_event = 0x6F,
.enable_ctrl1 = 0x1,
@@ -508,8 +507,12 @@
mutex_lock(&etm.mutex);
if (val) {
- etm.mode = 0x3;
- etm.ctrl = 0x1000;
+ etm.mode = ETM_MODE_EXCLUDE;
+ etm.ctrl = 0x0;
+ if (cpu_is_krait_v1()) {
+ etm.mode |= ETM_MODE_CYCACC;
+ etm.ctrl |= BIT(12);
+ }
etm.trigger_event = 0x406F;
etm.startstop_ctrl = 0x0;
etm.enable_event = 0x6F;
@@ -1168,7 +1171,7 @@
static int __init etm_arch_init(void)
{
- int ret;
+ int ret, i;
/* use cpu 0 for setup */
int cpu = 0;
uint32_t etmidr;
@@ -1200,6 +1203,20 @@
etm.nr_ext_out = BMVAL(etmccr, 20, 22);
etm.nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
+ if (cpu_is_krait_v1()) {
+ /* Krait pass1 doesn't support include filtering and non-cycle
+ * accurate tracing
+ */
+ etm.mode = (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC);
+ etm.ctrl = 0x1000;
+ etm.enable_ctrl1 = 0x1000000;
+ for (i = 0; i < etm.nr_addr_cmp; i++) {
+ etm.addr_val[i] = 0x0;
+ etm.addr_acctype[i] = 0x0;
+ etm.addr_type[i] = ETM_ADDR_TYPE_NONE;
+ }
+ }
+
/* Vote for ETM power/clock disable */
etm_set_pwrdwn(cpu);
ETM_LOCK(cpu);