msm: pil-8960: Break off Riva support into separate driver
Implement the Riva boot and shutdown support as a platform
driver.
Change-Id: I4d9227009b817f2f4b530ebf1eecfb3d8844dd58
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
diff --git a/arch/arm/configs/msm8960_defconfig b/arch/arm/configs/msm8960_defconfig
index f68aa30..d08e059 100644
--- a/arch/arm/configs/msm8960_defconfig
+++ b/arch/arm/configs/msm8960_defconfig
@@ -61,6 +61,7 @@
CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y
# CONFIG_MSM_HW3D is not set
CONFIG_MSM_PIL_QDSP6V4=y
+CONFIG_MSM_PIL_RIVA=y
CONFIG_MSM_SUBSYSTEM_RESTART=y
CONFIG_MSM_MODEM_8960=y
CONFIG_MSM_LPASS_8960=y
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index c049b5f..d80586e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1611,6 +1611,14 @@
The QDSP6 is a low power DSP used in audio, modem firmware, and modem
software applications.
+config MSM_PIL_RIVA
+ tristate "RIVA (WCNSS) Boot Support"
+ depends on MSM_PIL
+ help
+ Support for booting and shutting down the RIVA processor (WCNSS).
+ Riva is the wireless subsystem processor used in bluetooth, wireless
+ LAN, and FM software applications.
+
config MSM_SCM
bool "Secure Channel Manager (SCM) support"
default n
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index f826659..d6d0312 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -73,6 +73,7 @@
endif
obj-$(CONFIG_MSM_PIL_QDSP6V3) += pil-q6v3.o
obj-$(CONFIG_MSM_PIL_QDSP6V4) += pil-q6v4.o
+obj-$(CONFIG_MSM_PIL_RIVA) += pil-riva.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_ARCH_FSM9XXX) += sirc-fsm9xxx.o
obj-$(CONFIG_MSM_FIQ_SUPPORT) += fiq_glue.o
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 41074d1..3b89a32 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -1538,6 +1538,7 @@
&msm_8960_q6_lpass,
&msm_8960_q6_mss_fw,
&msm_8960_q6_mss_sw,
+ &msm_8960_riva,
&msm8960_device_qup_spi_gsbi1,
&msm8960_device_qup_i2c_gsbi3,
&msm8960_device_qup_i2c_gsbi4,
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index 9c6cd9b..bc9a2ba 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -1745,6 +1745,7 @@
&msm_8960_q6_lpass,
&msm_8960_q6_mss_fw,
&msm_8960_q6_mss_sw,
+ &msm_8960_riva,
&msm8960_device_otg,
&msm8960_device_gadget_peripheral,
&msm_device_hsusb_host,
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 172e124..6b268f3 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -926,6 +926,21 @@
.dev.platform_data = &msm_8960_q6_mss_sw_data,
};
+static struct resource msm_8960_riva_resources[] = {
+ {
+ .start = 0x03204000,
+ .end = 0x03204000 + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device msm_8960_riva = {
+ .name = "pil_riva",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(msm_8960_riva_resources),
+ .resource = msm_8960_riva_resources,
+};
+
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 264e9a9..be96e13 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -178,6 +178,7 @@
extern struct platform_device msm_8960_q6_lpass;
extern struct platform_device msm_8960_q6_mss_fw;
extern struct platform_device msm_8960_q6_mss_sw;
+extern struct platform_device msm_8960_riva;
extern struct platform_device apq_pcm;
extern struct platform_device apq_pcm_routing;
diff --git a/arch/arm/mach-msm/peripheral-reset-8960.c b/arch/arm/mach-msm/peripheral-reset-8960.c
index fa22e4e..d01851e 100644
--- a/arch/arm/mach-msm/peripheral-reset-8960.c
+++ b/arch/arm/mach-msm/peripheral-reset-8960.c
@@ -17,7 +17,6 @@
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/regulator/consumer.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
@@ -28,195 +27,15 @@
#include "peripheral-loader.h"
#include "scm-pas.h"
-#define MSM_RIVA_PHYS 0x03204000
-#define RIVA_PMU_A2XB_CFG (msm_riva_base + 0xB8)
-#define RIVA_PMU_A2XB_CFG_EN BIT(0)
-
-#define RIVA_PMU_CFG (msm_riva_base + 0x28)
-#define RIVA_PMU_CFG_WARM_BOOT BIT(0)
-#define RIVA_PMU_CFG_IRIS_XO_MODE 0x6
-#define RIVA_PMU_CFG_IRIS_XO_MODE_48 (3 << 1)
-
-#define RIVA_PMU_OVRD_VAL (msm_riva_base + 0x30)
-#define RIVA_PMU_OVRD_VAL_CCPU_RESET BIT(0)
-#define RIVA_PMU_OVRD_VAL_CCPU_CLK BIT(1)
-
-#define RIVA_PMU_CCPU_CTL (msm_riva_base + 0x9C)
-#define RIVA_PMU_CCPU_CTL_HIGH_IVT BIT(0)
-#define RIVA_PMU_CCPU_CTL_REMAP_EN BIT(2)
-
-#define RIVA_PMU_CCPU_BOOT_REMAP_ADDR (msm_riva_base + 0xA0)
-
-#define RIVA_PLL_MODE (MSM_CLK_CTL_BASE + 0x31A0)
-#define PLL_MODE_OUTCTRL BIT(0)
-#define PLL_MODE_BYPASSNL BIT(1)
-#define PLL_MODE_RESET_N BIT(2)
-#define PLL_MODE_REF_XO_SEL 0x30
-#define PLL_MODE_REF_XO_SEL_CXO (2 << 4)
-#define PLL_MODE_REF_XO_SEL_RF (3 << 4)
-#define RIVA_PLL_L_VAL (MSM_CLK_CTL_BASE + 0x31A4)
-#define RIVA_PLL_M_VAL (MSM_CLK_CTL_BASE + 0x31A8)
-#define RIVA_PLL_N_VAL (MSM_CLK_CTL_BASE + 0x31Ac)
-#define RIVA_PLL_CONFIG (MSM_CLK_CTL_BASE + 0x31B4)
-#define RIVA_PLL_STATUS (MSM_CLK_CTL_BASE + 0x31B8)
-
-#define RIVA_PMU_ROOT_CLK_SEL (msm_riva_base + 0xC8)
-#define RIVA_PMU_ROOT_CLK_SEL_3 BIT(2)
-
-#define RIVA_PMU_CLK_ROOT3 (msm_riva_base + 0x78)
-#define RIVA_PMU_CLK_ROOT3_ENA BIT(0)
-#define RIVA_PMU_CLK_ROOT3_SRC0_DIV 0x3C
-#define RIVA_PMU_CLK_ROOT3_SRC0_DIV_2 (1 << 2)
-#define RIVA_PMU_CLK_ROOT3_SRC0_SEL 0x1C0
-#define RIVA_PMU_CLK_ROOT3_SRC0_SEL_RIVA (1 << 6)
-#define RIVA_PMU_CLK_ROOT3_SRC1_DIV 0x1E00
-#define RIVA_PMU_CLK_ROOT3_SRC1_DIV_2 (1 << 9)
-#define RIVA_PMU_CLK_ROOT3_SRC1_SEL 0xE000
-#define RIVA_PMU_CLK_ROOT3_SRC1_SEL_RIVA (1 << 13)
-
#define PPSS_RESET (MSM_CLK_CTL_BASE + 0x2594)
#define PPSS_PROC_CLK_CTL (MSM_CLK_CTL_BASE + 0x2588)
#define PPSS_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2580)
-static void __iomem *msm_riva_base;
-static unsigned long riva_start;
-
static int verify_blob(struct pil_desc *pil, u32 phy_addr, size_t size)
{
return 0;
}
-static int init_image_riva_untrusted(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
- riva_start = ehdr->e_entry;
- return 0;
-}
-
-static int reset_riva_untrusted(struct pil_desc *pil)
-{
- u32 reg;
- bool xo;
-
- /* Enable A2XB bridge */
- reg = readl_relaxed(RIVA_PMU_A2XB_CFG);
- reg |= RIVA_PMU_A2XB_CFG_EN;
- writel_relaxed(reg, RIVA_PMU_A2XB_CFG);
-
- /* Determine which XO to use */
- reg = readl_relaxed(RIVA_PMU_CFG);
- xo = (reg & RIVA_PMU_CFG_IRIS_XO_MODE) == RIVA_PMU_CFG_IRIS_XO_MODE_48;
-
- /* Program PLL 13 to 960 MHz */
- reg = readl_relaxed(RIVA_PLL_MODE);
- reg &= ~(PLL_MODE_BYPASSNL | PLL_MODE_OUTCTRL | PLL_MODE_RESET_N);
- writel_relaxed(reg, RIVA_PLL_MODE);
-
- if (xo)
- writel_relaxed(0x40000C00 | 40, RIVA_PLL_L_VAL);
- else
- writel_relaxed(0x40000C00 | 50, RIVA_PLL_L_VAL);
- writel_relaxed(0, RIVA_PLL_M_VAL);
- writel_relaxed(1, RIVA_PLL_N_VAL);
- writel_relaxed(0x01495227, RIVA_PLL_CONFIG);
-
- reg = readl_relaxed(RIVA_PLL_MODE);
- reg &= ~(PLL_MODE_REF_XO_SEL);
- reg |= xo ? PLL_MODE_REF_XO_SEL_RF : PLL_MODE_REF_XO_SEL_CXO;
- writel_relaxed(reg, RIVA_PLL_MODE);
-
- /* Enable PLL 13 */
- reg |= PLL_MODE_BYPASSNL;
- writel_relaxed(reg, RIVA_PLL_MODE);
-
- /*
- * H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe.
- */
- mb();
- usleep_range(10, 20);
-
- reg |= PLL_MODE_RESET_N;
- writel_relaxed(reg, RIVA_PLL_MODE);
- reg |= PLL_MODE_OUTCTRL;
- writel_relaxed(reg, RIVA_PLL_MODE);
-
- /* Wait for PLL to settle */
- mb();
- usleep_range(50, 100);
-
- /* Configure cCPU for 240 MHz */
- reg = readl_relaxed(RIVA_PMU_CLK_ROOT3);
- if (readl_relaxed(RIVA_PMU_ROOT_CLK_SEL) & RIVA_PMU_ROOT_CLK_SEL_3) {
- reg &= ~(RIVA_PMU_CLK_ROOT3_SRC0_SEL |
- RIVA_PMU_CLK_ROOT3_SRC0_DIV);
- reg |= RIVA_PMU_CLK_ROOT3_SRC0_SEL_RIVA |
- RIVA_PMU_CLK_ROOT3_SRC0_DIV_2;
- } else {
- reg &= ~(RIVA_PMU_CLK_ROOT3_SRC1_SEL |
- RIVA_PMU_CLK_ROOT3_SRC1_DIV);
- reg |= RIVA_PMU_CLK_ROOT3_SRC1_SEL_RIVA |
- RIVA_PMU_CLK_ROOT3_SRC1_DIV_2;
- }
- writel_relaxed(reg, RIVA_PMU_CLK_ROOT3);
- reg |= RIVA_PMU_CLK_ROOT3_ENA;
- writel_relaxed(reg, RIVA_PMU_CLK_ROOT3);
- reg = readl_relaxed(RIVA_PMU_ROOT_CLK_SEL);
- reg ^= RIVA_PMU_ROOT_CLK_SEL_3;
- writel_relaxed(reg, RIVA_PMU_ROOT_CLK_SEL);
-
- /* Use the high vector table */
- reg = readl_relaxed(RIVA_PMU_CCPU_CTL);
- reg |= RIVA_PMU_CCPU_CTL_HIGH_IVT | RIVA_PMU_CCPU_CTL_REMAP_EN;
- writel_relaxed(reg, RIVA_PMU_CCPU_CTL);
-
- /* Set base memory address */
- writel_relaxed(riva_start >> 16, RIVA_PMU_CCPU_BOOT_REMAP_ADDR);
-
- /* Clear warmboot bit indicating this is a cold boot */
- reg = readl_relaxed(RIVA_PMU_CFG);
- reg &= ~(RIVA_PMU_CFG_WARM_BOOT);
- writel_relaxed(reg, RIVA_PMU_CFG);
-
- /* Enable the cCPU clock */
- reg = readl_relaxed(RIVA_PMU_OVRD_VAL);
- reg |= RIVA_PMU_OVRD_VAL_CCPU_CLK;
- writel_relaxed(reg, RIVA_PMU_OVRD_VAL);
-
- /* Take cCPU out of reset */
- reg |= RIVA_PMU_OVRD_VAL_CCPU_RESET;
- writel_relaxed(reg, RIVA_PMU_OVRD_VAL);
-
- return 0;
-}
-
-static int shutdown_riva_untrusted(struct pil_desc *pil)
-{
- u32 reg;
- /* Put riva into reset */
- reg = readl_relaxed(RIVA_PMU_OVRD_VAL);
- reg &= ~(RIVA_PMU_OVRD_VAL_CCPU_RESET | RIVA_PMU_OVRD_VAL_CCPU_CLK);
- writel_relaxed(reg, RIVA_PMU_OVRD_VAL);
- return 0;
-}
-
-static int init_image_riva_trusted(struct pil_desc *pil, const u8 *metadata,
- size_t size)
-{
- return pas_init_image(PAS_RIVA, metadata, size);
-}
-
-static int reset_riva_trusted(struct pil_desc *pil)
-{
- return pas_auth_and_reset(PAS_RIVA);
-}
-
-static int shutdown_riva_trusted(struct pil_desc *pil)
-{
- return pas_shutdown(PAS_RIVA);
-}
-
static int init_image_dsps_untrusted(struct pil_desc *pil, const u8 *metadata,
size_t size)
{
@@ -273,13 +92,6 @@
return pas_shutdown(PAS_TZAPPS);
}
-static struct pil_reset_ops pil_riva_ops = {
- .init_image = init_image_riva_untrusted,
- .verify_blob = verify_blob,
- .auth_and_reset = reset_riva_untrusted,
- .shutdown = shutdown_riva_untrusted,
-};
-
struct pil_reset_ops pil_dsps_ops = {
.init_image = init_image_dsps_untrusted,
.verify_blob = verify_blob,
@@ -294,16 +106,6 @@
.shutdown = shutdown_tzapps,
};
-static struct platform_device pil_riva = {
- .name = "pil_riva",
-};
-
-static struct pil_desc pil_riva_desc = {
- .name = "wcnss",
- .dev = &pil_riva.dev,
- .ops = &pil_riva_ops,
-};
-
static struct platform_device pil_dsps = {
.name = "pil_dsps",
};
@@ -331,12 +133,6 @@
pil_dsps_ops.auth_and_reset = reset_dsps_trusted;
pil_dsps_ops.shutdown = shutdown_dsps_trusted;
}
-
- if (pas_supported(PAS_RIVA) > 0) {
- pil_riva_ops.init_image = init_image_riva_trusted;
- pil_riva_ops.auth_and_reset = reset_riva_trusted;
- pil_riva_ops.shutdown = shutdown_riva_trusted;
- }
}
static int __init msm_peripheral_reset_init(void)
@@ -355,12 +151,6 @@
BUG_ON(platform_device_register(&pil_tzapps));
BUG_ON(msm_pil_register(&pil_tzapps_desc));
- msm_riva_base = ioremap(MSM_RIVA_PHYS, SZ_256);
- if (!msm_riva_base)
- return -ENOMEM;
- BUG_ON(platform_device_register(&pil_riva));
- BUG_ON(msm_pil_register(&pil_riva_desc));
-
return 0;
}
arch_initcall(msm_peripheral_reset_init);
diff --git a/arch/arm/mach-msm/pil-riva.c b/arch/arm/mach-msm/pil-riva.c
new file mode 100644
index 0000000..da6fbb0
--- /dev/null
+++ b/arch/arm/mach-msm/pil-riva.c
@@ -0,0 +1,297 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/elf.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include <mach/msm_iomap.h>
+
+#include "peripheral-loader.h"
+#include "scm-pas.h"
+
+#define RIVA_PMU_A2XB_CFG 0xB8
+#define RIVA_PMU_A2XB_CFG_EN BIT(0)
+
+#define RIVA_PMU_CFG 0x28
+#define RIVA_PMU_CFG_WARM_BOOT BIT(0)
+#define RIVA_PMU_CFG_IRIS_XO_MODE 0x6
+#define RIVA_PMU_CFG_IRIS_XO_MODE_48 (3 << 1)
+
+#define RIVA_PMU_OVRD_VAL 0x30
+#define RIVA_PMU_OVRD_VAL_CCPU_RESET BIT(0)
+#define RIVA_PMU_OVRD_VAL_CCPU_CLK BIT(1)
+
+#define RIVA_PMU_CCPU_CTL 0x9C
+#define RIVA_PMU_CCPU_CTL_HIGH_IVT BIT(0)
+#define RIVA_PMU_CCPU_CTL_REMAP_EN BIT(2)
+
+#define RIVA_PMU_CCPU_BOOT_REMAP_ADDR 0xA0
+
+#define RIVA_PLL_MODE (MSM_CLK_CTL_BASE + 0x31A0)
+#define PLL_MODE_OUTCTRL BIT(0)
+#define PLL_MODE_BYPASSNL BIT(1)
+#define PLL_MODE_RESET_N BIT(2)
+#define PLL_MODE_REF_XO_SEL 0x30
+#define PLL_MODE_REF_XO_SEL_CXO (2 << 4)
+#define PLL_MODE_REF_XO_SEL_RF (3 << 4)
+#define RIVA_PLL_L_VAL (MSM_CLK_CTL_BASE + 0x31A4)
+#define RIVA_PLL_M_VAL (MSM_CLK_CTL_BASE + 0x31A8)
+#define RIVA_PLL_N_VAL (MSM_CLK_CTL_BASE + 0x31Ac)
+#define RIVA_PLL_CONFIG (MSM_CLK_CTL_BASE + 0x31B4)
+#define RIVA_PLL_STATUS (MSM_CLK_CTL_BASE + 0x31B8)
+
+#define RIVA_PMU_ROOT_CLK_SEL 0xC8
+#define RIVA_PMU_ROOT_CLK_SEL_3 BIT(2)
+
+#define RIVA_PMU_CLK_ROOT3 0x78
+#define RIVA_PMU_CLK_ROOT3_ENA BIT(0)
+#define RIVA_PMU_CLK_ROOT3_SRC0_DIV 0x3C
+#define RIVA_PMU_CLK_ROOT3_SRC0_DIV_2 (1 << 2)
+#define RIVA_PMU_CLK_ROOT3_SRC0_SEL 0x1C0
+#define RIVA_PMU_CLK_ROOT3_SRC0_SEL_RIVA (1 << 6)
+#define RIVA_PMU_CLK_ROOT3_SRC1_DIV 0x1E00
+#define RIVA_PMU_CLK_ROOT3_SRC1_DIV_2 (1 << 9)
+#define RIVA_PMU_CLK_ROOT3_SRC1_SEL 0xE000
+#define RIVA_PMU_CLK_ROOT3_SRC1_SEL_RIVA (1 << 13)
+
+struct riva_data {
+ void __iomem *base;
+ unsigned long start_addr;
+};
+
+static int nop_verify_blob(struct pil_desc *pil, u32 phy_addr, size_t size)
+{
+ return 0;
+}
+
+static int pil_riva_init_image(struct pil_desc *pil, const u8 *metadata,
+ size_t size)
+{
+ const struct elf32_hdr *ehdr = (struct elf32_hdr *)metadata;
+ struct riva_data *drv = dev_get_drvdata(pil->dev);
+ drv->start_addr = ehdr->e_entry;
+ return 0;
+}
+
+static int pil_riva_reset(struct pil_desc *pil)
+{
+ u32 reg, sel;
+ bool xo;
+ struct riva_data *drv = dev_get_drvdata(pil->dev);
+ void __iomem *base = drv->base;
+ unsigned long start_addr = drv->start_addr;
+
+ /* Enable A2XB bridge */
+ reg = readl_relaxed(base + RIVA_PMU_A2XB_CFG);
+ reg |= RIVA_PMU_A2XB_CFG_EN;
+ writel_relaxed(reg, base + RIVA_PMU_A2XB_CFG);
+
+ /* Determine which XO to use */
+ reg = readl_relaxed(base + RIVA_PMU_CFG);
+ xo = (reg & RIVA_PMU_CFG_IRIS_XO_MODE) == RIVA_PMU_CFG_IRIS_XO_MODE_48;
+
+ /* Program PLL 13 to 960 MHz */
+ reg = readl_relaxed(RIVA_PLL_MODE);
+ reg &= ~(PLL_MODE_BYPASSNL | PLL_MODE_OUTCTRL | PLL_MODE_RESET_N);
+ writel_relaxed(reg, RIVA_PLL_MODE);
+
+ if (xo)
+ writel_relaxed(0x40000C00 | 40, RIVA_PLL_L_VAL);
+ else
+ writel_relaxed(0x40000C00 | 50, RIVA_PLL_L_VAL);
+ writel_relaxed(0, RIVA_PLL_M_VAL);
+ writel_relaxed(1, RIVA_PLL_N_VAL);
+ writel_relaxed(0x01495227, RIVA_PLL_CONFIG);
+
+ reg = readl_relaxed(RIVA_PLL_MODE);
+ reg &= ~(PLL_MODE_REF_XO_SEL);
+ reg |= xo ? PLL_MODE_REF_XO_SEL_RF : PLL_MODE_REF_XO_SEL_CXO;
+ writel_relaxed(reg, RIVA_PLL_MODE);
+
+ /* Enable PLL 13 */
+ reg |= PLL_MODE_BYPASSNL;
+ writel_relaxed(reg, RIVA_PLL_MODE);
+
+ /*
+ * H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe.
+ */
+ mb();
+ usleep_range(10, 20);
+
+ reg |= PLL_MODE_RESET_N;
+ writel_relaxed(reg, RIVA_PLL_MODE);
+ reg |= PLL_MODE_OUTCTRL;
+ writel_relaxed(reg, RIVA_PLL_MODE);
+
+ /* Wait for PLL to settle */
+ mb();
+ usleep_range(50, 100);
+
+ /* Configure cCPU for 240 MHz */
+ sel = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
+ reg = readl_relaxed(base + RIVA_PMU_CLK_ROOT3);
+ if (sel & RIVA_PMU_ROOT_CLK_SEL_3) {
+ reg &= ~(RIVA_PMU_CLK_ROOT3_SRC0_SEL |
+ RIVA_PMU_CLK_ROOT3_SRC0_DIV);
+ reg |= RIVA_PMU_CLK_ROOT3_SRC0_SEL_RIVA |
+ RIVA_PMU_CLK_ROOT3_SRC0_DIV_2;
+ } else {
+ reg &= ~(RIVA_PMU_CLK_ROOT3_SRC1_SEL |
+ RIVA_PMU_CLK_ROOT3_SRC1_DIV);
+ reg |= RIVA_PMU_CLK_ROOT3_SRC1_SEL_RIVA |
+ RIVA_PMU_CLK_ROOT3_SRC1_DIV_2;
+ }
+ writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
+ reg |= RIVA_PMU_CLK_ROOT3_ENA;
+ writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
+ reg = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
+ reg ^= RIVA_PMU_ROOT_CLK_SEL_3;
+ writel_relaxed(reg, base + RIVA_PMU_ROOT_CLK_SEL);
+
+ /* Use the high vector table */
+ reg = readl_relaxed(base + RIVA_PMU_CCPU_CTL);
+ reg |= RIVA_PMU_CCPU_CTL_HIGH_IVT | RIVA_PMU_CCPU_CTL_REMAP_EN;
+ writel_relaxed(reg, base + RIVA_PMU_CCPU_CTL);
+
+ /* Set base memory address */
+ writel_relaxed(start_addr >> 16, base + RIVA_PMU_CCPU_BOOT_REMAP_ADDR);
+
+ /* Clear warmboot bit indicating this is a cold boot */
+ reg = readl_relaxed(base + RIVA_PMU_CFG);
+ reg &= ~(RIVA_PMU_CFG_WARM_BOOT);
+ writel_relaxed(reg, base + RIVA_PMU_CFG);
+
+ /* Enable the cCPU clock */
+ reg = readl_relaxed(base + RIVA_PMU_OVRD_VAL);
+ reg |= RIVA_PMU_OVRD_VAL_CCPU_CLK;
+ writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
+
+ /* Take cCPU out of reset */
+ reg |= RIVA_PMU_OVRD_VAL_CCPU_RESET;
+ writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
+
+ return 0;
+}
+
+static int pil_riva_shutdown(struct pil_desc *pil)
+{
+ struct riva_data *drv = dev_get_drvdata(pil->dev);
+ u32 reg;
+
+ reg = readl_relaxed(drv->base + RIVA_PMU_OVRD_VAL);
+ reg &= ~(RIVA_PMU_OVRD_VAL_CCPU_RESET | RIVA_PMU_OVRD_VAL_CCPU_CLK);
+ writel_relaxed(reg, drv->base + RIVA_PMU_OVRD_VAL);
+
+ return 0;
+}
+
+static struct pil_reset_ops pil_riva_ops = {
+ .init_image = pil_riva_init_image,
+ .verify_blob = nop_verify_blob,
+ .auth_and_reset = pil_riva_reset,
+ .shutdown = pil_riva_shutdown,
+};
+
+static int pil_riva_init_image_trusted(struct pil_desc *pil,
+ const u8 *metadata, size_t size)
+{
+ return pas_init_image(PAS_RIVA, metadata, size);
+}
+
+static int pil_riva_reset_trusted(struct pil_desc *pil)
+{
+ return pas_auth_and_reset(PAS_RIVA);
+}
+
+static int pil_riva_shutdown_trusted(struct pil_desc *pil)
+{
+ return pas_shutdown(PAS_RIVA);
+}
+
+static struct pil_reset_ops pil_riva_ops_trusted = {
+ .init_image = pil_riva_init_image_trusted,
+ .verify_blob = nop_verify_blob,
+ .auth_and_reset = pil_riva_reset_trusted,
+ .shutdown = pil_riva_shutdown_trusted,
+};
+
+static int __devinit pil_riva_probe(struct platform_device *pdev)
+{
+ struct riva_data *drv;
+ struct resource *res;
+ struct pil_desc *desc;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
+
+ drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, drv);
+
+ drv->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!drv->base)
+ return -ENOMEM;
+
+ desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ desc->name = "wcnss";
+ desc->dev = &pdev->dev;
+
+ if (pas_supported(PAS_RIVA) > 0) {
+ desc->ops = &pil_riva_ops_trusted;
+ dev_info(&pdev->dev, "using secure boot\n");
+ } else {
+ desc->ops = &pil_riva_ops;
+ dev_info(&pdev->dev, "using non-secure boot\n");
+ }
+ return msm_pil_register(desc);
+}
+
+static int __devexit pil_riva_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver pil_riva_driver = {
+ .probe = pil_riva_probe,
+ .remove = __devexit_p(pil_riva_remove),
+ .driver = {
+ .name = "pil_riva",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pil_riva_init(void)
+{
+ return platform_driver_register(&pil_riva_driver);
+}
+module_init(pil_riva_init);
+
+static void __exit pil_riva_exit(void)
+{
+ platform_driver_unregister(&pil_riva_driver);
+}
+module_exit(pil_riva_exit);
+
+MODULE_DESCRIPTION("Support for booting RIVA (WCNSS) processors");
+MODULE_LICENSE("GPL v2");