Merge "msm: vidc: rename functions in hfi layer to hardware specific"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 53fd3b2..23181d9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1808,7 +1808,7 @@
config OABI_COMPAT
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
- default y
+ default y if !SMP
help
This option preserves the old syscall interface along with the
new (ARM EABI) one. It also provides a compatibility layer to
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index bba15a3..36bcdd7 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -85,6 +85,15 @@
compatible = "qcom,android-usb";
};
+ wcd9xxx_intc: wcd9xxx-irq {
+ compatible = "qcom,wcd9xxx-irq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <68 0>;
+ interrupt-names = "cdc-int";
+ };
+
slim@fe12f000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
@@ -93,6 +102,212 @@
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 163 0>, <0 164 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+
+ tapan_codec {
+ compatible = "qcom,tapan-slim-pgd";
+ elemental-addr = [00 01 E0 00 17 02];
+
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ 17 18 19 20 21 22 23 24 25 26 27 28>;
+ qcom,cdc-reset-gpio = <&msmgpio 72 0>;
+
+ cdc-vdd-buck-supply = <&pm8026_s4>;
+ qcom,cdc-vdd-buck-voltage = <2100000 2100000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-h-supply = <&pm8026_l6>;
+ qcom,cdc-vdd-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-h-current = <25000>;
+
+ cdc-vdd-px-supply = <&pm8026_l6>;
+ qcom,cdc-vdd-px-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-px-current = <25000>;
+
+ cdc-vdd-a-1p2v-supply = <&pm8026_l4>;
+ qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
+ qcom,cdc-vdd-a-1p2v-current = <10000>;
+
+ cdc-vdd-cx-supply = <&pm8026_l4>;
+ qcom,cdc-vdd-cx-voltage = <1200000 1200000>;
+ qcom,cdc-vdd-cx-current = <10000>;
+
+ qcom,cdc-micbias-ldoh-v = <0x3>;
+ qcom,cdc-micbias-cfilt1-mv = <1800>;
+ qcom,cdc-micbias-cfilt2-mv = <1800>;
+ qcom,cdc-micbias-cfilt3-mv = <1800>;
+
+ qcom,cdc-micbias1-cfilt-sel = <0x0>;
+ qcom,cdc-micbias2-cfilt-sel = <0x1>;
+ qcom,cdc-micbias3-cfilt-sel = <0x2>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+ qcom,cdc-slim-ifd = "tapan-slim-ifd";
+ qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02];
+ };
+ };
+
+ qcom,msm-adsp-loader {
+ compatible = "qcom,adsp-loader";
+ qcom,adsp-state = <0>;
+ };
+
+ sound {
+ compatible = "qcom,msm8226-audio-tapan";
+ qcom,model = "msm8226-tapan-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "AMIC1", "MIC BIAS1 Internal1",
+ "MIC BIAS1 Internal1", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2 External",
+ "MIC BIAS2 External", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+ qcom,tapan-mclk-clk-freq = <9600000>;
+ };
+
+ qcom,msm-pcm {
+ compatible = "qcom,msm-pcm-dsp";
+ };
+
+ qcom,msm-pcm-routing {
+ compatible = "qcom,msm-pcm-routing";
+ };
+
+ qcom,msm-pcm-lpa {
+ compatible = "qcom,msm-pcm-lpa";
+ };
+
+ qcom,msm-compr-dsp {
+ compatible = "qcom,msm-compr-dsp";
+ };
+
+ qcom,msm-voip-dsp {
+ compatible = "qcom,msm-voip-dsp";
+ };
+
+ qcom,msm-pcm-voice {
+ compatible = "qcom,msm-pcm-voice";
+ };
+
+ qcom,msm-stub-codec {
+ compatible = "qcom,msm-stub-codec";
+ };
+
+ qcom,msm-dai-fe {
+ compatible = "qcom,msm-dai-fe";
+ };
+
+ qcom,msm-pcm-afe {
+ compatible = "qcom,msm-pcm-afe";
+ };
+
+ qcom,msm-dai-q6-hdmi {
+ compatible = "qcom,msm-dai-q6-hdmi";
+ qcom,msm-dai-q6-dev-id = <8>;
+ };
+
+ qcom,msm-dai-q6 {
+ compatible = "qcom,msm-dai-q6";
+ qcom,msm-dai-q6-sb-0-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16384>;
+ };
+
+ qcom,msm-dai-q6-sb-0-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16385>;
+ };
+
+ qcom,msm-dai-q6-sb-1-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16386>;
+ };
+
+ qcom,msm-dai-q6-sb-1-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16387>;
+ };
+
+ qcom,msm-dai-q6-sb-3-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16390>;
+ };
+
+ qcom,msm-dai-q6-sb-3-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16391>;
+ };
+
+ qcom,msm-dai-q6-sb-4-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16392>;
+ };
+
+ qcom,msm-dai-q6-sb-4-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16393>;
+ };
+
+ qcom,msm-dai-q6-bt-sco-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12288>;
+ };
+
+ qcom,msm-dai-q6-bt-sco-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12289>;
+ };
+
+ qcom,msm-dai-q6-int-fm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12292>;
+ };
+
+ qcom,msm-dai-q6-int-fm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12293>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <224>;
+ };
+
+ qcom,msm-dai-q6-be-afe-pcm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <225>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <241>;
+ };
+
+ qcom,msm-dai-q6-afe-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <240>;
+ };
+ };
+
+ qcom,msm-pcm-hostless {
+ compatible = "qcom,msm-pcm-hostless";
};
qcom,wdt@f9017000 {
diff --git a/arch/arm/configs/msm8910_defconfig b/arch/arm/configs/msm8910_defconfig
index bf163e0..4b1e3f2 100644
--- a/arch/arm/configs/msm8910_defconfig
+++ b/arch/arm/configs/msm8910_defconfig
@@ -36,6 +36,7 @@
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8910=y
CONFIG_ARCH_MSM8226=y
+CONFIG_SND_SOC_MSM8226=y
# CONFIG_MSM_STACKED_MEMORY is not set
CONFIG_CPU_HAS_L2_PMU=y
# CONFIG_MSM_FIQ_SUPPORT is not set
@@ -45,6 +46,7 @@
# CONFIG_MSM_HW3D is not set
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
CONFIG_MSM_WATCHDOG_V2=y
+CONFIG_MSM_ADSP_LOADER=m
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
@@ -104,8 +106,12 @@
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_MSM_QPNP_INT=y
+CONFIG_SLIMBUS=y
+CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
+CONFIG_I2C=y
+CONFIG_WCD9306_CODEC=y
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_STUB=y
@@ -130,7 +136,6 @@
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_TEST=m
CONFIG_MMC_MSM=y
-CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
@@ -138,9 +143,10 @@
CONFIG_ANDROID_RAM_CONSOLE=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_MSM_IOMMU=y
CONFIG_SPS=y
CONFIG_SPS_SUPPORT_NDP_BAM=y
-CONFIG_MSM_IOMMU=y
+CONFIG_MMC_MSM_SPS_SUPPORT=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a32de20..989d80e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -403,6 +403,9 @@
select MSM_GPIOMUX
select MSM_NATIVE_RESTART
select MSM_RESTART_V2
+ select MSM_QDSP6_APRV2
+ select MSM_QDSP6V2_CODECS
+ select MSM_AUDIO_QDSP6V2 if SND_SOC
endmenu
choice
diff --git a/arch/arm/mach-msm/board-8064-display.c b/arch/arm/mach-msm/board-8064-display.c
index b717973..b0dc20b 100644
--- a/arch/arm/mach-msm/board-8064-display.c
+++ b/arch/arm/mach-msm/board-8064-display.c
@@ -818,12 +818,13 @@
return 0;
/* TBD: PM8921 regulator instead of 8901 */
- if (!reg_ext_3p3v) {
+ if (!reg_ext_3p3v &&
+ (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()))) {
reg_ext_3p3v = regulator_get(&hdmi_msm_device.dev,
- "hdmi_mux_vdd");
+ "hdmi_mux_vdd");
if (IS_ERR_OR_NULL(reg_ext_3p3v)) {
pr_err("could not get reg_ext_3p3v, rc = %ld\n",
- PTR_ERR(reg_ext_3p3v));
+ PTR_ERR(reg_ext_3p3v));
reg_ext_3p3v = NULL;
return -ENODEV;
}
@@ -831,7 +832,7 @@
if (!reg_8921_lvs7) {
reg_8921_lvs7 = regulator_get(&hdmi_msm_device.dev,
- "hdmi_vdda");
+ "hdmi_vdda");
if (IS_ERR(reg_8921_lvs7)) {
pr_err("could not get reg_8921_lvs7, rc = %ld\n",
PTR_ERR(reg_8921_lvs7));
@@ -841,7 +842,7 @@
}
if (!reg_8921_s4) {
reg_8921_s4 = regulator_get(&hdmi_msm_device.dev,
- "hdmi_lvl_tsl");
+ "hdmi_lvl_tsl");
if (IS_ERR(reg_8921_s4)) {
pr_err("could not get reg_8921_s4, rc = %ld\n",
PTR_ERR(reg_8921_s4));
@@ -860,17 +861,22 @@
* Configure 3P3V_BOOST_EN as GPIO, 8mA drive strength,
* pull none, out-high
*/
- rc = regulator_set_optimum_mode(reg_ext_3p3v, 290000);
- if (rc < 0) {
- pr_err("set_optimum_mode ext_3p3v failed, rc=%d\n", rc);
- return -EINVAL;
+ if (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv())) {
+ rc = regulator_set_optimum_mode(reg_ext_3p3v, 290000);
+ if (rc < 0) {
+ pr_err("set_optimum_mode ext_3p3v failed," \
+ "rc=%d\n", rc);
+ return -EINVAL;
+ }
+
+ rc = regulator_enable(reg_ext_3p3v);
+ if (rc) {
+ pr_err("enable reg_ext_3p3v failed, rc=%d\n",
+ rc);
+ return rc;
+ }
}
- rc = regulator_enable(reg_ext_3p3v);
- if (rc) {
- pr_err("enable reg_ext_3p3v failed, rc=%d\n", rc);
- return rc;
- }
rc = regulator_enable(reg_8921_lvs7);
if (rc) {
pr_err("'%s' regulator enable failed, rc=%d\n",
@@ -885,11 +891,15 @@
}
pr_debug("%s(on): success\n", __func__);
} else {
- rc = regulator_disable(reg_ext_3p3v);
- if (rc) {
- pr_err("disable reg_ext_3p3v failed, rc=%d\n", rc);
- return -ENODEV;
+ if (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv())) {
+ rc = regulator_disable(reg_ext_3p3v);
+ if (rc) {
+ pr_err("disable reg_ext_3p3v failed, rc=%d\n",
+ rc);
+ return -ENODEV;
+ }
}
+
rc = regulator_disable(reg_8921_lvs7);
if (rc) {
pr_err("disable reg_8921_l23 failed, rc=%d\n", rc);
@@ -910,7 +920,8 @@
error2:
regulator_disable(reg_8921_lvs7);
error1:
- regulator_disable(reg_ext_3p3v);
+ if (!(machine_is_mpq8064_hrd() || machine_is_mpq8064_dtv()))
+ regulator_disable(reg_ext_3p3v);
return rc;
}
diff --git a/arch/arm/mach-msm/board-8226-gpiomux.c b/arch/arm/mach-msm/board-8226-gpiomux.c
index 2b5399f..7a53b24 100644
--- a/arch/arm/mach-msm/board-8226-gpiomux.c
+++ b/arch/arm/mach-msm/board-8226-gpiomux.c
@@ -17,6 +17,57 @@
#include <mach/gpio.h>
#include <mach/gpiomux.h>
+#define KS8851_IRQ_GPIO 75
+
+#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
+static struct gpiomux_setting gpio_eth_config = {
+ .pull = GPIOMUX_PULL_UP,
+ .drv = GPIOMUX_DRV_2MA,
+ .func = GPIOMUX_FUNC_GPIO,
+};
+static struct gpiomux_setting gpio_spi_config = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_8MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+static struct msm_gpiomux_config msm_eth_configs[] = {
+ {
+ .gpio = KS8851_IRQ_GPIO,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_eth_config,
+ }
+ },
+};
+
+static struct msm_gpiomux_config msm_blsp_configs[] __initdata = {
+ {
+ .gpio = 0, /* BLSP1 QUP2 SPI_DATA_MOSI */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 1, /* BLSP1 QUP2 SPI_DATA_MISO */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 2, /* BLSP1 QUP2 SPI_CS_N */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+ {
+ .gpio = 3, /* BLSP1 QUP2 SPI_CLK */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_spi_config,
+ },
+ },
+};
+#endif
+
void __init msm8226_init_gpiomux(void)
{
int rc;
@@ -26,4 +77,8 @@
pr_err("%s failed %d\n", __func__, rc);
return;
}
+#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
+ msm_gpiomux_install(msm_eth_configs, ARRAY_SIZE(msm_eth_configs));
+ msm_gpiomux_install(msm_blsp_configs, ARRAY_SIZE(msm_blsp_configs));
+#endif
}
diff --git a/arch/arm/mach-msm/board-8226.c b/arch/arm/mach-msm/board-8226.c
index a5cb481..2f2eb2c 100644
--- a/arch/arm/mach-msm/board-8226.c
+++ b/arch/arm/mach-msm/board-8226.c
@@ -73,6 +73,8 @@
CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
+ CLK_DUMMY("core_clk", NULL, "f9928000.spi", OFF),
+ CLK_DUMMY("iface_clk", NULL, "f9928000.spi", OFF),
};
static struct clock_init_data msm_dummy_clock_init_data __initdata = {
diff --git a/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h b/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
index 88cb94a..b830134 100644
--- a/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
+++ b/arch/arm/mach-msm/include/mach/qdsp6v2/audio_acdb.h
@@ -14,7 +14,9 @@
#define _AUDIO_ACDB_H
#include <linux/msm_audio_acdb.h>
-#if defined CONFIG_ARCH_MSM8974 || defined CONFIG_ARCH_MSM9625
+#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM9625) \
+ || defined(CONFIG_ARCH_MSM8226)
+
#include <sound/q6adm-v2.h>
#else
#include <sound/q6adm.h>
diff --git a/arch/arm/mach-msm/qdsp6v2/q6audio_common.h b/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
index 3bc8454..5ffffd2 100644
--- a/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
+++ b/arch/arm/mach-msm/qdsp6v2/q6audio_common.h
@@ -15,7 +15,9 @@
#ifndef __Q6_AUDIO_COMMON_H__
#define __Q6_AUDIO_COMMON_H__
-#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM9625)
+#if defined(CONFIG_ARCH_MSM8974) || defined(CONFIG_ARCH_MSM9625) \
+ || defined(CONFIG_ARCH_MSM8226)
+
#include <sound/apr_audio-v2.h>
#include <sound/q6asm-v2.h>
#else
diff --git a/drivers/bluetooth/hci_smd.c b/drivers/bluetooth/hci_smd.c
index 6030520..9b60bda 100644
--- a/drivers/bluetooth/hci_smd.c
+++ b/drivers/bluetooth/hci_smd.c
@@ -44,6 +44,19 @@
#define RX_Q_MONITOR (500) /* 500 milli second */
#define HCI_REGISTER_SET 0
+/* SSR state machine to take care of back to back SSR requests
+ * and handling the incomming BT on/off,Airplane mode toggling and
+ * also spuriour SMD open notification while one SSr is in progress
+ */
+#define STATE_SSR_ON 0x1
+#define STATE_SSR_START 0x02
+#define STATE_SSR_CHANNEL_OPEN_PENDING 0x04
+#define STATE_SSR_PENDING_INIT 0x08
+#define STATE_SSR_COMPLETE 0x00
+#define STATE_SSR_OFF STATE_SSR_COMPLETE
+
+static int ssr_state = STATE_SSR_OFF;
+
static int hcismd_set;
static DEFINE_SEMAPHORE(hci_smd_enable);
@@ -341,25 +354,47 @@
break;
case SMD_EVENT_OPEN:
BT_INFO("opening HCI-SMD channel :%s", EVENT_CHANNEL);
- hci_smd_open(hdev);
- open_worker = kzalloc(sizeof(*open_worker), GFP_ATOMIC);
- if (!open_worker) {
- BT_ERR("Out of memory");
- break;
+ BT_DBG("SSR state is : %x", ssr_state);
+ if ((ssr_state == STATE_SSR_OFF) ||
+ (ssr_state == STATE_SSR_CHANNEL_OPEN_PENDING)) {
+
+ hci_smd_open(hdev);
+ open_worker = kzalloc(sizeof(*open_worker), GFP_ATOMIC);
+ if (!open_worker) {
+ BT_ERR("Out of memory");
+ break;
+ }
+ if (ssr_state == STATE_SSR_CHANNEL_OPEN_PENDING) {
+ ssr_state = STATE_SSR_PENDING_INIT;
+ BT_INFO("SSR state is : %x", ssr_state);
+ }
+ INIT_WORK(open_worker, hci_dev_smd_open);
+ schedule_work(open_worker);
+
}
- INIT_WORK(open_worker, hci_dev_smd_open);
- schedule_work(open_worker);
break;
case SMD_EVENT_CLOSE:
BT_INFO("Closing HCI-SMD channel :%s", EVENT_CHANNEL);
- hci_smd_close(hdev);
- reset_worker = kzalloc(sizeof(*reset_worker), GFP_ATOMIC);
- if (!reset_worker) {
- BT_ERR("Out of memory");
- break;
+ BT_DBG("SSR state is : %x", ssr_state);
+ if ((ssr_state == STATE_SSR_OFF) ||
+ (ssr_state == (STATE_SSR_PENDING_INIT))) {
+
+ hci_smd_close(hdev);
+ reset_worker = kzalloc(sizeof(*reset_worker),
+ GFP_ATOMIC);
+ if (!reset_worker) {
+ BT_ERR("Out of memory");
+ break;
+ }
+ ssr_state = STATE_SSR_ON;
+ BT_INFO("SSR state is : %x", ssr_state);
+ INIT_WORK(reset_worker, hci_dev_restart);
+ schedule_work(reset_worker);
+
+ } else if (ssr_state & STATE_SSR_ON) {
+ BT_ERR("SSR state is : %x", ssr_state);
}
- INIT_WORK(reset_worker, hci_dev_restart);
- schedule_work(reset_worker);
+
break;
default:
break;
@@ -403,19 +438,37 @@
{
struct hci_dev *hdev;
- hdev = hsmd->hdev;
- if (test_and_set_bit(HCI_REGISTER_SET, &hsmd->flags)) {
- BT_ERR("HCI device registered already");
+ if (hsmd->hdev)
+ hdev = hsmd->hdev;
+ else {
+ BT_ERR("hdev is NULL");
return 0;
- } else
- BT_INFO("HCI device registration is starting");
- if (hci_register_dev(hdev) < 0) {
- BT_ERR("Can't register HCI device");
- hci_free_dev(hdev);
- hsmd->hdev = NULL;
- clear_bit(HCI_REGISTER_SET, &hsmd->flags);
- return -ENODEV;
}
+ /* Allow the incomming SSR even the prev one at PENDING INIT STATE
+ * since clenup need to be started again from the beging and ignore
+ * or bypass the prev one
+ */
+ if ((ssr_state == STATE_SSR_OFF) ||
+ (ssr_state == STATE_SSR_PENDING_INIT)) {
+
+ if (test_and_set_bit(HCI_REGISTER_SET, &hsmd->flags)) {
+ BT_ERR("HCI device registered already");
+ return 0;
+ } else
+ BT_INFO("HCI device registration is starting");
+ if (hci_register_dev(hdev) < 0) {
+ BT_ERR("Can't register HCI device");
+ hci_free_dev(hdev);
+ hsmd->hdev = NULL;
+ clear_bit(HCI_REGISTER_SET, &hsmd->flags);
+ return -ENODEV;
+ }
+ if (ssr_state == STATE_SSR_PENDING_INIT) {
+ ssr_state = STATE_SSR_COMPLETE;
+ BT_INFO("SSR state is : %x", ssr_state);
+ }
+ } else if (ssr_state)
+ BT_ERR("Registration called in invalid context");
return 0;
}
@@ -449,7 +502,10 @@
*/
setup_timer(&hsmd->rx_q_timer, schedule_timer,
(unsigned long) hsmd->hdev);
-
+ if (ssr_state == STATE_SSR_START) {
+ ssr_state = STATE_SSR_CHANNEL_OPEN_PENDING;
+ BT_INFO("SSR state is : %x", ssr_state);
+ }
/* Open the SMD Channel and device and register the callback function */
rc = smd_named_open_on_edge(EVENT_CHANNEL, SMD_APPS_WCNSS,
&hsmd->event_channel, hdev, hci_smd_notify_event);
@@ -478,21 +534,25 @@
static void hci_smd_deregister_dev(struct hci_smd_data *hsmd)
{
tasklet_kill(&hs.rx_task);
-
+ if (ssr_state)
+ BT_DBG("SSR state is : %x", ssr_state);
+ /* Though the hci_smd driver is not registered with the hci
+ * need to close the opened channels as a part of cleaup
+ */
if (!test_and_clear_bit(HCI_REGISTER_SET, &hsmd->flags)) {
BT_ERR("HCI device un-registered already");
- return;
- } else
+ } else {
BT_INFO("HCI device un-registration going on");
- if (hsmd->hdev) {
- if (hci_unregister_dev(hsmd->hdev) < 0)
- BT_ERR("Can't unregister HCI device %s",
- hsmd->hdev->name);
- hci_free_dev(hsmd->hdev);
- hsmd->hdev = NULL;
+ if (hsmd->hdev) {
+ if (hci_unregister_dev(hsmd->hdev) < 0)
+ BT_ERR("Can't unregister HCI device %s",
+ hsmd->hdev->name);
+
+ hci_free_dev(hsmd->hdev);
+ hsmd->hdev = NULL;
+ }
}
-
smd_close(hs.event_channel);
smd_close(hs.data_channel);
@@ -513,23 +573,47 @@
{
down(&hci_smd_enable);
restart_in_progress = 1;
+ BT_DBG("SSR state is : %x", ssr_state);
+
+ if (ssr_state == STATE_SSR_ON) {
+ ssr_state = STATE_SSR_START;
+ BT_INFO("SSR state is : %x", ssr_state);
+ } else {
+ BT_ERR("restart triggered in wrong context");
+ up(&hci_smd_enable);
+ kfree(worker);
+ return;
+ }
hci_smd_deregister_dev(&hs);
hci_smd_register_smd(&hs);
up(&hci_smd_enable);
kfree(worker);
+
}
static void hci_dev_smd_open(struct work_struct *worker)
{
down(&hci_smd_enable);
+ if (ssr_state)
+ BT_DBG("SSR state is : %x", ssr_state);
+
+ if ((ssr_state != STATE_SSR_OFF) &&
+ (ssr_state != (STATE_SSR_PENDING_INIT))) {
+ up(&hci_smd_enable);
+ kfree(worker);
+ return;
+ }
+
if (restart_in_progress == 1) {
/* Allow wcnss to initialize */
restart_in_progress = 0;
msleep(10000);
}
+
hci_smd_hci_register_dev(&hs);
up(&hci_smd_enable);
kfree(worker);
+
}
static int hcismd_set_enable(const char *val, struct kernel_param *kp)
@@ -545,14 +629,23 @@
if (ret)
goto done;
+ /* Ignore the all incomming register de-register requests in case of
+ * SSR is in-progress
+ */
switch (hcismd_set) {
case 1:
- if (hs.hdev == NULL)
+ if ((hs.hdev == NULL) && (ssr_state == STATE_SSR_OFF))
hci_smd_register_smd(&hs);
+ else if (ssr_state)
+ BT_ERR("SSR is in progress,state is : %x", ssr_state);
+
break;
case 0:
- hci_smd_deregister_dev(&hs);
+ if (ssr_state == STATE_SSR_OFF)
+ hci_smd_deregister_dev(&hs);
+ else if (ssr_state)
+ BT_ERR("SSR is in progress,state is : %x", ssr_state);
break;
default:
ret = -EFAULT;
@@ -569,6 +662,7 @@
wake_lock_init(&hs.wake_lock_tx, WAKE_LOCK_SUSPEND,
"msm_smd_Tx");
restart_in_progress = 0;
+ ssr_state = STATE_SSR_OFF;
hs.hdev = NULL;
return 0;
}
diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c
index 2a85a00..e8567db 100644
--- a/drivers/char/diag/diag_masks.c
+++ b/drivers/char/diag/diag_masks.c
@@ -26,6 +26,9 @@
#define ALL_SSID -1
#define MAX_SSID_PER_RANGE 100
+#define FEATURE_MASK_LEN_BYTES 1
+#define APPS_RESPOND_LOG_ON_DEMAND 0x04
+
struct mask_info {
int equip_id;
int num_items;
@@ -309,6 +312,7 @@
smd_info->peripheral);
diag_send_log_mask_update(smd_info->ch, ALL_EQUIP_ID);
diag_send_event_mask_update(smd_info->ch, diag_event_num_bytes);
+ diag_send_feature_mask_update(smd_info->ch, smd_info->peripheral);
smd_info->notify_context = 0;
}
@@ -461,6 +465,42 @@
mutex_unlock(&driver->diag_cntl_mutex);
}
+void diag_send_feature_mask_update(smd_channel_t *ch, int proc)
+{
+ void *buf = driver->buf_feature_mask_update;
+ int header_size = sizeof(struct diag_ctrl_feature_mask);
+ int wr_size = -ENOMEM, retry_count = 0, timer;
+ uint8_t feature_byte = 0;
+
+ mutex_lock(&driver->diag_cntl_mutex);
+ /* send feature mask update */
+ driver->feature_mask->ctrl_pkt_id = DIAG_CTRL_MSG_FEATURE;
+ driver->feature_mask->ctrl_pkt_data_len = 4 + FEATURE_MASK_LEN_BYTES;
+ driver->feature_mask->feature_mask_len = FEATURE_MASK_LEN_BYTES;
+ memcpy(buf, driver->feature_mask, header_size);
+ feature_byte |= APPS_RESPOND_LOG_ON_DEMAND;
+ memcpy(buf+header_size, &feature_byte, FEATURE_MASK_LEN_BYTES);
+
+ if (ch) {
+ while (retry_count < 3) {
+ wr_size = smd_write(ch, buf, header_size +
+ FEATURE_MASK_LEN_BYTES);
+ if (wr_size == -ENOMEM) {
+ retry_count++;
+ for (timer = 0; timer < 5; timer++)
+ udelay(2000);
+ } else
+ break;
+ }
+ if (wr_size != header_size + FEATURE_MASK_LEN_BYTES)
+ pr_err("diag: proc %d fail feature update %d, tried %d",
+ proc, wr_size, header_size + FEATURE_MASK_LEN_BYTES);
+ } else
+ pr_err("diag: ch invalid, feature update on proc %d\n", proc);
+ mutex_unlock(&driver->diag_cntl_mutex);
+
+}
+
int diag_process_apps_masks(unsigned char *buf, int len)
{
int packet_type = 1;
@@ -671,6 +711,16 @@
return 0;
}
#endif
+ } else if (*buf == 0x78) {
+ if (!(driver->smd_cntl[MODEM_DATA].ch) ||
+ (driver->log_on_demand_support)) {
+ driver->apps_rsp_buf[0] = 0x78;
+ /* Copy log code received */
+ *(uint16_t *)(driver->apps_rsp_buf+1) =
+ *(uint16_t *)buf;
+ driver->apps_rsp_buf[3] = 0x1;/* Unknown */
+ encode_rsp_and_send(3);
+ }
}
return packet_type;
@@ -727,6 +777,21 @@
goto err;
kmemleak_not_leak(driver->msg_masks);
}
+ if (driver->buf_feature_mask_update == NULL) {
+ driver->buf_feature_mask_update = kzalloc(sizeof(
+ struct diag_ctrl_feature_mask) +
+ FEATURE_MASK_LEN_BYTES, GFP_KERNEL);
+ if (driver->buf_feature_mask_update == NULL)
+ goto err;
+ kmemleak_not_leak(driver->buf_feature_mask_update);
+ }
+ if (driver->feature_mask == NULL) {
+ driver->feature_mask = kzalloc(sizeof(
+ struct diag_ctrl_feature_mask), GFP_KERNEL);
+ if (driver->feature_mask == NULL)
+ goto err;
+ kmemleak_not_leak(driver->feature_mask);
+ }
diag_create_msg_mask_table();
diag_event_num_bytes = 0;
if (driver->log_masks == NULL) {
@@ -751,6 +816,8 @@
kfree(driver->msg_masks);
kfree(driver->log_masks);
kfree(driver->event_masks);
+ kfree(driver->feature_mask);
+ kfree(driver->buf_feature_mask_update);
}
void diag_masks_exit(void)
@@ -761,4 +828,6 @@
kfree(driver->msg_masks);
kfree(driver->log_masks);
kfree(driver->event_masks);
+ kfree(driver->feature_mask);
+ kfree(driver->buf_feature_mask_update);
}
diff --git a/drivers/char/diag/diag_masks.h b/drivers/char/diag/diag_masks.h
index f144774..53f72e8 100644
--- a/drivers/char/diag/diag_masks.h
+++ b/drivers/char/diag/diag_masks.h
@@ -21,6 +21,7 @@
int ssid_last, int proc);
void diag_send_log_mask_update(smd_channel_t *, int);
void diag_mask_update_fn(struct work_struct *work);
+void diag_send_feature_mask_update(smd_channel_t *ch, int proc);
int diag_process_apps_masks(unsigned char *buf, int len);
void diag_masks_init(void);
void diag_masks_exit(void);
diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h
index 8c46a5d..0b395c5 100644
--- a/drivers/char/diag/diagchar.h
+++ b/drivers/char/diag/diagchar.h
@@ -231,6 +231,7 @@
struct diag_ctrl_event_mask *event_mask;
struct diag_ctrl_log_mask *log_mask;
struct diag_ctrl_msg_mask *msg_mask;
+ struct diag_ctrl_feature_mask *feature_mask;
/* State for diag forwarding */
struct diag_smd_info smd_data[NUM_SMD_DATA_CHANNELS];
struct diag_smd_info smd_cntl[NUM_SMD_CONTROL_CHANNELS];
@@ -242,6 +243,7 @@
unsigned char *buf_msg_mask_update;
unsigned char *buf_log_mask_update;
unsigned char *buf_event_mask_update;
+ unsigned char *buf_feature_mask_update;
int read_len_legacy;
unsigned char *hdlc_buf;
unsigned hdlc_count;
@@ -259,6 +261,7 @@
uint8_t *log_masks;
int log_masks_length;
uint8_t *event_masks;
+ uint8_t log_on_demand_support;
struct diag_master_table *table;
uint8_t *pkt_buf;
int pkt_length;
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index a900d97..acac2fb 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -44,6 +44,7 @@
int total_recd)
{
int data_len = 0, type = -1, count_bytes = 0, j, flag = 0;
+ int feature_mask_len;
struct bindpkt_params_per_process *pkt_params =
kzalloc(sizeof(struct bindpkt_params_per_process), GFP_KERNEL);
struct diag_ctrl_msg *msg;
@@ -115,6 +116,11 @@
pr_err("diag: drop reg proc %d\n",
smd_info->peripheral);
kfree(temp);
+ } else if ((type == DIAG_CTRL_MSG_FEATURE) &&
+ (smd_info->peripheral == MODEM_DATA)) {
+ feature_mask_len = *(int *)(buf + 8);
+ driver->log_on_demand_support = (*(uint8_t *)
+ (buf + 12)) & 0x04;
} else if (type != DIAG_CTRL_MSG_REG) {
flag = 1;
}
@@ -209,6 +215,7 @@
reg_dirty = 0;
driver->polling_reg_flag = 0;
+ driver->log_on_demand_support = 1;
driver->diag_cntl_wq = create_singlethread_workqueue("diag_cntl_wq");
success = diag_smd_constructor(&driver->smd_cntl[MODEM_DATA],
diff --git a/drivers/char/diag/diagfwd_cntl.h b/drivers/char/diag/diagfwd_cntl.h
index aeb4ba1..8d262c4 100644
--- a/drivers/char/diag/diagfwd_cntl.h
+++ b/drivers/char/diag/diagfwd_cntl.h
@@ -77,6 +77,13 @@
/* Copy msg mask here */
} __packed;
+struct diag_ctrl_feature_mask {
+ uint32_t ctrl_pkt_id;
+ uint32_t ctrl_pkt_data_len;
+ uint32_t feature_mask_len;
+ /* Copy feature mask here */
+} __packed;
+
void diagfwd_cntl_init(void);
void diagfwd_cntl_exit(void);
void diag_read_smd_cntl_work_fn(struct work_struct *);
diff --git a/drivers/hwmon/qpnp-adc-common.c b/drivers/hwmon/qpnp-adc-common.c
index 440dc42..bde18d4 100644
--- a/drivers/hwmon/qpnp-adc-common.c
+++ b/drivers/hwmon/qpnp-adc-common.c
@@ -130,175 +130,6 @@
{790, 203}
};
-static const struct qpnp_vadc_map_pt adcmap_ntcg_104ef_104fb[] = {
- {696483, -40960},
- {649148, -39936},
- {605368, -38912},
- {564809, -37888},
- {527215, -36864},
- {492322, -35840},
- {460007, -34816},
- {429982, -33792},
- {402099, -32768},
- {376192, -31744},
- {352075, -30720},
- {329714, -29696},
- {308876, -28672},
- {289480, -27648},
- {271417, -26624},
- {254574, -25600},
- {238903, -24576},
- {224276, -23552},
- {210631, -22528},
- {197896, -21504},
- {186007, -20480},
- {174899, -19456},
- {164521, -18432},
- {154818, -17408},
- {145744, -16384},
- {137265, -15360},
- {129307, -14336},
- {121866, -13312},
- {114896, -12288},
- {108365, -11264},
- {102252, -10240},
- {96499, -9216},
- {91111, -8192},
- {86055, -7168},
- {81308, -6144},
- {76857, -5120},
- {72660, -4096},
- {68722, -3072},
- {65020, -2048},
- {61538, -1024},
- {58261, 0},
- {55177, 1024},
- {52274, 2048},
- {49538, 3072},
- {46962, 4096},
- {44531, 5120},
- {42243, 6144},
- {40083, 7168},
- {38045, 8192},
- {36122, 9216},
- {34308, 10240},
- {32592, 11264},
- {30972, 12288},
- {29442, 13312},
- {27995, 14336},
- {26624, 15360},
- {25333, 16384},
- {24109, 17408},
- {22951, 18432},
- {21854, 19456},
- {20807, 20480},
- {19831, 21504},
- {18899, 22528},
- {18016, 23552},
- {17178, 24576},
- {16384, 25600},
- {15631, 26624},
- {14916, 27648},
- {14237, 28672},
- {13593, 29696},
- {12976, 30720},
- {12400, 31744},
- {11848, 32768},
- {11324, 33792},
- {10825, 34816},
- {10354, 35840},
- {9900, 36864},
- {9471, 37888},
- {9062, 38912},
- {8674, 39936},
- {8306, 40960},
- {7951, 41984},
- {7616, 43008},
- {7296, 44032},
- {6991, 45056},
- {6701, 46080},
- {6424, 47104},
- {6160, 48128},
- {5908, 49152},
- {5667, 50176},
- {5439, 51200},
- {5219, 52224},
- {5010, 53248},
- {4810, 54272},
- {4619, 55296},
- {4440, 56320},
- {4263, 57344},
- {4097, 58368},
- {3938, 59392},
- {3785, 60416},
- {3637, 61440},
- {3501, 62464},
- {3368, 63488},
- {3240, 64512},
- {3118, 65536},
- {2998, 66560},
- {2889, 67584},
- {2782, 68608},
- {2680, 69632},
- {2581, 70656},
- {2490, 71680},
- {2397, 72704},
- {2310, 73728},
- {2227, 74752},
- {2147, 75776},
- {2064, 76800},
- {1998, 77824},
- {1927, 78848},
- {1860, 79872},
- {1795, 80896},
- {1736, 81920},
- {1673, 82944},
- {1615, 83968},
- {1560, 84992},
- {1507, 86016},
- {1456, 87040},
- {1407, 88064},
- {1360, 89088},
- {1314, 90112},
- {1271, 91136},
- {1228, 92160},
- {1189, 93184},
- {1150, 94208},
- {1112, 95232},
- {1076, 96256},
- {1042, 97280},
- {1008, 98304},
- {976, 99328},
- {945, 100352},
- {915, 101376},
- {886, 102400},
- {859, 103424},
- {832, 104448},
- {807, 105472},
- {782, 106496},
- {756, 107520},
- {735, 108544},
- {712, 109568},
- {691, 110592},
- {670, 111616},
- {650, 112640},
- {631, 113664},
- {612, 114688},
- {594, 115712},
- {577, 116736},
- {560, 117760},
- {544, 118784},
- {528, 119808},
- {513, 120832},
- {498, 121856},
- {483, 122880},
- {470, 123904},
- {457, 124928},
- {444, 125952},
- {431, 126976},
- {419, 128000}
-};
-
/* Voltage to temperature */
static const struct qpnp_vadc_map_pt adcmap_100k_104ef_104fb[] = {
{1758, -40},
@@ -553,9 +384,9 @@
xo_thm = qpnp_adc_scale_ratiometric_calib(adc_code,
adc_properties, chan_properties);
- xo_thm <<= 4;
- qpnp_adc_map_voltage_temp(adcmap_ntcg_104ef_104fb,
- ARRAY_SIZE(adcmap_ntcg_104ef_104fb),
+
+ qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb,
+ ARRAY_SIZE(adcmap_100k_104ef_104fb),
xo_thm, &adc_chan_result->physical);
return 0;
diff --git a/drivers/hwmon/qpnp-adc-current.c b/drivers/hwmon/qpnp-adc-current.c
index 0290335..c28c61d 100644
--- a/drivers/hwmon/qpnp-adc-current.c
+++ b/drivers/hwmon/qpnp-adc-current.c
@@ -789,7 +789,7 @@
return 0;
fail:
- adc_qpnp = NULL;
+ qpnp_iadc = NULL;
return rc;
}
diff --git a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
index 1587068..aff1046 100644
--- a/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
+++ b/drivers/media/dvb/mpq/demux/mpq_dmx_plugin_common.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -39,10 +39,14 @@
static int mpq_demux_device_num = CONFIG_DVB_MPQ_NUM_DMX_DEVICES;
module_param(mpq_demux_device_num, int, S_IRUGO);
-/* ION heap ID to be used when calling ion_alloc for video decoder buffer */
-static int video_ion_alloc_heap = ION_CP_MM_HEAP_ID;
-module_param(video_ion_alloc_heap, int, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(video_ion_alloc_heap, "ION heap ID for allocation");
+/* ION heap IDs used for allocating video output buffer */
+static int video_secure_ion_heap = ION_CP_MM_HEAP_ID;
+module_param(video_secure_ion_heap , int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(video_secure_ion_heap, "ION heap for secure video buffer allocation");
+
+static int video_nonsecure_ion_heap = ION_IOMMU_HEAP_ID;
+module_param(video_nonsecure_ion_heap, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(video_nonsecure_ion_heap, "ION heap for non-secure video buffer allocation");
static int generate_es_events;
module_param(generate_es_events, int, S_IRUGO | S_IWUSR);
@@ -1033,7 +1037,9 @@
actual_buffer_size &= ~(SZ_4K - 1);
temp_handle = ion_alloc(client, actual_buffer_size, SZ_4K,
- ION_HEAP(video_ion_alloc_heap), ION_FLAG_CACHED);
+ ION_HEAP(video_secure_ion_heap) |
+ ION_HEAP(video_nonsecure_ion_heap),
+ ION_FLAG_CACHED);
if (IS_ERR_OR_NULL(temp_handle)) {
ret = PTR_ERR(temp_handle);
@@ -2601,27 +2607,18 @@
const struct ts_packet_header *ts_header;
const struct ts_adaptation_field *adaptation_field;
- /*
- * When we play from front-end, we configure HW
- * to output the extra timestamp, if we are playing
- * from DVR, make sure the format is 192 packet.
- */
- if ((mpq_demux->source >= DMX_SOURCE_DVR0) &&
- (mpq_demux->demux.tsp_format != DMX_TSP_FORMAT_192_TAIL)) {
- MPQ_DVB_ERR_PRINT(
- "%s: invalid packet format %d for PCR extraction\n",
- __func__,
- mpq_demux->demux.tsp_format);
-
- return -EINVAL;
- }
-
ts_header = (const struct ts_packet_header *)buf;
/* Make sure this TS packet has a adaptation field */
if ((ts_header->sync_byte != 0x47) ||
(ts_header->adaptation_field_control == 0) ||
- (ts_header->adaptation_field_control == 1)) {
+ (ts_header->adaptation_field_control == 1) ||
+ ts_header->transport_error_indicator) {
+ MPQ_DVB_DBG_PRINT(
+ "%s: PCR packet dropped, AFC %d, TEI %d\n",
+ __func__,
+ ts_header->adaptation_field_control,
+ ts_header->transport_error_indicator);
return 0;
}
@@ -2642,10 +2639,21 @@
(((u64)adaptation_field->program_clock_reference_ext_1) << 8) +
adaptation_field->program_clock_reference_ext_2;
- stc = buf[190] << 16;
- stc += buf[189] << 8;
- stc += buf[188];
- stc *= 256; /* convert from 105.47 KHZ to 27MHz */
+ /*
+ * When we play from front-end, we configure HW
+ * to output the extra timestamp, if we are playing
+ * from DVR, we don't have a timestamp if the packet
+ * format is not 192-tail.
+ */
+ if ((mpq_demux->source >= DMX_SOURCE_DVR0) &&
+ (mpq_demux->demux.tsp_format != DMX_TSP_FORMAT_192_TAIL)) {
+ stc = 0;
+ } else {
+ stc = buf[190] << 16;
+ stc += buf[189] << 8;
+ stc += buf[188];
+ stc *= 256; /* convert from 105.47 KHZ to 27MHz */
+ }
data.data_length = 0;
data.pcr.pcr = pcr;
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 464f19f..ff0fc74 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1054,6 +1054,16 @@
The WCD9320 codec support either I2C/I2S or Slimbus for
control and data exchnage with master processor.
+config WCD9306_CODEC
+ tristate "WCD9306 Codec"
+ select SLIMBUS
+ select MFD_CORE
+ help
+ Enables the WCD9xxx codec core driver. The core driver provides
+ read/write capability to registers which are part of the
+ WCD9306 core and gives the ability to use the WCD9306 codec.
+ The WCD9306 codec supports either I2C/I2S or Slimbus for
+ control and data exchnage with master processor.
config MFD_RC5T583
bool "Ricoh RC5T583 Power Management system device"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 07552c8..ce65e3f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -81,6 +81,7 @@
obj-$(CONFIG_WCD9310_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
obj-$(CONFIG_WCD9304_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
obj-$(CONFIG_WCD9320_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
+obj-$(CONFIG_WCD9306_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
ifeq ($(CONFIG_SA1100_ASSABET),y)
diff --git a/drivers/mfd/wcd9xxx-core.c b/drivers/mfd/wcd9xxx-core.c
index d43b399..bc129da 100644
--- a/drivers/mfd/wcd9xxx-core.c
+++ b/drivers/mfd/wcd9xxx-core.c
@@ -46,6 +46,11 @@
#define WCD9XXX_I2C_DIGITAL_1 2
#define WCD9XXX_I2C_DIGITAL_2 3
+/* Number of return values needs to be checked for each
+ * registration of Slimbus of I2C bus for each codec
+ */
+#define NUM_WCD9XXX_REG_RET 8
+
struct wcd9xxx_i2c {
struct i2c_client *client;
struct i2c_msg xfer_msg[2];
@@ -58,6 +63,11 @@
"cdc-vdd-a-1p2v", "cdc-vddcx-1", "cdc-vddcx-2",
};
+static char *tapan_supplies[] = {
+ "cdc-vdd-buck", "cdc-vdd-h", "cdc-vdd-px",
+ "cdc-vdd-a-1p2v", "cdc-vdd-cx"
+};
+
static int wcd9xxx_dt_parse_vreg_info(struct device *dev,
struct wcd9xxx_regulator *vreg, const char *vreg_name);
static int wcd9xxx_dt_parse_micbias_info(struct device *dev,
@@ -275,6 +285,12 @@
},
};
+static struct mfd_cell tapan_devs[] = {
+ {
+ .name = "tapan_codec",
+ },
+};
+
static struct wcd9xx_codec_type {
u8 byte[4];
struct mfd_cell *dev;
@@ -287,6 +303,8 @@
TABLA_NUM_IRQS},
{{0x0, 0x0, 0x2, 0x1}, taiko_devs, ARRAY_SIZE(taiko_devs),
TAIKO_NUM_IRQS},
+ {{0x0, 0x0, 0x3, 0x1}, tapan_devs, ARRAY_SIZE(tapan_devs),
+ TAPAN_NUM_IRQS},
{{0x0, 0x0, 0x0, 0x1}, sitar_devs, ARRAY_SIZE(sitar_devs),
SITAR_NUM_IRQS},
{{0x1, 0x0, 0x1, 0x1}, sitar_devs, ARRAY_SIZE(sitar_devs),
@@ -987,92 +1005,54 @@
return 0;
}
+static int wcd9xxx_read_of_property_u32(struct device *dev,
+ const char *name, u32 *val)
+{
+ int ret = 0;
+ ret = of_property_read_u32(dev->of_node, name, val);
+ if (ret)
+ dev_err(dev, "Looking up %s property in node %s failed",
+ name, dev->of_node->full_name);
+ return ret;
+}
+
static int wcd9xxx_dt_parse_micbias_info(struct device *dev,
struct wcd9xxx_micbias_setting *micbias)
{
- int ret = 0;
- char prop_name[CODEC_DT_MAX_PROP_SIZE];
u32 prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-ldoh-v");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->ldoh_v = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-ldoh-v",
+ &prop_val)))
+ micbias->ldoh_v = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-cfilt1-mv");
- ret = of_property_read_u32(dev->of_node, prop_name,
- &micbias->cfilt1_mv);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
+ wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-cfilt1-mv",
+ &micbias->cfilt1_mv);
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-cfilt2-mv");
- ret = of_property_read_u32(dev->of_node, prop_name,
- &micbias->cfilt2_mv);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
+ wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-cfilt2-mv",
+ &micbias->cfilt2_mv);
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias-cfilt3-mv");
- ret = of_property_read_u32(dev->of_node, prop_name,
- &micbias->cfilt3_mv);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
+ wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias-cfilt3-mv",
+ &micbias->cfilt3_mv);
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias1-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias1_cfilt_sel = (u8)prop_val;
+ /* Read micbias values for codec. Does not matter even if a few
+ * micbias values are not defined in the Device Tree. Codec will
+ * anyway not use those values
+ */
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias1-cfilt-sel",
+ &prop_val)))
+ micbias->bias1_cfilt_sel = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias2-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias2_cfilt_sel = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias2-cfilt-sel",
+ &prop_val)))
+ micbias->bias2_cfilt_sel = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias3-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias3_cfilt_sel = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias3-cfilt-sel",
+ &prop_val)))
+ micbias->bias3_cfilt_sel = (u8)prop_val;
- snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE,
- "qcom,cdc-micbias4-cfilt-sel");
- ret = of_property_read_u32(dev->of_node, prop_name, &prop_val);
- if (ret) {
- dev_err(dev, "Looking up %s property in node %s failed",
- prop_name, dev->of_node->full_name);
- return -ENODEV;
- }
- micbias->bias4_cfilt_sel = (u8)prop_val;
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-micbias4-cfilt-sel",
+ &prop_val)))
+ micbias->bias4_cfilt_sel = (u8)prop_val;
/* micbias external cap */
micbias->bias1_cap_mode =
@@ -1153,6 +1133,9 @@
(!strcmp(dev_name(dev), WCD9XXX_I2C_GSBI_SLAVE_ID))) {
codec_supplies = taiko_supplies;
num_of_supplies = ARRAY_SIZE(taiko_supplies);
+ } else if (!strcmp(dev_name(dev), "tapan-slim-pgd")) {
+ codec_supplies = tapan_supplies;
+ num_of_supplies = ARRAY_SIZE(tapan_supplies);
} else {
dev_err(dev, "%s unsupported device %s\n",
__func__, dev_name(dev));
@@ -1552,6 +1535,23 @@
.suspend = wcd9xxx_slim_suspend,
};
+static const struct slim_device_id tapan_slimtest_id[] = {
+ {"tapan-slim-pgd", 0},
+ {}
+};
+
+static struct slim_driver tapan_slim_driver = {
+ .driver = {
+ .name = "tapan-slim",
+ .owner = THIS_MODULE,
+ },
+ .probe = wcd9xxx_slim_probe,
+ .remove = wcd9xxx_slim_remove,
+ .id_table = tapan_slimtest_id,
+ .resume = wcd9xxx_slim_resume,
+ .suspend = wcd9xxx_slim_suspend,
+};
+
static struct i2c_device_id wcd9xxx_id_table[] = {
{"wcd9xxx-i2c", WCD9XXX_I2C_TOP_LEVEL},
{"wcd9xxx-i2c", WCD9XXX_I2C_ANALOG},
@@ -1596,39 +1596,48 @@
static int __init wcd9xxx_init(void)
{
- int ret1, ret2, ret3, ret4, ret5, ret6, ret7;
+ int ret[NUM_WCD9XXX_REG_RET];
+ int i = 0;
wcd9xxx_intf = WCD9XXX_INTERFACE_TYPE_PROBING;
- ret1 = slim_driver_register(&tabla_slim_driver);
- if (ret1 != 0)
- pr_err("Failed to register tabla SB driver: %d\n", ret1);
+ ret[0] = slim_driver_register(&tabla_slim_driver);
+ if (ret[0])
+ pr_err("Failed to register tabla SB driver: %d\n", ret[0]);
- ret2 = slim_driver_register(&tabla2x_slim_driver);
- if (ret2 != 0)
- pr_err("Failed to register tabla2x SB driver: %d\n", ret2);
+ ret[1] = slim_driver_register(&tabla2x_slim_driver);
+ if (ret[1])
+ pr_err("Failed to register tabla2x SB driver: %d\n", ret[1]);
- ret3 = i2c_add_driver(&tabla_i2c_driver);
- if (ret3 != 0)
- pr_err("failed to add the tabla2x I2C driver\n");
+ ret[2] = i2c_add_driver(&tabla_i2c_driver);
+ if (ret[2])
+ pr_err("failed to add the tabla2x I2C driver: %d\n", ret[2]);
- ret4 = slim_driver_register(&sitar_slim_driver);
- if (ret4 != 0)
- pr_err("Failed to register sitar SB driver: %d\n", ret4);
+ ret[3] = slim_driver_register(&sitar_slim_driver);
+ if (ret[3])
+ pr_err("Failed to register sitar SB driver: %d\n", ret[3]);
- ret5 = slim_driver_register(&sitar1p1_slim_driver);
- if (ret5 != 0)
- pr_err("Failed to register sitar SB driver: %d\n", ret5);
+ ret[4] = slim_driver_register(&sitar1p1_slim_driver);
+ if (ret[4])
+ pr_err("Failed to register sitar SB driver: %d\n", ret[4]);
- ret6 = slim_driver_register(&taiko_slim_driver);
- if (ret6 != 0)
- pr_err("Failed to register taiko SB driver: %d\n", ret6);
+ ret[5] = slim_driver_register(&taiko_slim_driver);
+ if (ret[5])
+ pr_err("Failed to register taiko SB driver: %d\n", ret[5]);
- ret7 = i2c_add_driver(&wcd9xxx_i2c_driver);
- if (ret7 != 0)
- pr_err("failed to add the wcd9xxx I2C driver\n");
+ ret[6] = i2c_add_driver(&wcd9xxx_i2c_driver);
+ if (ret[6])
+ pr_err("failed to add the wcd9xxx I2C driver: %d\n", ret[6]);
- return (ret1 && ret2 && ret3 && ret4 && ret5 && ret6 && ret7) ? -1 : 0;
+ ret[7] = slim_driver_register(&tapan_slim_driver);
+ if (ret[7])
+ pr_err("Failed to register tapan SB driver: %d\n", ret[7]);
+
+ for (i = 0; i < NUM_WCD9XXX_REG_RET; i++) {
+ if (ret[i])
+ return ret[i];
+ }
+ return 0;
}
module_init(wcd9xxx_init);
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index e8f3d38..47dc9d2 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -163,6 +163,10 @@
static int msmsdcc_dt_get_array(struct device *dev, const char *prop_name,
u32 **out_array, int *len, int size);
static int msmsdcc_execute_tuning(struct mmc_host *mmc, u32 opcode);
+static bool msmsdcc_is_wait_for_auto_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq);
+static bool msmsdcc_is_wait_for_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq);
static inline unsigned short msmsdcc_get_nr_sg(struct msmsdcc_host *host)
{
@@ -440,18 +444,23 @@
{
struct mmc_request *mrq = host->curr.mrq;
- if (!mrq || !mrq->cmd || (!mrq->data && !host->pending_dpsm_reset))
- goto out;
+ if (!mrq || !mrq->cmd || !mrq->data)
+ goto out;
/*
- * For CMD24, if auto prog done is not supported defer
- * dpsm reset until prog done is received. Otherwise,
- * we poll here unnecessarily as TXACTIVE will not be
- * deasserted until DAT0 goes high.
+ * If we have not waited for the prog done for write transfer then
+ * perform the DPSM reset without polling for TXACTIVE.
+ * Otherwise, we poll here unnecessarily as TXACTIVE will not be
+ * deasserted until DAT0 (Busy line) goes high.
*/
- if ((mrq->cmd->opcode == MMC_WRITE_BLOCK) && !is_auto_prog_done(host)) {
- host->pending_dpsm_reset = true;
- goto out;
+ if (mrq->data->flags & MMC_DATA_WRITE) {
+ if (!msmsdcc_is_wait_for_prog_done(host, mrq)) {
+ if (is_wait_for_tx_rx_active(host) &&
+ !is_auto_prog_done(host))
+ pr_warning("%s: %s: AUTO_PROG_DONE capability is must\n",
+ mmc_hostname(host->mmc), __func__);
+ goto no_polling;
+ }
}
/* Make sure h/w (TX/RX) is inactive before resetting DPSM */
@@ -473,15 +482,14 @@
& MCI_TXACTIVE ? "TX" : "RX");
msmsdcc_dump_sdcc_state(host);
msmsdcc_reset_and_restore(host);
- host->pending_dpsm_reset = false;
goto out;
}
}
}
+no_polling:
writel_relaxed(0, host->base + MMCIDATACTRL);
msmsdcc_sync_reg_wr(host); /* Allow the DPSM to be reset */
- host->pending_dpsm_reset = false;
out:
return;
}
@@ -1240,13 +1248,10 @@
MCI_DLL_CONFIG) & ~MCI_CDR_EN),
host->base + MCI_DLL_CONFIG);
- if (((cmd->flags & MMC_RSP_R1B) == MMC_RSP_R1B) ||
- (cmd->opcode == MMC_SEND_STATUS &&
- !(cmd->flags & MMC_CMD_ADTC))) {
+ if ((cmd->flags & MMC_RSP_R1B) == MMC_RSP_R1B) {
*c |= MCI_CPSM_PROGENA;
host->prog_enable = 1;
}
-
if (cmd == cmd->mrq->stop)
*c |= MCI_CSPM_MCIABORT;
@@ -2139,6 +2144,43 @@
}
}
+/*
+ * This function returns true if AUTO_PROG_DONE feature of host is
+ * applicable for current request, returns "false" otherwise.
+ *
+ * NOTE: Caller should call this function only for data write operations.
+ */
+static bool msmsdcc_is_wait_for_auto_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq)
+{
+ /*
+ * Auto-prog done will be enabled for following cases:
+ * mrq->sbc | mrq->stop
+ * _____________|________________
+ * True | Don't care
+ * False | False (CMD24, ACMD25 use case)
+ */
+ if (is_auto_prog_done(host) && (mrq->sbc || !mrq->stop))
+ return true;
+
+ return false;
+}
+
+/*
+ * This function returns true if controller can wait for prog done
+ * for current request, returns "false" otherwise.
+ *
+ * NOTE: Caller should call this function only for data write operations.
+ */
+static bool msmsdcc_is_wait_for_prog_done(struct msmsdcc_host *host,
+ struct mmc_request *mrq)
+{
+ if (msmsdcc_is_wait_for_auto_prog_done(host, mrq) || mrq->stop)
+ return true;
+
+ return false;
+}
+
static void
msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
@@ -2235,16 +2277,8 @@
}
if (mrq->data && (mrq->data->flags & MMC_DATA_WRITE)) {
- if (is_auto_prog_done(host)) {
- /*
- * Auto-prog done will be enabled for following cases:
- * mrq->sbc | mrq->stop
- * _____________|________________
- * True | Don't care
- * False | False (CMD24, ACMD25 use case)
- */
- if (mrq->sbc || !mrq->stop)
- host->curr.wait_for_auto_prog_done = true;
+ if (msmsdcc_is_wait_for_auto_prog_done(host, mrq)) {
+ host->curr.wait_for_auto_prog_done = true;
} else {
if ((mrq->cmd->opcode == SD_IO_RW_EXTENDED) ||
(mrq->cmd->opcode == 54))
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index 7469c8e..8ae5b86 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -422,7 +422,6 @@
struct mutex clk_mutex;
bool pending_resume;
unsigned int idle_tout; /* Timeout in msecs */
- bool pending_dpsm_reset;
bool enforce_pio_mode;
bool print_pm_stats;
struct msmsdcc_msm_bus_vote msm_bus_vote;
diff --git a/drivers/platform/msm/ipa/ipa.c b/drivers/platform/msm/ipa/ipa.c
index 288de52..d673e5a 100644
--- a/drivers/platform/msm/ipa/ipa.c
+++ b/drivers/platform/msm/ipa/ipa.c
@@ -929,23 +929,30 @@
static void ipa_set_aggregation_params(void)
{
struct ipa_ep_cfg_aggr agg_params;
+ struct ipa_ep_cfg_hdr hdr_params;
u32 producer_hdl = 0;
u32 consumer_hdl = 0;
rmnet_bridge_get_client_handles(&producer_hdl, &consumer_hdl);
+ /* configure aggregation on producer */
+ memset(&agg_params, 0, sizeof(struct ipa_ep_cfg_aggr));
+ agg_params.aggr_en = IPA_ENABLE_AGGR;
agg_params.aggr = ipa_ctx->aggregation_type;
agg_params.aggr_byte_limit = ipa_ctx->aggregation_byte_limit;
agg_params.aggr_time_limit = ipa_ctx->aggregation_time_limit;
-
- /* configure aggregation on producer */
- agg_params.aggr_en = IPA_ENABLE_AGGR;
ipa_cfg_ep_aggr(producer_hdl, &agg_params);
- /* configure deaggregation on consumer */
- agg_params.aggr_en = IPA_ENABLE_DEAGGR;
- ipa_cfg_ep_aggr(consumer_hdl, &agg_params);
+ /* configure header on producer */
+ memset(&hdr_params, 0, sizeof(struct ipa_ep_cfg_hdr));
+ hdr_params.hdr_len = 1;
+ ipa_cfg_ep_hdr(producer_hdl, &hdr_params);
+ /* configure deaggregation on consumer */
+ memset(&agg_params, 0, sizeof(struct ipa_ep_cfg_aggr));
+ agg_params.aggr_en = IPA_ENABLE_DEAGGR;
+ agg_params.aggr = ipa_ctx->aggregation_type;
+ ipa_cfg_ep_aggr(consumer_hdl, &agg_params);
}
/*
@@ -1340,6 +1347,22 @@
result = -ENODEV;
goto fail_init_hw;
}
+
+ /* setup chicken bits */
+ result = ipa_set_single_ndp_per_mbim(true);
+ if (result) {
+ IPAERR(":failed to set single ndp per mbim.\n");
+ result = -EFAULT;
+ goto fail_init_hw;
+ }
+
+ result = ipa_set_hw_timer_fix_for_mbim_aggr(true);
+ if (result) {
+ IPAERR(":failed to set HW timer fix for MBIM aggregation.\n");
+ result = -EFAULT;
+ goto fail_init_hw;
+ }
+
/* read how much SRAM is available for SW use */
ipa_ctx->smem_sz = ipa_read_reg(ipa_ctx->mmio,
IPA_SHARED_MEM_SIZE_OFST);
diff --git a/drivers/platform/msm/ipa/ipa_i.h b/drivers/platform/msm/ipa/ipa_i.h
index 3be2369..4172371 100644
--- a/drivers/platform/msm/ipa/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_i.h
@@ -654,6 +654,8 @@
int ipa_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem);
int ipa_generate_rt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem);
int ipa_generate_flt_hw_tbl(enum ipa_ip_type ip, struct ipa_mem_buffer *mem);
+int ipa_set_single_ndp_per_mbim(bool);
+int ipa_set_hw_timer_fix_for_mbim_aggr(bool);
void ipa_debugfs_init(void);
void ipa_debugfs_remove(void);
diff --git a/drivers/platform/msm/ipa/ipa_reg.h b/drivers/platform/msm/ipa/ipa_reg.h
index 61913b6..ca67e35 100644
--- a/drivers/platform/msm/ipa/ipa_reg.h
+++ b/drivers/platform/msm/ipa/ipa_reg.h
@@ -213,6 +213,8 @@
#define IPA_AGGREGATION_QCNCM_SIG_BMSK 0xff000000
#define IPA_AGGREGATION_SINGLE_NDP_MSK 0x1
#define IPA_AGGREGATION_SINGLE_NDP_BMSK 0xfffffffe
+#define IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_SHFT 2
+#define IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_BMSK 0x4
#define IPA_SRAM_DIRECT_ACCESS_n_OFST(n) (0x00004000 + 0x4 * (n))
#define IPA_SRAM_DIRECT_ACCESS_n_RMSK 0xffffffff
diff --git a/drivers/platform/msm/ipa/ipa_utils.c b/drivers/platform/msm/ipa/ipa_utils.c
index d5d5566..7cdde4a 100644
--- a/drivers/platform/msm/ipa/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_utils.c
@@ -1323,6 +1323,24 @@
EXPORT_SYMBOL(ipa_set_single_ndp_per_mbim);
/**
+ * ipa_set_hw_timer_fix_for_mbim_aggr() - Enable/disable HW timer fix
+ * for MBIM aggregation.
+ * @enable: [in] true for enable HW fix; false otherwise
+ *
+ * Returns: 0 on success
+ */
+int ipa_set_hw_timer_fix_for_mbim_aggr(bool enable)
+{
+ u32 reg_val;
+ reg_val = ipa_read_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_1_OFST);
+ ipa_write_reg(ipa_ctx->mmio, IPA_AGGREGATION_SPARE_REG_1_OFST,
+ (enable << IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_SHFT) |
+ (reg_val & ~IPA_AGGREGATION_HW_TIMER_FIX_MBIM_AGGR_BMSK));
+ return 0;
+}
+EXPORT_SYMBOL(ipa_set_hw_timer_fix_for_mbim_aggr);
+
+/**
* ipa_straddle_boundary() - Checks whether a memory buffer straddles a boundary
* @start: start address of the memory buffer
* @end: end address of the memory buffer
diff --git a/drivers/power/pm8921-charger.c b/drivers/power/pm8921-charger.c
index 1ca0728..c86ba9e 100644
--- a/drivers/power/pm8921-charger.c
+++ b/drivers/power/pm8921-charger.c
@@ -293,6 +293,7 @@
int btc_override_hot_decidegc;
int btc_delay_ms;
bool btc_panic_if_cant_stop_chg;
+ int stop_chg_upon_expiry;
};
/* user space parameter to limit usb current */
@@ -2733,9 +2734,11 @@
struct pm8921_chg_chip *chip = data;
int ret;
- ret = pm_chg_failed_clear(chip, 1);
- if (ret)
- pr_err("Failed to write CHG_FAILED_CLEAR bit\n");
+ if (!chip->stop_chg_upon_expiry) {
+ ret = pm_chg_failed_clear(chip, 1);
+ if (ret)
+ pr_err("Failed to write CHG_FAILED_CLEAR bit\n");
+ }
pr_err("batt_present = %d, batt_temp_ok = %d, state_changed_to=%d\n",
get_prop_batt_present(chip),
@@ -3237,7 +3240,6 @@
struct pm8921_chg_chip *chip = container_of(dwork,
struct pm8921_chg_chip, update_heartbeat_work);
- pm_chg_failed_clear(chip, 1);
power_supply_changed(&chip->batt_psy);
if (chip->recent_reported_soc <= 20)
schedule_delayed_work(&chip->update_heartbeat_work,
@@ -3670,8 +3672,6 @@
int ichg_meas_ua, ichg_meas_ma;
int vbat_batt_terminal_uv;
- pm_chg_failed_clear(chip, 1);
-
pm8921_bms_get_simultaneous_battery_voltage_and_current(
&ichg_meas_ua, &vbat_meas_uv);
vbat_meas_mv = vbat_meas_uv / 1000;
@@ -4736,6 +4736,8 @@
if (chip->btc_override)
pm8921_chg_btc_override_init(chip);
+ chip->stop_chg_upon_expiry = pdata->stop_chg_upon_expiry;
+
chip->usb_psy.name = "usb",
chip->usb_psy.type = POWER_SUPPLY_TYPE_USB,
chip->usb_psy.supplied_to = pm_power_supplied_to,
diff --git a/drivers/thermal/qpnp-adc-tm.c b/drivers/thermal/qpnp-adc-tm.c
index 20481ac..4818941 100644
--- a/drivers/thermal/qpnp-adc-tm.c
+++ b/drivers/thermal/qpnp-adc-tm.c
@@ -1488,7 +1488,7 @@
return 0;
fail:
- adc_qpnp = NULL;
+ qpnp_adc_tm = NULL;
return rc;
}
diff --git a/include/linux/mfd/pm8xxx/pm8921-charger.h b/include/linux/mfd/pm8xxx/pm8921-charger.h
index 44f8538..ab52309 100644
--- a/include/linux/mfd/pm8xxx/pm8921-charger.h
+++ b/include/linux/mfd/pm8xxx/pm8921-charger.h
@@ -138,6 +138,10 @@
* driver couldn't stop charging when battery
* temperature is out of bounds. Used only if
* btc_override = 1
+ * stop_chg_upon_expiry: flag to indicate that the charger driver should
+ * stop charging the battery when the safety timer
+ * expires. If not set the charger driver will
+ * restart charging upon expiry.
*/
struct pm8921_charger_platform_data {
struct pm8xxx_charger_core_data charger_cdata;
@@ -183,6 +187,7 @@
int btc_override_hot_degc;
int btc_delay_ms;
int btc_panic_if_cant_stop_chg;
+ int stop_chg_upon_expiry;
};
enum pm8921_charger_source {
diff --git a/include/linux/mfd/wcd9xxx/core.h b/include/linux/mfd/wcd9xxx/core.h
index 2874a3b..4b2ad66 100644
--- a/include/linux/mfd/wcd9xxx/core.h
+++ b/include/linux/mfd/wcd9xxx/core.h
@@ -83,6 +83,7 @@
TABLA_NUM_IRQS = WCD9XXX_NUM_IRQS,
SITAR_NUM_IRQS = WCD9XXX_NUM_IRQS,
TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
+ TAPAN_NUM_IRQS = WCD9XXX_NUM_IRQS,
};
@@ -212,7 +213,8 @@
void wcd9xxx_disable_irq_sync(struct wcd9xxx *wcd9xxx, int irq);
#if defined(CONFIG_WCD9310_CODEC) || \
defined(CONFIG_WCD9304_CODEC) || \
- defined(CONFIG_WCD9320_CODEC)
+ defined(CONFIG_WCD9320_CODEC) || \
+ defined(CONFIG_WCD9306_CODEC)
int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent);
#else
@@ -221,5 +223,5 @@
{
return 0;
}
-#endif
+#endif /* CONFIG_OF */
#endif
diff --git a/include/linux/mfd/wcd9xxx/wcd9306_registers.h b/include/linux/mfd/wcd9xxx/wcd9306_registers.h
new file mode 100644
index 0000000..1254fac
--- /dev/null
+++ b/include/linux/mfd/wcd9xxx/wcd9306_registers.h
@@ -0,0 +1,1015 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef WCD9306_REGISTERS_H
+#define WCD9306_REGISTERS_H
+
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+
+#define TAPAN_A_CHIP_CTL WCD9XXX_A_CHIP_CTL
+#define TAPAN_A_CHIP_CTL__POR WCD9XXX_A_CHIP_CTL__POR
+#define TAPAN_A_CHIP_STATUS WCD9XXX_A_CHIP_STATUS
+#define TAPAN_A_CHIP_STATUS__POR WCD9XXX_A_CHIP_STATUS__POR
+#define TAPAN_A_CHIP_ID_BYTE_0 WCD9XXX_A_CHIP_ID_BYTE_0
+#define TAPAN_A_CHIP_ID_BYTE_0__POR WCD9XXX_A_CHIP_ID_BYTE_0__POR
+#define TAPAN_A_CHIP_ID_BYTE_1 WCD9XXX_A_CHIP_ID_BYTE_1
+#define TAPAN_A_CHIP_ID_BYTE_1__POR WCD9XXX_A_CHIP_ID_BYTE_1__POR
+#define TAPAN_A_CHIP_ID_BYTE_2 WCD9XXX_A_CHIP_ID_BYTE_2
+#define TAPAN_A_CHIP_ID_BYTE_2__POR WCD9XXX_A_CHIP_ID_BYTE_2__POR
+#define TAPAN_A_CHIP_ID_BYTE_3 WCD9XXX_A_CHIP_ID_BYTE_3
+#define TAPAN_A_CHIP_ID_BYTE_3__POR WCD9XXX_A_CHIP_ID_BYTE_3__POR
+#define TAPAN_A_CHIP_VERSION WCD9XXX_A_CHIP_VERSION
+#define TAPAN_A_CHIP_VERSION__POR WCD9XXX_A_CHIP_VERSION__POR
+#define TAPAN_A_CHIP_DEBUG_CTL (0x009)
+#define TAPAN_A_CHIP_DEBUG_CTL__POR (0x00)
+#define TAPAN_A_SLAVE_ID_1 (0x00C)
+#define TAPAN_A_SLAVE_ID_1__POR (0x77)
+#define TAPAN_A_SLAVE_ID_2 (0x00D)
+#define TAPAN_A_SLAVE_ID_2__POR (0x66)
+#define TAPAN_A_SLAVE_ID_3 (0x00E)
+#define TAPAN_A_SLAVE_ID_3__POR (0x55)
+#define TAPAN_A_PIN_CTL_OE0 (0x010)
+#define TAPAN_A_PIN_CTL_OE0__POR (0x00)
+#define TAPAN_A_PIN_CTL_DATA0 (0x012)
+#define TAPAN_A_PIN_CTL_DATA0__POR (0x00)
+#define TAPAN_A_HDRIVE_GENERIC (0x018)
+#define TAPAN_A_HDRIVE_GENERIC__POR (0x00)
+#define TAPAN_A_HDRIVE_OVERRIDE (0x019)
+#define TAPAN_A_HDRIVE_OVERRIDE__POR (0x08)
+#define TAPAN_A_ANA_CSR_WAIT_STATE (0x020)
+#define TAPAN_A_ANA_CSR_WAIT_STATE__POR (0x44)
+#define TAPAN_A_PROCESS_MONITOR_CTL0 (0x040)
+#define TAPAN_A_PROCESS_MONITOR_CTL0__POR (0x80)
+#define TAPAN_A_PROCESS_MONITOR_CTL1 (0x041)
+#define TAPAN_A_PROCESS_MONITOR_CTL1__POR (0x00)
+#define TAPAN_A_PROCESS_MONITOR_CTL2 (0x042)
+#define TAPAN_A_PROCESS_MONITOR_CTL2__POR (0x00)
+#define TAPAN_A_PROCESS_MONITOR_CTL3 (0x043)
+#define TAPAN_A_PROCESS_MONITOR_CTL3__POR (0x01)
+#define TAPAN_A_QFUSE_CTL (0x048)
+#define TAPAN_A_QFUSE_CTL__POR (0x00)
+#define TAPAN_A_QFUSE_STATUS (0x049)
+#define TAPAN_A_QFUSE_STATUS__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT0 (0x04A)
+#define TAPAN_A_QFUSE_DATA_OUT0__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT1 (0x04B)
+#define TAPAN_A_QFUSE_DATA_OUT1__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT2 (0x04C)
+#define TAPAN_A_QFUSE_DATA_OUT2__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT3 (0x04D)
+#define TAPAN_A_QFUSE_DATA_OUT3__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT4 (0x04E)
+#define TAPAN_A_QFUSE_DATA_OUT4__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT5 (0x04F)
+#define TAPAN_A_QFUSE_DATA_OUT5__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT6 (0x050)
+#define TAPAN_A_QFUSE_DATA_OUT6__POR (0x00)
+#define TAPAN_A_QFUSE_DATA_OUT7 (0x051)
+#define TAPAN_A_QFUSE_DATA_OUT7__POR (0x00)
+#define TAPAN_A_CDC_CTL (0x080)
+#define TAPAN_A_CDC_CTL__POR (0x00)
+#define TAPAN_A_LEAKAGE_CTL (0x088)
+#define TAPAN_A_LEAKAGE_CTL__POR (0x04)
+#define TAPAN_A_INTR_MODE (0x090)
+#define TAPAN_A_INTR_MODE__POR (0x00)
+#define TAPAN_A_INTR_MASK0 (0x094)
+#define TAPAN_A_INTR_MASK0__POR (0xFF)
+#define TAPAN_A_INTR_MASK1 (0x095)
+#define TAPAN_A_INTR_MASK1__POR (0xFF)
+#define TAPAN_A_INTR_MASK2 (0x096)
+#define TAPAN_A_INTR_MASK2__POR (0x3F)
+#define TAPAN_A_INTR_MASK3 (0x097)
+#define TAPAN_A_INTR_MASK3__POR (0x3F)
+#define TAPAN_A_INTR_STATUS0 (0x098)
+#define TAPAN_A_INTR_STATUS0__POR (0x00)
+#define TAPAN_A_INTR_STATUS1 (0x099)
+#define TAPAN_A_INTR_STATUS1__POR (0x00)
+#define TAPAN_A_INTR_STATUS2 (0x09A)
+#define TAPAN_A_INTR_STATUS2__POR (0x00)
+#define TAPAN_A_INTR_STATUS3 (0x09B)
+#define TAPAN_A_INTR_STATUS3__POR (0x00)
+#define TAPAN_A_INTR_CLEAR0 (0x09C)
+#define TAPAN_A_INTR_CLEAR0__POR (0x00)
+#define TAPAN_A_INTR_CLEAR1 (0x09D)
+#define TAPAN_A_INTR_CLEAR1__POR (0x00)
+#define TAPAN_A_INTR_CLEAR2 (0x09E)
+#define TAPAN_A_INTR_CLEAR2__POR (0x00)
+#define TAPAN_A_INTR_CLEAR3 (0x09F)
+#define TAPAN_A_INTR_CLEAR3__POR (0x00)
+#define TAPAN_A_INTR_LEVEL0 (0x0A0)
+#define TAPAN_A_INTR_LEVEL0__POR (0x01)
+#define TAPAN_A_INTR_LEVEL1 (0x0A1)
+#define TAPAN_A_INTR_LEVEL1__POR (0x00)
+#define TAPAN_A_INTR_LEVEL2 (0x0A2)
+#define TAPAN_A_INTR_LEVEL2__POR (0x00)
+#define TAPAN_A_INTR_LEVEL3 (0x0A3)
+#define TAPAN_A_INTR_LEVEL3__POR (0x00)
+#define TAPAN_A_INTR_TEST0 (0x0A4)
+#define TAPAN_A_INTR_TEST0__POR (0x00)
+#define TAPAN_A_INTR_TEST1 (0x0A5)
+#define TAPAN_A_INTR_TEST1__POR (0x00)
+#define TAPAN_A_INTR_TEST2 (0x0A6)
+#define TAPAN_A_INTR_TEST2__POR (0x00)
+#define TAPAN_A_INTR_TEST3 (0x0A7)
+#define TAPAN_A_INTR_TEST3__POR (0x00)
+#define TAPAN_A_INTR_SET0 (0x0A8)
+#define TAPAN_A_INTR_SET0__POR (0x00)
+#define TAPAN_A_INTR_SET1 (0x0A9)
+#define TAPAN_A_INTR_SET1__POR (0x00)
+#define TAPAN_A_INTR_SET2 (0x0AA)
+#define TAPAN_A_INTR_SET2__POR (0x00)
+#define TAPAN_A_INTR_SET3 (0x0AB)
+#define TAPAN_A_INTR_SET3__POR (0x00)
+#define TAPAN_A_INTR_DESTN0 (0x0AC)
+#define TAPAN_A_INTR_DESTN0__POR (0x00)
+#define TAPAN_A_INTR_DESTN1 (0x0AD)
+#define TAPAN_A_INTR_DESTN1__POR (0x00)
+#define TAPAN_A_INTR_DESTN2 (0x0AE)
+#define TAPAN_A_INTR_DESTN2__POR (0x00)
+#define TAPAN_A_INTR_DESTN3 (0x0AF)
+#define TAPAN_A_INTR_DESTN3__POR (0x00)
+#define TAPAN_A_CDC_DMIC_DATA0_MODE (0x0C0)
+#define TAPAN_A_CDC_DMIC_DATA0_MODE__POR (0x00)
+#define TAPAN_A_CDC_DMIC_CLK0_MODE (0x0C1)
+#define TAPAN_A_CDC_DMIC_CLK0_MODE__POR (0x00)
+#define TAPAN_A_CDC_DMIC_DATA1_MODE (0x0C2)
+#define TAPAN_A_CDC_DMIC_DATA1_MODE__POR (0x00)
+#define TAPAN_A_CDC_DMIC_CLK1_MODE (0x0C3)
+#define TAPAN_A_CDC_DMIC_CLK1_MODE__POR (0x00)
+#define TAPAN_A_CDC_INTR_MODE (0x0C4)
+#define TAPAN_A_CDC_INTR_MODE__POR (0x00)
+#define TAPAN_A_BIAS_REF_CTL (0x100)
+#define TAPAN_A_BIAS_REF_CTL__POR (0x1C)
+#define TAPAN_A_BIAS_CENTRAL_BG_CTL (0x101)
+#define TAPAN_A_BIAS_CENTRAL_BG_CTL__POR (0x50)
+#define TAPAN_A_BIAS_PRECHRG_CTL (0x102)
+#define TAPAN_A_BIAS_PRECHRG_CTL__POR (0x07)
+#define TAPAN_A_BIAS_CURR_CTL_1 (0x103)
+#define TAPAN_A_BIAS_CURR_CTL_1__POR (0x52)
+#define TAPAN_A_BIAS_CURR_CTL_2 (0x104)
+#define TAPAN_A_BIAS_CURR_CTL_2__POR (0x00)
+#define TAPAN_A_BIAS_OSC_BG_CTL (0x105)
+#define TAPAN_A_BIAS_OSC_BG_CTL__POR (0x16)
+#define TAPAN_A_CLK_BUFF_EN1 (0x108)
+#define TAPAN_A_CLK_BUFF_EN1__POR (0x04)
+#define TAPAN_A_CLK_BUFF_EN2 (0x109)
+#define TAPAN_A_CLK_BUFF_EN2__POR (0x02)
+#define TAPAN_A_LDO_H_MODE_1 (0x110)
+#define TAPAN_A_LDO_H_MODE_1__POR (0x65)
+#define TAPAN_A_LDO_H_MODE_2 (0x111)
+#define TAPAN_A_LDO_H_MODE_2__POR (0xA8)
+#define TAPAN_A_LDO_H_LOOP_CTL (0x112)
+#define TAPAN_A_LDO_H_LOOP_CTL__POR (0x6B)
+#define TAPAN_A_LDO_H_COMP_1 (0x113)
+#define TAPAN_A_LDO_H_COMP_1__POR (0x84)
+#define TAPAN_A_LDO_H_COMP_2 (0x114)
+#define TAPAN_A_LDO_H_COMP_2__POR (0xE0)
+#define TAPAN_A_LDO_H_BIAS_1 (0x115)
+#define TAPAN_A_LDO_H_BIAS_1__POR (0x6D)
+#define TAPAN_A_LDO_H_BIAS_2 (0x116)
+#define TAPAN_A_LDO_H_BIAS_2__POR (0xA5)
+#define TAPAN_A_LDO_H_BIAS_3 (0x117)
+#define TAPAN_A_LDO_H_BIAS_3__POR (0x60)
+#define TAPAN_A_MICB_CFILT_1_CTL (0x128)
+#define TAPAN_A_MICB_CFILT_1_CTL__POR (0x40)
+#define TAPAN_A_MICB_CFILT_1_VAL (0x129)
+#define TAPAN_A_MICB_CFILT_1_VAL__POR (0x80)
+#define TAPAN_A_MICB_CFILT_1_PRECHRG (0x12A)
+#define TAPAN_A_MICB_CFILT_1_PRECHRG__POR (0x00)
+#define TAPAN_A_MICB_1_CTL (0x12B)
+#define TAPAN_A_MICB_1_CTL__POR (0x02)
+#define TAPAN_A_MICB_1_INT_RBIAS (0x12C)
+#define TAPAN_A_MICB_1_INT_RBIAS__POR (0x24)
+#define TAPAN_A_MICB_1_MBHC (0x12D)
+#define TAPAN_A_MICB_1_MBHC__POR (0x01)
+#define TAPAN_A_MICB_CFILT_2_CTL (0x12E)
+#define TAPAN_A_MICB_CFILT_2_CTL__POR (0x40)
+#define TAPAN_A_MICB_CFILT_2_VAL (0x12F)
+#define TAPAN_A_MICB_CFILT_2_VAL__POR (0x80)
+#define TAPAN_A_MICB_CFILT_2_PRECHRG (0x130)
+#define TAPAN_A_MICB_CFILT_2_PRECHRG__POR (0x00)
+#define TAPAN_A_MICB_2_CTL (0x131)
+#define TAPAN_A_MICB_2_CTL__POR (0x12)
+#define TAPAN_A_MICB_2_INT_RBIAS (0x132)
+#define TAPAN_A_MICB_2_INT_RBIAS__POR (0x24)
+#define TAPAN_A_MICB_2_MBHC (0x133)
+#define TAPAN_A_MICB_2_MBHC__POR (0x02)
+#define TAPAN_A_MICB_CFILT_3_CTL (0x134)
+#define TAPAN_A_MICB_CFILT_3_CTL__POR (0x40)
+#define TAPAN_A_MICB_CFILT_3_VAL (0x135)
+#define TAPAN_A_MICB_CFILT_3_VAL__POR (0x80)
+#define TAPAN_A_MICB_CFILT_3_PRECHRG (0x136)
+#define TAPAN_A_MICB_CFILT_3_PRECHRG__POR (0x00)
+#define TAPAN_A_MICB_3_CTL (0x137)
+#define TAPAN_A_MICB_3_CTL__POR (0x02)
+#define TAPAN_A_MICB_3_INT_RBIAS (0x138)
+#define TAPAN_A_MICB_3_INT_RBIAS__POR (0x24)
+#define TAPAN_A_MICB_3_MBHC (0x139)
+#define TAPAN_A_MICB_3_MBHC__POR (0x00)
+#define TAPAN_A_MBHC_INSERT_DETECT (0x14A)
+#define TAPAN_A_MBHC_INSERT_DETECT__POR (0x00)
+#define TAPAN_A_MBHC_INSERT_DET_STATUS (0x14B)
+#define TAPAN_A_MBHC_INSERT_DET_STATUS__POR (0x00)
+#define TAPAN_A_TX_COM_BIAS (0x14C)
+#define TAPAN_A_TX_COM_BIAS__POR (0xF0)
+#define TAPAN_A_MBHC_SCALING_MUX_1 (0x14E)
+#define TAPAN_A_MBHC_SCALING_MUX_1__POR (0x00)
+#define TAPAN_A_MBHC_SCALING_MUX_2 (0x14F)
+#define TAPAN_A_MBHC_SCALING_MUX_2__POR (0x80)
+#define TAPAN_A_RESERVED_MAD_ANA_CTRL (0x150)
+#define TAPAN_A_RESERVED_MAD_ANA_CTRL__POR (0xF1)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_1 (0x151)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_1__POR (0x00)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_2 (0x152)
+#define TAPAN_A_TX_SUP_SWITCH_CTRL_2__POR (0x80)
+#define TAPAN_A_TX_1_EN (0x153)
+#define TAPAN_A_TX_1_EN__POR (0x02)
+#define TAPAN_A_TX_2_EN (0x154)
+#define TAPAN_A_TX_2_EN__POR (0x02)
+#define TAPAN_A_TX_1_2_ADC_CH1 (0x155)
+#define TAPAN_A_TX_1_2_ADC_CH1__POR (0x44)
+#define TAPAN_A_TX_1_2_ADC_CH2 (0x156)
+#define TAPAN_A_TX_1_2_ADC_CH2__POR (0x44)
+#define TAPAN_A_TX_1_2_ATEST_REFCTRL (0x157)
+#define TAPAN_A_TX_1_2_ATEST_REFCTRL__POR (0x00)
+#define TAPAN_A_TX_1_2_TEST_CTL (0x158)
+#define TAPAN_A_TX_1_2_TEST_CTL__POR (0x38)
+#define TAPAN_A_TX_1_2_TEST_BLOCK_EN (0x159)
+#define TAPAN_A_TX_1_2_TEST_BLOCK_EN__POR (0xFC)
+#define TAPAN_A_TX_1_2_TXFE_CLKDIV (0x15A)
+#define TAPAN_A_TX_1_2_TXFE_CLKDIV__POR (0x55)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH1 (0x15B)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH1__POR (0x00)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH2 (0x15C)
+#define TAPAN_A_TX_1_2_SAR_ERR_CH2__POR (0x00)
+#define TAPAN_A_TX_3_EN (0x15D)
+#define TAPAN_A_TX_3_EN__POR (0x00)
+#define TAPAN_A_TX_1_2_TEST_EN (0x15E)
+#define TAPAN_A_TX_1_2_TEST_EN__POR (0xCC)
+#define TAPAN_A_TX_4_5_TXFE_SC_CTL (0x15F)
+#define TAPAN_A_TX_4_5_TXFE_SC_CTL__POR (0x00)
+#define TAPAN_A_TX_4_5_TEST_EN (0x160)
+#define TAPAN_A_TX_4_5_TEST_EN__POR (0xCC)
+#define TAPAN_A_TX_4_EN (0x167)
+#define TAPAN_A_TX_4_EN__POR (0x02)
+#define TAPAN_A_TX_5_EN (0x168)
+#define TAPAN_A_TX_5_EN__POR (0x02)
+#define TAPAN_A_TX_4_5_ADC_CH4 (0x169)
+#define TAPAN_A_TX_4_5_ADC_CH4__POR (0x44)
+#define TAPAN_A_TX_4_5_ADC_CH5 (0x16A)
+#define TAPAN_A_TX_4_5_ADC_CH5__POR (0x44)
+#define TAPAN_A_TX_4_5_ATEST_REFCTRL (0x16B)
+#define TAPAN_A_TX_4_5_ATEST_REFCTRL__POR (0x00)
+#define TAPAN_A_TX_4_5_TEST_CTL (0x16C)
+#define TAPAN_A_TX_4_5_TEST_CTL__POR (0x38)
+#define TAPAN_A_TX_4_5_TEST_BLOCK_EN (0x16D)
+#define TAPAN_A_TX_4_5_TEST_BLOCK_EN__POR (0xFC)
+#define TAPAN_A_TX_4_5_TXFE_CKDIV (0x16E)
+#define TAPAN_A_TX_4_5_TXFE_CKDIV__POR (0x55)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH4 (0x16F)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH4__POR (0x00)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH5 (0x170)
+#define TAPAN_A_TX_4_5_SAR_ERR_CH5__POR (0x00)
+#define TAPAN_A_TX_7_MBHC_EN (0x171)
+#define TAPAN_A_TX_7_MBHC_EN__POR (0x0C)
+#define TAPAN_A_TX_7_MBHC_ATEST_REFCTRL (0x172)
+#define TAPAN_A_TX_7_MBHC_ATEST_REFCTRL__POR (0x00)
+#define TAPAN_A_TX_7_MBHC_ADC (0x173)
+#define TAPAN_A_TX_7_MBHC_ADC__POR (0x44)
+#define TAPAN_A_TX_7_MBHC_TEST_CTL (0x174)
+#define TAPAN_A_TX_7_MBHC_TEST_CTL__POR (0x38)
+#define TAPAN_A_TX_7_MBHC_SAR_ERR (0x175)
+#define TAPAN_A_TX_7_MBHC_SAR_ERR__POR (0x00)
+#define TAPAN_A_TX_7_TXFE_CLKDIV (0x176)
+#define TAPAN_A_TX_7_TXFE_CLKDIV__POR (0x0B)
+#define TAPAN_A_BUCK_MODE_1 (0x181)
+#define TAPAN_A_BUCK_MODE_1__POR (0x21)
+#define TAPAN_A_BUCK_MODE_2 (0x182)
+#define TAPAN_A_BUCK_MODE_2__POR (0xFF)
+#define TAPAN_A_BUCK_MODE_3 (0x183)
+#define TAPAN_A_BUCK_MODE_3__POR (0xCE)
+#define TAPAN_A_BUCK_MODE_4 (0x184)
+#define TAPAN_A_BUCK_MODE_4__POR (0x3A)
+#define TAPAN_A_BUCK_MODE_5 (0x185)
+#define TAPAN_A_BUCK_MODE_5__POR (0x00)
+#define TAPAN_A_BUCK_CTRL_VCL_1 (0x186)
+#define TAPAN_A_BUCK_CTRL_VCL_1__POR (0x08)
+#define TAPAN_A_BUCK_CTRL_VCL_2 (0x187)
+#define TAPAN_A_BUCK_CTRL_VCL_2__POR (0xA3)
+#define TAPAN_A_BUCK_CTRL_VCL_3 (0x188)
+#define TAPAN_A_BUCK_CTRL_VCL_3__POR (0x82)
+#define TAPAN_A_BUCK_CTRL_CCL_1 (0x189)
+#define TAPAN_A_BUCK_CTRL_CCL_1__POR (0x5B)
+#define TAPAN_A_BUCK_CTRL_CCL_2 (0x18A)
+#define TAPAN_A_BUCK_CTRL_CCL_2__POR (0xDC)
+#define TAPAN_A_BUCK_CTRL_CCL_3 (0x18B)
+#define TAPAN_A_BUCK_CTRL_CCL_3__POR (0x6A)
+#define TAPAN_A_BUCK_CTRL_CCL_4 (0x18C)
+#define TAPAN_A_BUCK_CTRL_CCL_4__POR (0x50)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_1 (0x18D)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_2 (0x18E)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_3 (0x18F)
+#define TAPAN_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77)
+#define TAPAN_A_BUCK_TMUX_A_D (0x190)
+#define TAPAN_A_BUCK_TMUX_A_D__POR (0x00)
+#define TAPAN_A_NCP_BUCKREF (0x191)
+#define TAPAN_A_NCP_BUCKREF__POR (0x00)
+#define TAPAN_A_NCP_EN (0x192)
+#define TAPAN_A_NCP_EN__POR (0xFE)
+#define TAPAN_A_NCP_CLK (0x193)
+#define TAPAN_A_NCP_CLK__POR (0x94)
+#define TAPAN_A_NCP_STATIC (0x194)
+#define TAPAN_A_NCP_STATIC__POR (0x28)
+#define TAPAN_A_NCP_VTH_LOW (0x195)
+#define TAPAN_A_NCP_VTH_LOW__POR (0x88)
+#define TAPAN_A_NCP_VTH_HIGH (0x196)
+#define TAPAN_A_NCP_VTH_HIGH__POR (0xA0)
+#define TAPAN_A_NCP_ATEST (0x197)
+#define TAPAN_A_NCP_ATEST__POR (0x00)
+#define TAPAN_A_NCP_DTEST (0x198)
+#define TAPAN_A_NCP_DTEST__POR (0x10)
+#define TAPAN_A_NCP_DLY1 (0x199)
+#define TAPAN_A_NCP_DLY1__POR (0x06)
+#define TAPAN_A_NCP_DLY2 (0x19A)
+#define TAPAN_A_NCP_DLY2__POR (0x06)
+#define TAPAN_A_RX_AUX_SW_CTL (0x19B)
+#define TAPAN_A_RX_AUX_SW_CTL__POR (0x00)
+#define TAPAN_A_RX_PA_AUX_IN_CONN (0x19C)
+#define TAPAN_A_RX_PA_AUX_IN_CONN__POR (0x00)
+#define TAPAN_A_RX_COM_TIMER_DIV (0x19E)
+#define TAPAN_A_RX_COM_TIMER_DIV__POR (0xE8)
+#define TAPAN_A_RX_COM_OCP_CTL (0x19F)
+#define TAPAN_A_RX_COM_OCP_CTL__POR (0x1F)
+#define TAPAN_A_RX_COM_OCP_COUNT (0x1A0)
+#define TAPAN_A_RX_COM_OCP_COUNT__POR (0x77)
+#define TAPAN_A_RX_COM_DAC_CTL (0x1A1)
+#define TAPAN_A_RX_COM_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_COM_BIAS (0x1A2)
+#define TAPAN_A_RX_COM_BIAS__POR (0x00)
+#define TAPAN_A_RX_HPH_AUTO_CHOP (0x1A4)
+#define TAPAN_A_RX_HPH_AUTO_CHOP__POR (0x38)
+#define TAPAN_A_RX_HPH_CHOP_CTL (0x1A5)
+#define TAPAN_A_RX_HPH_CHOP_CTL__POR (0xA4)
+#define TAPAN_A_RX_HPH_BIAS_PA (0x1A6)
+#define TAPAN_A_RX_HPH_BIAS_PA__POR (0x7A)
+#define TAPAN_A_RX_HPH_BIAS_LDO (0x1A7)
+#define TAPAN_A_RX_HPH_BIAS_LDO__POR (0x87)
+#define TAPAN_A_RX_HPH_BIAS_CNP (0x1A8)
+#define TAPAN_A_RX_HPH_BIAS_CNP__POR (0x8A)
+#define TAPAN_A_RX_HPH_BIAS_WG_OCP (0x1A9)
+#define TAPAN_A_RX_HPH_BIAS_WG_OCP__POR (0x2A)
+#define TAPAN_A_RX_HPH_OCP_CTL (0x1AA)
+#define TAPAN_A_RX_HPH_OCP_CTL__POR (0x69)
+#define TAPAN_A_RX_HPH_CNP_EN (0x1AB)
+#define TAPAN_A_RX_HPH_CNP_EN__POR (0x80)
+#define TAPAN_A_RX_HPH_CNP_WG_CTL (0x1AC)
+#define TAPAN_A_RX_HPH_CNP_WG_CTL__POR (0xDE)
+#define TAPAN_A_RX_HPH_CNP_WG_TIME (0x1AD)
+#define TAPAN_A_RX_HPH_CNP_WG_TIME__POR (0x15)
+#define TAPAN_A_RX_HPH_L_GAIN (0x1AE)
+#define TAPAN_A_RX_HPH_L_GAIN__POR (0x00)
+#define TAPAN_A_RX_HPH_L_TEST (0x1AF)
+#define TAPAN_A_RX_HPH_L_TEST__POR (0x00)
+#define TAPAN_A_RX_HPH_L_PA_CTL (0x1B0)
+#define TAPAN_A_RX_HPH_L_PA_CTL__POR (0x40)
+#define TAPAN_A_RX_HPH_L_DAC_CTL (0x1B1)
+#define TAPAN_A_RX_HPH_L_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_HPH_L_ATEST (0x1B2)
+#define TAPAN_A_RX_HPH_L_ATEST__POR (0x00)
+#define TAPAN_A_RX_HPH_L_STATUS (0x1B3)
+#define TAPAN_A_RX_HPH_L_STATUS__POR (0x00)
+#define TAPAN_A_RX_HPH_R_GAIN (0x1B4)
+#define TAPAN_A_RX_HPH_R_GAIN__POR (0x00)
+#define TAPAN_A_RX_HPH_R_TEST (0x1B5)
+#define TAPAN_A_RX_HPH_R_TEST__POR (0x00)
+#define TAPAN_A_RX_HPH_R_PA_CTL (0x1B6)
+#define TAPAN_A_RX_HPH_R_PA_CTL__POR (0x40)
+#define TAPAN_A_RX_HPH_R_DAC_CTL (0x1B7)
+#define TAPAN_A_RX_HPH_R_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_HPH_R_ATEST (0x1B8)
+#define TAPAN_A_RX_HPH_R_ATEST__POR (0x00)
+#define TAPAN_A_RX_HPH_R_STATUS (0x1B9)
+#define TAPAN_A_RX_HPH_R_STATUS__POR (0x00)
+#define TAPAN_A_RX_EAR_BIAS_PA (0x1BA)
+#define TAPAN_A_RX_EAR_BIAS_PA__POR (0x76)
+#define TAPAN_A_RX_EAR_BIAS_CMBUFF (0x1BB)
+#define TAPAN_A_RX_EAR_BIAS_CMBUFF__POR (0xA0)
+#define TAPAN_A_RX_EAR_EN (0x1BC)
+#define TAPAN_A_RX_EAR_EN__POR (0x00)
+#define TAPAN_A_RX_EAR_GAIN (0x1BD)
+#define TAPAN_A_RX_EAR_GAIN__POR (0x02)
+#define TAPAN_A_RX_EAR_CMBUFF (0x1BE)
+#define TAPAN_A_RX_EAR_CMBUFF__POR (0x05)
+#define TAPAN_A_RX_EAR_ICTL (0x1BF)
+#define TAPAN_A_RX_EAR_ICTL__POR (0x40)
+#define TAPAN_A_RX_EAR_CCOMP (0x1C0)
+#define TAPAN_A_RX_EAR_CCOMP__POR (0x08)
+#define TAPAN_A_RX_EAR_VCM (0x1C1)
+#define TAPAN_A_RX_EAR_VCM__POR (0x03)
+#define TAPAN_A_RX_EAR_CNP (0x1C2)
+#define TAPAN_A_RX_EAR_CNP__POR (0xF2)
+#define TAPAN_A_RX_EAR_DAC_CTL_ATEST (0x1C3)
+#define TAPAN_A_RX_EAR_DAC_CTL_ATEST__POR (0x00)
+#define TAPAN_A_RX_EAR_STATUS (0x1C5)
+#define TAPAN_A_RX_EAR_STATUS__POR (0x04)
+#define TAPAN_A_RX_LINE_BIAS_PA (0x1C6)
+#define TAPAN_A_RX_LINE_BIAS_PA__POR (0x78)
+#define TAPAN_A_RX_BUCK_BIAS1 (0x1C7)
+#define TAPAN_A_RX_BUCK_BIAS1__POR (0x42)
+#define TAPAN_A_RX_BUCK_BIAS2 (0x1C8)
+#define TAPAN_A_RX_BUCK_BIAS2__POR (0x84)
+#define TAPAN_A_RX_LINE_COM (0x1C9)
+#define TAPAN_A_RX_LINE_COM__POR (0x80)
+#define TAPAN_A_RX_LINE_CNP_EN (0x1CA)
+#define TAPAN_A_RX_LINE_CNP_EN__POR (0x00)
+#define TAPAN_A_RX_LINE_CNP_WG_CTL (0x1CB)
+#define TAPAN_A_RX_LINE_CNP_WG_CTL__POR (0x00)
+#define TAPAN_A_RX_LINE_CNP_WG_TIME (0x1CC)
+#define TAPAN_A_RX_LINE_CNP_WG_TIME__POR (0x04)
+#define TAPAN_A_RX_LINE_1_GAIN (0x1CD)
+#define TAPAN_A_RX_LINE_1_GAIN__POR (0x00)
+#define TAPAN_A_RX_LINE_1_TEST (0x1CE)
+#define TAPAN_A_RX_LINE_1_TEST__POR (0x00)
+#define TAPAN_A_RX_LINE_1_DAC_CTL (0x1CF)
+#define TAPAN_A_RX_LINE_1_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_LINE_1_STATUS (0x1D0)
+#define TAPAN_A_RX_LINE_1_STATUS__POR (0x00)
+#define TAPAN_A_RX_LINE_2_GAIN (0x1D1)
+#define TAPAN_A_RX_LINE_2_GAIN__POR (0x00)
+#define TAPAN_A_RX_LINE_2_TEST (0x1D2)
+#define TAPAN_A_RX_LINE_2_TEST__POR (0x00)
+#define TAPAN_A_RX_LINE_2_DAC_CTL (0x1D3)
+#define TAPAN_A_RX_LINE_2_DAC_CTL__POR (0x00)
+#define TAPAN_A_RX_LINE_2_STATUS (0x1D4)
+#define TAPAN_A_RX_LINE_2_STATUS__POR (0x00)
+#define TAPAN_A_RX_LINE_CNP_DBG (0x1DD)
+#define TAPAN_A_RX_LINE_CNP_DBG__POR (0x00)
+#define TAPAN_A_SPKR_DRV_EN (0x1DF)
+#define TAPAN_A_SPKR_DRV_EN__POR (0x6F)
+#define TAPAN_A_SPKR_DRV_GAIN (0x1E0)
+#define TAPAN_A_SPKR_DRV_GAIN__POR (0x00)
+#define TAPAN_A_SPKR_DRV_DAC_CTL (0x1E1)
+#define TAPAN_A_SPKR_DRV_DAC_CTL__POR (0x04)
+#define TAPAN_A_SPKR_DRV_OCP_CTL (0x1E2)
+#define TAPAN_A_SPKR_DRV_OCP_CTL__POR (0x98)
+#define TAPAN_A_SPKR_DRV_CLIP_DET (0x1E3)
+#define TAPAN_A_SPKR_DRV_CLIP_DET__POR (0x48)
+#define TAPAN_A_SPKR_DRV_IEC (0x1E4)
+#define TAPAN_A_SPKR_DRV_IEC__POR (0x28)
+#define TAPAN_A_SPKR_DRV_DBG_DAC (0x1E5)
+#define TAPAN_A_SPKR_DRV_DBG_DAC__POR (0x05)
+#define TAPAN_A_SPKR_DRV_DBG_PA (0x1E6)
+#define TAPAN_A_SPKR_DRV_DBG_PA__POR (0x18)
+#define TAPAN_A_SPKR_DRV_DBG_PWRSTG (0x1E7)
+#define TAPAN_A_SPKR_DRV_DBG_PWRSTG__POR (0x00)
+#define TAPAN_A_SPKR_DRV_BIAS_LDO (0x1E8)
+#define TAPAN_A_SPKR_DRV_BIAS_LDO__POR (0x45)
+#define TAPAN_A_SPKR_DRV_BIAS_INT (0x1E9)
+#define TAPAN_A_SPKR_DRV_BIAS_INT__POR (0xA5)
+#define TAPAN_A_SPKR_DRV_BIAS_PA (0x1EA)
+#define TAPAN_A_SPKR_DRV_BIAS_PA__POR (0x55)
+#define TAPAN_A_SPKR_DRV_STATUS_OCP (0x1EB)
+#define TAPAN_A_SPKR_DRV_STATUS_OCP__POR (0x00)
+#define TAPAN_A_SPKR_DRV_STATUS_PA (0x1EC)
+#define TAPAN_A_SPKR_DRV_STATUS_PA__POR (0x00)
+#define TAPAN_A_RC_OSC_FREQ (0x1FA)
+#define TAPAN_A_RC_OSC_FREQ__POR (0x46)
+#define TAPAN_A_RC_OSC_TEST (0x1FB)
+#define TAPAN_A_RC_OSC_TEST__POR (0x0A)
+#define TAPAN_A_RC_OSC_STATUS (0x1FC)
+#define TAPAN_A_RC_OSC_STATUS__POR (0x18)
+#define TAPAN_A_RC_OSC_TUNER (0x1FD)
+#define TAPAN_A_RC_OSC_TUNER__POR (0x00)
+#define TAPAN_A_MBHC_HPH (0x1FE)
+#define TAPAN_A_MBHC_HPH__POR (0x44)
+#define TAPAN_A_CDC_ANC1_B1_CTL (0x200)
+#define TAPAN_A_CDC_ANC1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_B1_CTL (0x280)
+#define TAPAN_A_CDC_ANC2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_SHIFT (0x201)
+#define TAPAN_A_CDC_ANC1_SHIFT__POR (0x00)
+#define TAPAN_A_CDC_ANC2_SHIFT (0x281)
+#define TAPAN_A_CDC_ANC2_SHIFT__POR (0x00)
+#define TAPAN_A_CDC_ANC1_IIR_B1_CTL (0x202)
+#define TAPAN_A_CDC_ANC1_IIR_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_IIR_B1_CTL (0x282)
+#define TAPAN_A_CDC_ANC2_IIR_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_IIR_B2_CTL (0x203)
+#define TAPAN_A_CDC_ANC1_IIR_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_IIR_B2_CTL (0x283)
+#define TAPAN_A_CDC_ANC2_IIR_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_IIR_B3_CTL (0x204)
+#define TAPAN_A_CDC_ANC1_IIR_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_IIR_B3_CTL (0x284)
+#define TAPAN_A_CDC_ANC2_IIR_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_LPF_B1_CTL (0x206)
+#define TAPAN_A_CDC_ANC1_LPF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_LPF_B1_CTL (0x286)
+#define TAPAN_A_CDC_ANC2_LPF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_LPF_B2_CTL (0x207)
+#define TAPAN_A_CDC_ANC1_LPF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_LPF_B2_CTL (0x287)
+#define TAPAN_A_CDC_ANC2_LPF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_SPARE (0x209)
+#define TAPAN_A_CDC_ANC1_SPARE__POR (0x00)
+#define TAPAN_A_CDC_ANC2_SPARE (0x289)
+#define TAPAN_A_CDC_ANC2_SPARE__POR (0x00)
+#define TAPAN_A_CDC_ANC1_SMLPF_CTL (0x20A)
+#define TAPAN_A_CDC_ANC1_SMLPF_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_SMLPF_CTL (0x28A)
+#define TAPAN_A_CDC_ANC2_SMLPF_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_DCFLT_CTL (0x20B)
+#define TAPAN_A_CDC_ANC1_DCFLT_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_DCFLT_CTL (0x28B)
+#define TAPAN_A_CDC_ANC2_DCFLT_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_GAIN_CTL (0x20C)
+#define TAPAN_A_CDC_ANC1_GAIN_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_GAIN_CTL (0x28C)
+#define TAPAN_A_CDC_ANC2_GAIN_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC1_B2_CTL (0x20D)
+#define TAPAN_A_CDC_ANC1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_ANC2_B2_CTL (0x28D)
+#define TAPAN_A_CDC_ANC2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX1_VOL_CTL_TIMER (0x220)
+#define TAPAN_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX2_VOL_CTL_TIMER (0x228)
+#define TAPAN_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX3_VOL_CTL_TIMER (0x230)
+#define TAPAN_A_CDC_TX3_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX4_VOL_CTL_TIMER (0x238)
+#define TAPAN_A_CDC_TX4_VOL_CTL_TIMER__POR (0x00)
+#define TAPAN_A_CDC_TX1_VOL_CTL_GAIN (0x221)
+#define TAPAN_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX2_VOL_CTL_GAIN (0x229)
+#define TAPAN_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX3_VOL_CTL_GAIN (0x231)
+#define TAPAN_A_CDC_TX3_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX4_VOL_CTL_GAIN (0x239)
+#define TAPAN_A_CDC_TX4_VOL_CTL_GAIN__POR (0x00)
+#define TAPAN_A_CDC_TX1_VOL_CTL_CFG (0x222)
+#define TAPAN_A_CDC_TX1_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX2_VOL_CTL_CFG (0x22A)
+#define TAPAN_A_CDC_TX2_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX3_VOL_CTL_CFG (0x232)
+#define TAPAN_A_CDC_TX3_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX4_VOL_CTL_CFG (0x23A)
+#define TAPAN_A_CDC_TX4_VOL_CTL_CFG__POR (0x00)
+#define TAPAN_A_CDC_TX1_MUX_CTL (0x223)
+#define TAPAN_A_CDC_TX1_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX2_MUX_CTL (0x22B)
+#define TAPAN_A_CDC_TX2_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX3_MUX_CTL (0x233)
+#define TAPAN_A_CDC_TX3_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX4_MUX_CTL (0x23B)
+#define TAPAN_A_CDC_TX4_MUX_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX1_CLK_FS_CTL (0x224)
+#define TAPAN_A_CDC_TX1_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX2_CLK_FS_CTL (0x22C)
+#define TAPAN_A_CDC_TX2_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX3_CLK_FS_CTL (0x234)
+#define TAPAN_A_CDC_TX3_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX4_CLK_FS_CTL (0x23C)
+#define TAPAN_A_CDC_TX4_CLK_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX1_DMIC_CTL (0x225)
+#define TAPAN_A_CDC_TX1_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX2_DMIC_CTL (0x22D)
+#define TAPAN_A_CDC_TX2_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX3_DMIC_CTL (0x235)
+#define TAPAN_A_CDC_TX3_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_TX4_DMIC_CTL (0x23D)
+#define TAPAN_A_CDC_TX4_DMIC_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B1_CTL (0x278)
+#define TAPAN_A_CDC_DEBUG_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B2_CTL (0x279)
+#define TAPAN_A_CDC_DEBUG_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B3_CTL (0x27A)
+#define TAPAN_A_CDC_DEBUG_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B4_CTL (0x27B)
+#define TAPAN_A_CDC_DEBUG_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B5_CTL (0x27C)
+#define TAPAN_A_CDC_DEBUG_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B6_CTL (0x27D)
+#define TAPAN_A_CDC_DEBUG_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_DEBUG_B7_CTL (0x27E)
+#define TAPAN_A_CDC_DEBUG_B7_CTL__POR (0x00)
+#define TAPAN_A_CDC_SRC1_PDA_CFG (0x2A0)
+#define TAPAN_A_CDC_SRC1_PDA_CFG__POR (0x00)
+#define TAPAN_A_CDC_SRC2_PDA_CFG (0x2A8)
+#define TAPAN_A_CDC_SRC2_PDA_CFG__POR (0x00)
+#define TAPAN_A_CDC_SRC1_FS_CTL (0x2A1)
+#define TAPAN_A_CDC_SRC1_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_SRC2_FS_CTL (0x2A9)
+#define TAPAN_A_CDC_SRC2_FS_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B1_CTL (0x2B0)
+#define TAPAN_A_CDC_RX1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B1_CTL (0x2B8)
+#define TAPAN_A_CDC_RX2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B1_CTL (0x2C0)
+#define TAPAN_A_CDC_RX3_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B1_CTL (0x2C8)
+#define TAPAN_A_CDC_RX4_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B2_CTL (0x2B1)
+#define TAPAN_A_CDC_RX1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B2_CTL (0x2B9)
+#define TAPAN_A_CDC_RX2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B2_CTL (0x2C1)
+#define TAPAN_A_CDC_RX3_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B2_CTL (0x2C9)
+#define TAPAN_A_CDC_RX4_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B3_CTL (0x2B2)
+#define TAPAN_A_CDC_RX1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B3_CTL (0x2BA)
+#define TAPAN_A_CDC_RX2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B3_CTL (0x2C2)
+#define TAPAN_A_CDC_RX3_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B3_CTL (0x2CA)
+#define TAPAN_A_CDC_RX4_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B4_CTL (0x2B3)
+#define TAPAN_A_CDC_RX1_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B4_CTL (0x2BB)
+#define TAPAN_A_CDC_RX2_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B4_CTL (0x2C3)
+#define TAPAN_A_CDC_RX3_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B4_CTL (0x2CB)
+#define TAPAN_A_CDC_RX4_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B5_CTL (0x2B4)
+#define TAPAN_A_CDC_RX1_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B5_CTL (0x2BC)
+#define TAPAN_A_CDC_RX2_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B5_CTL (0x2C4)
+#define TAPAN_A_CDC_RX3_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B5_CTL (0x2CC)
+#define TAPAN_A_CDC_RX4_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_B6_CTL (0x2B5)
+#define TAPAN_A_CDC_RX1_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_B6_CTL (0x2BD)
+#define TAPAN_A_CDC_RX2_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_B6_CTL (0x2C5)
+#define TAPAN_A_CDC_RX3_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_B6_CTL (0x2CD)
+#define TAPAN_A_CDC_RX4_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL (0x2BE)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL (0x2C6)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL (0x2CE)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7)
+#define TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL (0x2BF)
+#define TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL (0x2C7)
+#define TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL (0x2CF)
+#define TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_ANC_RESET_CTL (0x300)
+#define TAPAN_A_CDC_CLK_ANC_RESET_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RX_RESET_CTL (0x301)
+#define TAPAN_A_CDC_CLK_RX_RESET_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_RESET_B1_CTL (0x302)
+#define TAPAN_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_RESET_B2_CTL (0x303)
+#define TAPAN_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_DMIC_B1_CTL (0x304)
+#define TAPAN_A_CDC_CLK_DMIC_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_DMIC_B2_CTL (0x305)
+#define TAPAN_A_CDC_CLK_DMIC_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_I2S_CTL (0x306)
+#define TAPAN_A_CDC_CLK_I2S_CTL__POR (0x03)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL (0x308)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL (0x309)
+#define TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x30A)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL (0x30B)
+#define TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_OTHR_CTL (0x30C)
+#define TAPAN_A_CDC_CLK_OTHR_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30D)
+#define TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL (0x30E)
+#define TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RX_B1_CTL (0x30F)
+#define TAPAN_A_CDC_CLK_RX_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_RX_B2_CTL (0x310)
+#define TAPAN_A_CDC_CLK_RX_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_MCLK_CTL (0x311)
+#define TAPAN_A_CDC_CLK_MCLK_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_PDM_CTL (0x312)
+#define TAPAN_A_CDC_CLK_PDM_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_SD_CTL (0x313)
+#define TAPAN_A_CDC_CLK_SD_CTL__POR (0x00)
+#define TAPAN_A_CDC_CLK_POWER_CTL (0x314)
+#define TAPAN_A_CDC_CLK_POWER_CTL__POR (0x03)
+#define TAPAN_A_CDC_CLSH_B1_CTL (0x320)
+#define TAPAN_A_CDC_CLSH_B1_CTL__POR (0x22)
+#define TAPAN_A_CDC_CLSH_B2_CTL (0x321)
+#define TAPAN_A_CDC_CLSH_B2_CTL__POR (0x35)
+#define TAPAN_A_CDC_CLSH_B3_CTL (0x322)
+#define TAPAN_A_CDC_CLSH_B3_CTL__POR (0x3B)
+#define TAPAN_A_CDC_CLSH_BUCK_NCP_VARS (0x323)
+#define TAPAN_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x04)
+#define TAPAN_A_CDC_CLSH_IDLE_HPH_THSD (0x324)
+#define TAPAN_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12)
+#define TAPAN_A_CDC_CLSH_IDLE_EAR_THSD (0x325)
+#define TAPAN_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327)
+#define TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23)
+#define TAPAN_A_CDC_CLSH_K_ADDR (0x328)
+#define TAPAN_A_CDC_CLSH_K_ADDR__POR (0x00)
+#define TAPAN_A_CDC_CLSH_K_DATA (0x329)
+#define TAPAN_A_CDC_CLSH_K_DATA__POR (0xA4)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D)
+#define TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_EAR (0x32E)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_EAR__POR (0x0D)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_HPH (0x32F)
+#define TAPAN_A_CDC_CLSH_V_PA_HD_HPH__POR (0x0D)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_EAR (0x330)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x3A)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_HPH (0x331)
+#define TAPAN_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x1D)
+#define TAPAN_A_CDC_IIR1_GAIN_B1_CTL (0x340)
+#define TAPAN_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B1_CTL (0x350)
+#define TAPAN_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B2_CTL (0x341)
+#define TAPAN_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B2_CTL (0x351)
+#define TAPAN_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B3_CTL (0x342)
+#define TAPAN_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B3_CTL (0x352)
+#define TAPAN_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B4_CTL (0x343)
+#define TAPAN_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B4_CTL (0x353)
+#define TAPAN_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B5_CTL (0x344)
+#define TAPAN_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B5_CTL (0x354)
+#define TAPAN_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B6_CTL (0x345)
+#define TAPAN_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B6_CTL (0x355)
+#define TAPAN_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B7_CTL (0x346)
+#define TAPAN_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B7_CTL (0x356)
+#define TAPAN_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_B8_CTL (0x347)
+#define TAPAN_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_B8_CTL (0x357)
+#define TAPAN_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_CTL (0x348)
+#define TAPAN_A_CDC_IIR1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_CTL (0x358)
+#define TAPAN_A_CDC_IIR2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL (0x349)
+#define TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL (0x359)
+#define TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_COEF_B1_CTL (0x34A)
+#define TAPAN_A_CDC_IIR1_COEF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_COEF_B1_CTL (0x35A)
+#define TAPAN_A_CDC_IIR2_COEF_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR1_COEF_B2_CTL (0x34B)
+#define TAPAN_A_CDC_IIR1_COEF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_IIR2_COEF_B2_CTL (0x35B)
+#define TAPAN_A_CDC_IIR2_COEF_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_TOP_GAIN_UPDATE (0x360)
+#define TAPAN_A_CDC_TOP_GAIN_UPDATE__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B1_CTL (0x368)
+#define TAPAN_A_CDC_COMP0_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B1_CTL (0x370)
+#define TAPAN_A_CDC_COMP1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B1_CTL (0x378)
+#define TAPAN_A_CDC_COMP2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B2_CTL (0x369)
+#define TAPAN_A_CDC_COMP0_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B2_CTL (0x371)
+#define TAPAN_A_CDC_COMP1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B2_CTL (0x379)
+#define TAPAN_A_CDC_COMP2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B3_CTL (0x36A)
+#define TAPAN_A_CDC_COMP0_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B3_CTL (0x372)
+#define TAPAN_A_CDC_COMP1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B3_CTL (0x37A)
+#define TAPAN_A_CDC_COMP2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B4_CTL (0x36B)
+#define TAPAN_A_CDC_COMP0_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B4_CTL (0x373)
+#define TAPAN_A_CDC_COMP1_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B4_CTL (0x37B)
+#define TAPAN_A_CDC_COMP2_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B5_CTL (0x36C)
+#define TAPAN_A_CDC_COMP0_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B5_CTL (0x374)
+#define TAPAN_A_CDC_COMP1_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B5_CTL (0x37C)
+#define TAPAN_A_CDC_COMP2_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_B6_CTL (0x36D)
+#define TAPAN_A_CDC_COMP0_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP1_B6_CTL (0x375)
+#define TAPAN_A_CDC_COMP1_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP2_B6_CTL (0x37D)
+#define TAPAN_A_CDC_COMP2_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS (0x36E)
+#define TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS__POR (0x00)
+#define TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376)
+#define TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00)
+#define TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS (0x37E)
+#define TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS__POR (0x00)
+#define TAPAN_A_CDC_COMP0_FS_CFG (0x36F)
+#define TAPAN_A_CDC_COMP0_FS_CFG__POR (0x00)
+#define TAPAN_A_CDC_COMP1_FS_CFG (0x377)
+#define TAPAN_A_CDC_COMP1_FS_CFG__POR (0x00)
+#define TAPAN_A_CDC_COMP2_FS_CFG (0x37F)
+#define TAPAN_A_CDC_COMP2_FS_CFG__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX1_B1_CTL (0x380)
+#define TAPAN_A_CDC_CONN_RX1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX1_B2_CTL (0x381)
+#define TAPAN_A_CDC_CONN_RX1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX1_B3_CTL (0x382)
+#define TAPAN_A_CDC_CONN_RX1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX2_B1_CTL (0x383)
+#define TAPAN_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX2_B2_CTL (0x384)
+#define TAPAN_A_CDC_CONN_RX2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX2_B3_CTL (0x385)
+#define TAPAN_A_CDC_CONN_RX2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX3_B1_CTL (0x386)
+#define TAPAN_A_CDC_CONN_RX3_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX3_B2_CTL (0x387)
+#define TAPAN_A_CDC_CONN_RX3_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX4_B1_CTL (0x388)
+#define TAPAN_A_CDC_CONN_RX4_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX4_B2_CTL (0x389)
+#define TAPAN_A_CDC_CONN_RX4_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX4_B3_CTL (0x38A)
+#define TAPAN_A_CDC_CONN_RX4_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_ANC_B1_CTL (0x391)
+#define TAPAN_A_CDC_CONN_ANC_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_ANC_B2_CTL (0x392)
+#define TAPAN_A_CDC_CONN_ANC_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B1_CTL (0x393)
+#define TAPAN_A_CDC_CONN_TX_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B2_CTL (0x394)
+#define TAPAN_A_CDC_CONN_TX_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B3_CTL (0x395)
+#define TAPAN_A_CDC_CONN_TX_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_B4_CTL (0x396)
+#define TAPAN_A_CDC_CONN_TX_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B1_CTL (0x397)
+#define TAPAN_A_CDC_CONN_EQ1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B2_CTL (0x398)
+#define TAPAN_A_CDC_CONN_EQ1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B3_CTL (0x399)
+#define TAPAN_A_CDC_CONN_EQ1_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ1_B4_CTL (0x39A)
+#define TAPAN_A_CDC_CONN_EQ1_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B1_CTL (0x39B)
+#define TAPAN_A_CDC_CONN_EQ2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B2_CTL (0x39C)
+#define TAPAN_A_CDC_CONN_EQ2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B3_CTL (0x39D)
+#define TAPAN_A_CDC_CONN_EQ2_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_EQ2_B4_CTL (0x39E)
+#define TAPAN_A_CDC_CONN_EQ2_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC1_B1_CTL (0x39F)
+#define TAPAN_A_CDC_CONN_SRC1_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC1_B2_CTL (0x3A0)
+#define TAPAN_A_CDC_CONN_SRC1_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC2_B1_CTL (0x3A1)
+#define TAPAN_A_CDC_CONN_SRC2_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_SRC2_B2_CTL (0x3A2)
+#define TAPAN_A_CDC_CONN_SRC2_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B1_CTL (0x3A3)
+#define TAPAN_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B2_CTL (0x3A4)
+#define TAPAN_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B3_CTL (0x3A5)
+#define TAPAN_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B4_CTL (0x3A6)
+#define TAPAN_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B5_CTL (0x3A7)
+#define TAPAN_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_TX_SB_B11_CTL (0x3AD)
+#define TAPAN_A_CDC_CONN_TX_SB_B11_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX_SB_B1_CTL (0x3AE)
+#define TAPAN_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_RX_SB_B2_CTL (0x3AF)
+#define TAPAN_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_CLSH_CTL (0x3B0)
+#define TAPAN_A_CDC_CONN_CLSH_CTL__POR (0x00)
+#define TAPAN_A_CDC_CONN_MISC (0x3B1)
+#define TAPAN_A_CDC_CONN_MISC__POR (0x01)
+#define TAPAN_A_CDC_MBHC_EN_CTL (0x3C0)
+#define TAPAN_A_CDC_MBHC_EN_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_FIR_B1_CFG (0x3C1)
+#define TAPAN_A_CDC_MBHC_FIR_B1_CFG__POR (0x00)
+#define TAPAN_A_CDC_MBHC_FIR_B2_CFG (0x3C2)
+#define TAPAN_A_CDC_MBHC_FIR_B2_CFG__POR (0x06)
+#define TAPAN_A_CDC_MBHC_TIMER_B1_CTL (0x3C3)
+#define TAPAN_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03)
+#define TAPAN_A_CDC_MBHC_TIMER_B2_CTL (0x3C4)
+#define TAPAN_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09)
+#define TAPAN_A_CDC_MBHC_TIMER_B3_CTL (0x3C5)
+#define TAPAN_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E)
+#define TAPAN_A_CDC_MBHC_TIMER_B4_CTL (0x3C6)
+#define TAPAN_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45)
+#define TAPAN_A_CDC_MBHC_TIMER_B5_CTL (0x3C7)
+#define TAPAN_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04)
+#define TAPAN_A_CDC_MBHC_TIMER_B6_CTL (0x3C8)
+#define TAPAN_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78)
+#define TAPAN_A_CDC_MBHC_B1_STATUS (0x3C9)
+#define TAPAN_A_CDC_MBHC_B1_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B2_STATUS (0x3CA)
+#define TAPAN_A_CDC_MBHC_B2_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B3_STATUS (0x3CB)
+#define TAPAN_A_CDC_MBHC_B3_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B4_STATUS (0x3CC)
+#define TAPAN_A_CDC_MBHC_B4_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B5_STATUS (0x3CD)
+#define TAPAN_A_CDC_MBHC_B5_STATUS__POR (0x00)
+#define TAPAN_A_CDC_MBHC_B1_CTL (0x3CE)
+#define TAPAN_A_CDC_MBHC_B1_CTL__POR (0xC0)
+#define TAPAN_A_CDC_MBHC_B2_CTL (0x3CF)
+#define TAPAN_A_CDC_MBHC_B2_CTL__POR (0x5D)
+#define TAPAN_A_CDC_MBHC_VOLT_B1_CTL (0x3D0)
+#define TAPAN_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B2_CTL (0x3D1)
+#define TAPAN_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B3_CTL (0x3D2)
+#define TAPAN_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B4_CTL (0x3D3)
+#define TAPAN_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B5_CTL (0x3D4)
+#define TAPAN_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B6_CTL (0x3D5)
+#define TAPAN_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B7_CTL (0x3D6)
+#define TAPAN_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF)
+#define TAPAN_A_CDC_MBHC_VOLT_B8_CTL (0x3D7)
+#define TAPAN_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07)
+#define TAPAN_A_CDC_MBHC_VOLT_B9_CTL (0x3D8)
+#define TAPAN_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF)
+#define TAPAN_A_CDC_MBHC_VOLT_B10_CTL (0x3D9)
+#define TAPAN_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F)
+#define TAPAN_A_CDC_MBHC_VOLT_B11_CTL (0x3DA)
+#define TAPAN_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_VOLT_B12_CTL (0x3DB)
+#define TAPAN_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80)
+#define TAPAN_A_CDC_MBHC_CLK_CTL (0x3DC)
+#define TAPAN_A_CDC_MBHC_CLK_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_INT_CTL (0x3DD)
+#define TAPAN_A_CDC_MBHC_INT_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_DEBUG_CTL (0x3DE)
+#define TAPAN_A_CDC_MBHC_DEBUG_CTL__POR (0x00)
+#define TAPAN_A_CDC_MBHC_SPARE (0x3DF)
+#define TAPAN_A_CDC_MBHC_SPARE__POR (0x00)
+
+
+/* SLIMBUS Slave Registers */
+#define TAPAN_SLIM_PGD_PORT_INT_EN0 (0x30)
+#define TAPAN_SLIM_PGD_PORT_INT_STATUS0 (0x34)
+#define TAPAN_SLIM_PGD_PORT_INT_CLR0 (0x38)
+#define TAPAN_SLIM_PGD_PORT_INT_SOURCE0 (0x60)
+
+/* Macros for Packing Register Writes into a U32 */
+#define TAPAN_PACKED_REG_SIZE sizeof(u32)
+
+#define TAPAN_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\
+ ((mask & 0xff) << 8)|((reg & 0xffff) << 16))
+
+#define TAPAN_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
+ do { \
+ ((reg) = ((packed >> 16) & (0xffff))); \
+ ((mask) = ((packed >> 8) & (0xff))); \
+ ((val) = ((packed) & (0xff))); \
+ } while (0);
+
+#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 1b46499..df34213 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -295,6 +295,9 @@
config SND_SOC_WCD9320
tristate
+config SND_SOC_WCD9306
+ tristate
+
config SND_SOC_WL1273
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 42121fe..11338aa 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -52,6 +52,7 @@
snd-soc-wcd9310-objs := wcd9310.o wcd9310-tables.o
snd-soc-cs8427-objs := cs8427.o
snd-soc-wcd9320-objs := wcd9xxx-resmgr.o wcd9320.o wcd9320-tables.o wcd9xxx-mbhc.o
+snd-soc-wcd9306-objs := wcd9xxx-resmgr.o wcd9306.o wcd9306-tables.o wcd9xxx-mbhc.o
snd-soc-wl1273-objs := wl1273.o
snd-soc-wm1250-ev1-objs := wm1250-ev1.o
snd-soc-wm2000-objs := wm2000.o
@@ -162,6 +163,7 @@
obj-$(CONFIG_SND_SOC_WCD9310) += snd-soc-wcd9310.o
obj-$(CONFIG_SND_SOC_CS8427) += snd-soc-cs8427.o
obj-$(CONFIG_SND_SOC_WCD9320) += snd-soc-wcd9320.o
+obj-$(CONFIG_SND_SOC_WCD9306) += snd-soc-wcd9306.o
obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o
obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o
diff --git a/sound/soc/codecs/wcd9306-tables.c b/sound/soc/codecs/wcd9306-tables.c
new file mode 100644
index 0000000..21c5636
--- /dev/null
+++ b/sound/soc/codecs/wcd9306-tables.c
@@ -0,0 +1,1015 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 and
+* only version 2 as published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include <linux/mfd/wcd9xxx/wcd9306_registers.h>
+#include "wcd9306.h"
+
+const u8 tapan_reg_readable[TAPAN_CACHE_SIZE] = {
+ [TAPAN_A_CHIP_CTL] = 1,
+ [TAPAN_A_CHIP_STATUS] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_0] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_1] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_2] = 1,
+ [TAPAN_A_CHIP_ID_BYTE_3] = 1,
+ [TAPAN_A_CHIP_VERSION] = 1,
+ [TAPAN_A_CHIP_DEBUG_CTL] = 1,
+ [TAPAN_A_SLAVE_ID_1] = 1,
+ [TAPAN_A_SLAVE_ID_2] = 1,
+ [TAPAN_A_SLAVE_ID_3] = 1,
+ [TAPAN_A_PIN_CTL_OE0] = 1,
+ [TAPAN_A_PIN_CTL_DATA0] = 1,
+ [TAPAN_A_HDRIVE_GENERIC] = 1,
+ [TAPAN_A_HDRIVE_OVERRIDE] = 1,
+ [TAPAN_A_ANA_CSR_WAIT_STATE] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL0] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL1] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL2] = 1,
+ [TAPAN_A_PROCESS_MONITOR_CTL3] = 1,
+ [TAPAN_A_QFUSE_CTL] = 1,
+ [TAPAN_A_QFUSE_STATUS] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT0] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT1] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT2] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT3] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT4] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT5] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT6] = 1,
+ [TAPAN_A_QFUSE_DATA_OUT7] = 1,
+ [TAPAN_A_CDC_CTL] = 1,
+ [TAPAN_A_LEAKAGE_CTL] = 1,
+ [TAPAN_A_INTR_MODE] = 1,
+ [TAPAN_A_INTR_MASK0] = 1,
+ [TAPAN_A_INTR_MASK1] = 1,
+ [TAPAN_A_INTR_MASK2] = 1,
+ [TAPAN_A_INTR_MASK3] = 1,
+ [TAPAN_A_INTR_STATUS0] = 1,
+ [TAPAN_A_INTR_STATUS1] = 1,
+ [TAPAN_A_INTR_STATUS2] = 1,
+ [TAPAN_A_INTR_STATUS3] = 1,
+ [TAPAN_A_INTR_CLEAR0] = 0,
+ [TAPAN_A_INTR_CLEAR1] = 0,
+ [TAPAN_A_INTR_CLEAR2] = 0,
+ [TAPAN_A_INTR_CLEAR3] = 0,
+ [TAPAN_A_INTR_LEVEL0] = 1,
+ [TAPAN_A_INTR_LEVEL1] = 1,
+ [TAPAN_A_INTR_LEVEL2] = 1,
+ [TAPAN_A_INTR_LEVEL3] = 1,
+ [TAPAN_A_INTR_TEST0] = 1,
+ [TAPAN_A_INTR_TEST1] = 1,
+ [TAPAN_A_INTR_TEST2] = 1,
+ [TAPAN_A_INTR_TEST3] = 1,
+ [TAPAN_A_INTR_SET0] = 1,
+ [TAPAN_A_INTR_SET1] = 1,
+ [TAPAN_A_INTR_SET2] = 1,
+ [TAPAN_A_INTR_SET3] = 1,
+ [TAPAN_A_INTR_DESTN0] = 1,
+ [TAPAN_A_INTR_DESTN1] = 1,
+ [TAPAN_A_INTR_DESTN2] = 1,
+ [TAPAN_A_INTR_DESTN3] = 1,
+ [TAPAN_A_CDC_DMIC_DATA0_MODE] = 1,
+ [TAPAN_A_CDC_DMIC_CLK0_MODE] = 1,
+ [TAPAN_A_CDC_DMIC_DATA1_MODE] = 1,
+ [TAPAN_A_CDC_DMIC_CLK1_MODE] = 1,
+ [TAPAN_A_CDC_INTR_MODE] = 1,
+ [TAPAN_A_BIAS_REF_CTL] = 1,
+ [TAPAN_A_BIAS_CENTRAL_BG_CTL] = 1,
+ [TAPAN_A_BIAS_PRECHRG_CTL] = 1,
+ [TAPAN_A_BIAS_CURR_CTL_1] = 1,
+ [TAPAN_A_BIAS_CURR_CTL_2] = 1,
+ [TAPAN_A_BIAS_OSC_BG_CTL] = 1,
+ [TAPAN_A_CLK_BUFF_EN1] = 1,
+ [TAPAN_A_CLK_BUFF_EN2] = 1,
+ [TAPAN_A_LDO_H_MODE_1] = 1,
+ [TAPAN_A_LDO_H_MODE_2] = 1,
+ [TAPAN_A_LDO_H_LOOP_CTL] = 1,
+ [TAPAN_A_LDO_H_COMP_1] = 1,
+ [TAPAN_A_LDO_H_COMP_2] = 1,
+ [TAPAN_A_LDO_H_BIAS_1] = 1,
+ [TAPAN_A_LDO_H_BIAS_2] = 1,
+ [TAPAN_A_LDO_H_BIAS_3] = 1,
+ [TAPAN_A_MICB_CFILT_1_CTL] = 1,
+ [TAPAN_A_MICB_CFILT_1_VAL] = 1,
+ [TAPAN_A_MICB_CFILT_1_PRECHRG] = 1,
+ [TAPAN_A_MICB_1_CTL] = 1,
+ [TAPAN_A_MICB_1_INT_RBIAS] = 1,
+ [TAPAN_A_MICB_1_MBHC] = 1,
+ [TAPAN_A_MICB_CFILT_2_CTL] = 1,
+ [TAPAN_A_MICB_CFILT_2_VAL] = 1,
+ [TAPAN_A_MICB_CFILT_2_PRECHRG] = 1,
+ [TAPAN_A_MICB_2_CTL] = 1,
+ [TAPAN_A_MICB_2_INT_RBIAS] = 1,
+ [TAPAN_A_MICB_2_MBHC] = 1,
+ [TAPAN_A_MICB_CFILT_3_CTL] = 1,
+ [TAPAN_A_MICB_CFILT_3_VAL] = 1,
+ [TAPAN_A_MICB_CFILT_3_PRECHRG] = 1,
+ [TAPAN_A_MICB_3_CTL] = 1,
+ [TAPAN_A_MICB_3_INT_RBIAS] = 1,
+ [TAPAN_A_MICB_3_MBHC] = 1,
+ [TAPAN_A_MBHC_INSERT_DETECT] = 1,
+ [TAPAN_A_MBHC_INSERT_DET_STATUS] = 1,
+ [TAPAN_A_TX_COM_BIAS] = 1,
+ [TAPAN_A_MBHC_SCALING_MUX_1] = 1,
+ [TAPAN_A_MBHC_SCALING_MUX_2] = 1,
+ [TAPAN_A_RESERVED_MAD_ANA_CTRL] = 1,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_1] = 1,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_2] = 1,
+ [TAPAN_A_TX_1_EN] = 1,
+ [TAPAN_A_TX_2_EN] = 1,
+ [TAPAN_A_TX_1_2_ADC_CH1] = 1,
+ [TAPAN_A_TX_1_2_ADC_CH2] = 1,
+ [TAPAN_A_TX_1_2_ATEST_REFCTRL] = 1,
+ [TAPAN_A_TX_1_2_TEST_CTL] = 1,
+ [TAPAN_A_TX_1_2_TEST_BLOCK_EN] = 1,
+ [TAPAN_A_TX_1_2_TXFE_CLKDIV] = 1,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH1] = 1,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH2] = 1,
+ [TAPAN_A_TX_3_EN] = 1,
+ [TAPAN_A_TX_1_2_TEST_EN] = 1,
+ [TAPAN_A_TX_4_5_TXFE_SC_CTL] = 1,
+ [TAPAN_A_TX_4_5_TEST_EN] = 1,
+ [TAPAN_A_TX_4_EN] = 1,
+ [TAPAN_A_TX_5_EN] = 1,
+ [TAPAN_A_TX_4_5_ADC_CH4] = 1,
+ [TAPAN_A_TX_4_5_ADC_CH5] = 1,
+ [TAPAN_A_TX_4_5_ATEST_REFCTRL] = 1,
+ [TAPAN_A_TX_4_5_TEST_CTL] = 1,
+ [TAPAN_A_TX_4_5_TEST_BLOCK_EN] = 1,
+ [TAPAN_A_TX_4_5_TXFE_CKDIV] = 1,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH4] = 1,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH5] = 1,
+ [TAPAN_A_TX_7_MBHC_EN] = 1,
+ [TAPAN_A_TX_7_MBHC_ATEST_REFCTRL] = 1,
+ [TAPAN_A_TX_7_MBHC_ADC] = 1,
+ [TAPAN_A_TX_7_MBHC_TEST_CTL] = 1,
+ [TAPAN_A_TX_7_MBHC_SAR_ERR] = 1,
+ [TAPAN_A_TX_7_TXFE_CLKDIV] = 1,
+ [TAPAN_A_BUCK_MODE_1] = 1,
+ [TAPAN_A_BUCK_MODE_2] = 1,
+ [TAPAN_A_BUCK_MODE_3] = 1,
+ [TAPAN_A_BUCK_MODE_4] = 1,
+ [TAPAN_A_BUCK_MODE_5] = 1,
+ [TAPAN_A_BUCK_CTRL_VCL_1] = 1,
+ [TAPAN_A_BUCK_CTRL_VCL_2] = 1,
+ [TAPAN_A_BUCK_CTRL_VCL_3] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_1] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_2] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_3] = 1,
+ [TAPAN_A_BUCK_CTRL_CCL_4] = 1,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_1] = 1,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_2] = 1,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_3] = 1,
+ [TAPAN_A_BUCK_TMUX_A_D] = 1,
+ [TAPAN_A_NCP_BUCKREF] = 1,
+ [TAPAN_A_NCP_EN] = 1,
+ [TAPAN_A_NCP_CLK] = 1,
+ [TAPAN_A_NCP_STATIC] = 1,
+ [TAPAN_A_NCP_VTH_LOW] = 1,
+ [TAPAN_A_NCP_VTH_HIGH] = 1,
+ [TAPAN_A_NCP_ATEST] = 1,
+ [TAPAN_A_NCP_DTEST] = 1,
+ [TAPAN_A_NCP_DLY1] = 1,
+ [TAPAN_A_NCP_DLY2] = 1,
+ [TAPAN_A_RX_AUX_SW_CTL] = 1,
+ [TAPAN_A_RX_PA_AUX_IN_CONN] = 1,
+ [TAPAN_A_RX_COM_TIMER_DIV] = 1,
+ [TAPAN_A_RX_COM_OCP_CTL] = 1,
+ [TAPAN_A_RX_COM_OCP_COUNT] = 1,
+ [TAPAN_A_RX_COM_DAC_CTL] = 1,
+ [TAPAN_A_RX_COM_BIAS] = 1,
+ [TAPAN_A_RX_HPH_AUTO_CHOP] = 1,
+ [TAPAN_A_RX_HPH_CHOP_CTL] = 1,
+ [TAPAN_A_RX_HPH_BIAS_PA] = 1,
+ [TAPAN_A_RX_HPH_BIAS_LDO] = 1,
+ [TAPAN_A_RX_HPH_BIAS_CNP] = 1,
+ [TAPAN_A_RX_HPH_BIAS_WG_OCP] = 1,
+ [TAPAN_A_RX_HPH_OCP_CTL] = 1,
+ [TAPAN_A_RX_HPH_CNP_EN] = 1,
+ [TAPAN_A_RX_HPH_CNP_WG_CTL] = 1,
+ [TAPAN_A_RX_HPH_CNP_WG_TIME] = 1,
+ [TAPAN_A_RX_HPH_L_GAIN] = 1,
+ [TAPAN_A_RX_HPH_L_TEST] = 1,
+ [TAPAN_A_RX_HPH_L_PA_CTL] = 1,
+ [TAPAN_A_RX_HPH_L_DAC_CTL] = 1,
+ [TAPAN_A_RX_HPH_L_ATEST] = 1,
+ [TAPAN_A_RX_HPH_L_STATUS] = 1,
+ [TAPAN_A_RX_HPH_R_GAIN] = 1,
+ [TAPAN_A_RX_HPH_R_TEST] = 1,
+ [TAPAN_A_RX_HPH_R_PA_CTL] = 1,
+ [TAPAN_A_RX_HPH_R_DAC_CTL] = 1,
+ [TAPAN_A_RX_HPH_R_ATEST] = 1,
+ [TAPAN_A_RX_HPH_R_STATUS] = 1,
+ [TAPAN_A_RX_EAR_BIAS_PA] = 1,
+ [TAPAN_A_RX_EAR_BIAS_CMBUFF] = 1,
+ [TAPAN_A_RX_EAR_EN] = 1,
+ [TAPAN_A_RX_EAR_GAIN] = 1,
+ [TAPAN_A_RX_EAR_CMBUFF] = 1,
+ [TAPAN_A_RX_EAR_ICTL] = 1,
+ [TAPAN_A_RX_EAR_CCOMP] = 1,
+ [TAPAN_A_RX_EAR_VCM] = 1,
+ [TAPAN_A_RX_EAR_CNP] = 1,
+ [TAPAN_A_RX_EAR_DAC_CTL_ATEST] = 1,
+ [TAPAN_A_RX_EAR_STATUS] = 1,
+ [TAPAN_A_RX_LINE_BIAS_PA] = 1,
+ [TAPAN_A_RX_BUCK_BIAS1] = 1,
+ [TAPAN_A_RX_BUCK_BIAS2] = 1,
+ [TAPAN_A_RX_LINE_COM] = 1,
+ [TAPAN_A_RX_LINE_CNP_EN] = 1,
+ [TAPAN_A_RX_LINE_CNP_WG_CTL] = 1,
+ [TAPAN_A_RX_LINE_CNP_WG_TIME] = 1,
+ [TAPAN_A_RX_LINE_1_GAIN] = 1,
+ [TAPAN_A_RX_LINE_1_TEST] = 1,
+ [TAPAN_A_RX_LINE_1_DAC_CTL] = 1,
+ [TAPAN_A_RX_LINE_1_STATUS] = 1,
+ [TAPAN_A_RX_LINE_2_GAIN] = 1,
+ [TAPAN_A_RX_LINE_2_TEST] = 1,
+ [TAPAN_A_RX_LINE_2_DAC_CTL] = 1,
+ [TAPAN_A_RX_LINE_2_STATUS] = 1,
+ [TAPAN_A_RX_LINE_CNP_DBG] = 1,
+ [TAPAN_A_SPKR_DRV_EN] = 1,
+ [TAPAN_A_SPKR_DRV_GAIN] = 1,
+ [TAPAN_A_SPKR_DRV_DAC_CTL] = 1,
+ [TAPAN_A_SPKR_DRV_OCP_CTL] = 1,
+ [TAPAN_A_SPKR_DRV_CLIP_DET] = 1,
+ [TAPAN_A_SPKR_DRV_IEC] = 1,
+ [TAPAN_A_SPKR_DRV_DBG_DAC] = 1,
+ [TAPAN_A_SPKR_DRV_DBG_PA] = 1,
+ [TAPAN_A_SPKR_DRV_DBG_PWRSTG] = 1,
+ [TAPAN_A_SPKR_DRV_BIAS_LDO] = 1,
+ [TAPAN_A_SPKR_DRV_BIAS_INT] = 1,
+ [TAPAN_A_SPKR_DRV_BIAS_PA] = 1,
+ [TAPAN_A_SPKR_DRV_STATUS_OCP] = 1,
+ [TAPAN_A_SPKR_DRV_STATUS_PA] = 1,
+ [TAPAN_A_RC_OSC_FREQ] = 1,
+ [TAPAN_A_RC_OSC_TEST] = 1,
+ [TAPAN_A_RC_OSC_STATUS] = 1,
+ [TAPAN_A_RC_OSC_TUNER] = 1,
+ [TAPAN_A_MBHC_HPH] = 1,
+ [TAPAN_A_CDC_ANC1_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_SHIFT] = 1,
+ [TAPAN_A_CDC_ANC2_SHIFT] = 1,
+ [TAPAN_A_CDC_ANC1_IIR_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_IIR_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_IIR_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_IIR_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_IIR_B3_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_IIR_B3_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_LPF_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_LPF_B1_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_LPF_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_LPF_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_SPARE] = 1,
+ [TAPAN_A_CDC_ANC2_SPARE] = 1,
+ [TAPAN_A_CDC_ANC1_SMLPF_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_SMLPF_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_DCFLT_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_DCFLT_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_GAIN_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_GAIN_CTL] = 1,
+ [TAPAN_A_CDC_ANC1_B2_CTL] = 1,
+ [TAPAN_A_CDC_ANC2_B2_CTL] = 1,
+ [TAPAN_A_CDC_TX1_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX2_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX3_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX4_VOL_CTL_TIMER] = 1,
+ [TAPAN_A_CDC_TX1_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX2_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX3_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX4_VOL_CTL_GAIN] = 1,
+ [TAPAN_A_CDC_TX1_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX2_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX3_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX4_VOL_CTL_CFG] = 1,
+ [TAPAN_A_CDC_TX1_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX2_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX3_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX4_MUX_CTL] = 1,
+ [TAPAN_A_CDC_TX1_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX2_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX3_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX4_CLK_FS_CTL] = 1,
+ [TAPAN_A_CDC_TX1_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_TX2_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_TX3_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_TX4_DMIC_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B1_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B2_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B3_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B4_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B5_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B6_CTL] = 1,
+ [TAPAN_A_CDC_DEBUG_B7_CTL] = 1,
+ [TAPAN_A_CDC_SRC1_PDA_CFG] = 1,
+ [TAPAN_A_CDC_SRC2_PDA_CFG] = 1,
+ [TAPAN_A_CDC_SRC1_FS_CTL] = 1,
+ [TAPAN_A_CDC_SRC2_FS_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B3_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B4_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B5_CTL] = 1,
+ [TAPAN_A_CDC_RX1_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX2_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX3_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX4_B6_CTL] = 1,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL] = 1,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_ANC_RESET_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RX_RESET_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_RESET_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_RESET_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_DMIC_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_DMIC_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_I2S_CTL] = 1,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_OTHR_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL] = 1,
+ [TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RX_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLK_RX_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLK_MCLK_CTL] = 1,
+ [TAPAN_A_CDC_CLK_PDM_CTL] = 1,
+ [TAPAN_A_CDC_CLK_SD_CTL] = 1,
+ [TAPAN_A_CDC_CLK_POWER_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_B1_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_B2_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_B3_CTL] = 1,
+ [TAPAN_A_CDC_CLSH_BUCK_NCP_VARS] = 1,
+ [TAPAN_A_CDC_CLSH_IDLE_HPH_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_IDLE_EAR_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD] = 1,
+ [TAPAN_A_CDC_CLSH_K_ADDR] = 1,
+ [TAPAN_A_CDC_CLSH_K_DATA] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L] = 1,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_EAR] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_HPH] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_EAR] = 1,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_HPH] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B2_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B2_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B3_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B3_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B4_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B4_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B5_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B5_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B6_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B6_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B7_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B7_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_B8_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_B8_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_COEF_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_COEF_B1_CTL] = 1,
+ [TAPAN_A_CDC_IIR1_COEF_B2_CTL] = 1,
+ [TAPAN_A_CDC_IIR2_COEF_B2_CTL] = 1,
+ [TAPAN_A_CDC_TOP_GAIN_UPDATE] = 1,
+ [TAPAN_A_CDC_COMP0_B1_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B1_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B1_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B2_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B2_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B2_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B3_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B3_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B3_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B4_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B4_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B4_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B5_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B5_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B5_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_B6_CTL] = 1,
+ [TAPAN_A_CDC_COMP1_B6_CTL] = 1,
+ [TAPAN_A_CDC_COMP2_B6_CTL] = 1,
+ [TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS] = 1,
+ [TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS] = 1,
+ [TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS] = 1,
+ [TAPAN_A_CDC_COMP0_FS_CFG] = 1,
+ [TAPAN_A_CDC_COMP1_FS_CFG] = 1,
+ [TAPAN_A_CDC_COMP2_FS_CFG] = 1,
+ [TAPAN_A_CDC_CONN_RX1_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX1_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX1_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX2_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX2_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX2_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX3_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX3_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX4_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX4_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX4_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_ANC_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_ANC_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ1_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_EQ2_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC1_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC1_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC2_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_SRC2_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B3_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B4_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B5_CTL] = 1,
+ [TAPAN_A_CDC_CONN_TX_SB_B11_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX_SB_B1_CTL] = 1,
+ [TAPAN_A_CDC_CONN_RX_SB_B2_CTL] = 1,
+ [TAPAN_A_CDC_CONN_CLSH_CTL] = 1,
+ [TAPAN_A_CDC_CONN_MISC] = 1,
+ [TAPAN_A_CDC_MBHC_EN_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_FIR_B1_CFG] = 1,
+ [TAPAN_A_CDC_MBHC_FIR_B2_CFG] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B1_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B2_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B3_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B4_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B5_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_TIMER_B6_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_B1_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B2_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B3_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B4_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B5_STATUS] = 1,
+ [TAPAN_A_CDC_MBHC_B1_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_B2_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B1_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B2_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B3_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B4_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B5_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B6_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B7_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B8_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B9_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B10_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B11_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_VOLT_B12_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_CLK_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_INT_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_DEBUG_CTL] = 1,
+ [TAPAN_A_CDC_MBHC_SPARE] = 1,
+};
+
+const u8 tapan_reset_reg_defaults[TAPAN_CACHE_SIZE] = {
+ [TAPAN_A_CHIP_CTL] = TAPAN_A_CHIP_CTL__POR,
+ [TAPAN_A_CHIP_STATUS] = TAPAN_A_CHIP_STATUS__POR,
+ [TAPAN_A_CHIP_ID_BYTE_0] = TAPAN_A_CHIP_ID_BYTE_0__POR,
+ [TAPAN_A_CHIP_ID_BYTE_1] = TAPAN_A_CHIP_ID_BYTE_1__POR,
+ [TAPAN_A_CHIP_ID_BYTE_2] = TAPAN_A_CHIP_ID_BYTE_2__POR,
+ [TAPAN_A_CHIP_ID_BYTE_3] = TAPAN_A_CHIP_ID_BYTE_3__POR,
+ [TAPAN_A_CHIP_VERSION] = TAPAN_A_CHIP_VERSION__POR,
+ [TAPAN_A_CHIP_DEBUG_CTL] = TAPAN_A_CHIP_DEBUG_CTL__POR,
+ [TAPAN_A_SLAVE_ID_1] = TAPAN_A_SLAVE_ID_1__POR,
+ [TAPAN_A_SLAVE_ID_2] = TAPAN_A_SLAVE_ID_2__POR,
+ [TAPAN_A_SLAVE_ID_3] = TAPAN_A_SLAVE_ID_3__POR,
+ [TAPAN_A_PIN_CTL_OE0] = TAPAN_A_PIN_CTL_OE0__POR,
+ [TAPAN_A_PIN_CTL_DATA0] = TAPAN_A_PIN_CTL_DATA0__POR,
+ [TAPAN_A_HDRIVE_GENERIC] = TAPAN_A_HDRIVE_GENERIC__POR,
+ [TAPAN_A_HDRIVE_OVERRIDE] = TAPAN_A_HDRIVE_OVERRIDE__POR,
+ [TAPAN_A_ANA_CSR_WAIT_STATE] = TAPAN_A_ANA_CSR_WAIT_STATE__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL0] = TAPAN_A_PROCESS_MONITOR_CTL0__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL1] = TAPAN_A_PROCESS_MONITOR_CTL1__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL2] = TAPAN_A_PROCESS_MONITOR_CTL2__POR,
+ [TAPAN_A_PROCESS_MONITOR_CTL3] = TAPAN_A_PROCESS_MONITOR_CTL3__POR,
+ [TAPAN_A_QFUSE_CTL] = TAPAN_A_QFUSE_CTL__POR,
+ [TAPAN_A_QFUSE_STATUS] = TAPAN_A_QFUSE_STATUS__POR,
+ [TAPAN_A_QFUSE_DATA_OUT0] = TAPAN_A_QFUSE_DATA_OUT0__POR,
+ [TAPAN_A_QFUSE_DATA_OUT1] = TAPAN_A_QFUSE_DATA_OUT1__POR,
+ [TAPAN_A_QFUSE_DATA_OUT2] = TAPAN_A_QFUSE_DATA_OUT2__POR,
+ [TAPAN_A_QFUSE_DATA_OUT3] = TAPAN_A_QFUSE_DATA_OUT3__POR,
+ [TAPAN_A_QFUSE_DATA_OUT4] = TAPAN_A_QFUSE_DATA_OUT4__POR,
+ [TAPAN_A_QFUSE_DATA_OUT5] = TAPAN_A_QFUSE_DATA_OUT5__POR,
+ [TAPAN_A_QFUSE_DATA_OUT6] = TAPAN_A_QFUSE_DATA_OUT6__POR,
+ [TAPAN_A_QFUSE_DATA_OUT7] = TAPAN_A_QFUSE_DATA_OUT7__POR,
+ [TAPAN_A_CDC_CTL] = TAPAN_A_CDC_CTL__POR,
+ [TAPAN_A_LEAKAGE_CTL] = TAPAN_A_LEAKAGE_CTL__POR,
+ [TAPAN_A_INTR_MODE] = TAPAN_A_INTR_MODE__POR,
+ [TAPAN_A_INTR_MASK0] = TAPAN_A_INTR_MASK0__POR,
+ [TAPAN_A_INTR_MASK1] = TAPAN_A_INTR_MASK1__POR,
+ [TAPAN_A_INTR_MASK2] = TAPAN_A_INTR_MASK2__POR,
+ [TAPAN_A_INTR_MASK3] = TAPAN_A_INTR_MASK3__POR,
+ [TAPAN_A_INTR_STATUS0] = TAPAN_A_INTR_STATUS0__POR,
+ [TAPAN_A_INTR_STATUS1] = TAPAN_A_INTR_STATUS1__POR,
+ [TAPAN_A_INTR_STATUS2] = TAPAN_A_INTR_STATUS2__POR,
+ [TAPAN_A_INTR_STATUS3] = TAPAN_A_INTR_STATUS3__POR,
+ [TAPAN_A_INTR_CLEAR0] = TAPAN_A_INTR_CLEAR0__POR,
+ [TAPAN_A_INTR_CLEAR1] = TAPAN_A_INTR_CLEAR1__POR,
+ [TAPAN_A_INTR_CLEAR2] = TAPAN_A_INTR_CLEAR2__POR,
+ [TAPAN_A_INTR_CLEAR3] = TAPAN_A_INTR_CLEAR3__POR,
+ [TAPAN_A_INTR_LEVEL0] = TAPAN_A_INTR_LEVEL0__POR,
+ [TAPAN_A_INTR_LEVEL1] = TAPAN_A_INTR_LEVEL1__POR,
+ [TAPAN_A_INTR_LEVEL2] = TAPAN_A_INTR_LEVEL2__POR,
+ [TAPAN_A_INTR_LEVEL3] = TAPAN_A_INTR_LEVEL3__POR,
+ [TAPAN_A_INTR_TEST0] = TAPAN_A_INTR_TEST0__POR,
+ [TAPAN_A_INTR_TEST1] = TAPAN_A_INTR_TEST1__POR,
+ [TAPAN_A_INTR_TEST2] = TAPAN_A_INTR_TEST2__POR,
+ [TAPAN_A_INTR_TEST3] = TAPAN_A_INTR_TEST3__POR,
+ [TAPAN_A_INTR_SET0] = TAPAN_A_INTR_SET0__POR,
+ [TAPAN_A_INTR_SET1] = TAPAN_A_INTR_SET1__POR,
+ [TAPAN_A_INTR_SET2] = TAPAN_A_INTR_SET2__POR,
+ [TAPAN_A_INTR_SET3] = TAPAN_A_INTR_SET3__POR,
+ [TAPAN_A_INTR_DESTN0] = TAPAN_A_INTR_DESTN0__POR,
+ [TAPAN_A_INTR_DESTN1] = TAPAN_A_INTR_DESTN1__POR,
+ [TAPAN_A_INTR_DESTN2] = TAPAN_A_INTR_DESTN2__POR,
+ [TAPAN_A_INTR_DESTN3] = TAPAN_A_INTR_DESTN3__POR,
+ [TAPAN_A_CDC_DMIC_DATA0_MODE] = TAPAN_A_CDC_DMIC_DATA0_MODE__POR,
+ [TAPAN_A_CDC_DMIC_CLK0_MODE] = TAPAN_A_CDC_DMIC_CLK0_MODE__POR,
+ [TAPAN_A_CDC_DMIC_DATA1_MODE] = TAPAN_A_CDC_DMIC_DATA1_MODE__POR,
+ [TAPAN_A_CDC_DMIC_CLK1_MODE] = TAPAN_A_CDC_DMIC_CLK1_MODE__POR,
+ [TAPAN_A_CDC_INTR_MODE] = TAPAN_A_CDC_INTR_MODE__POR,
+ [TAPAN_A_BIAS_REF_CTL] = TAPAN_A_BIAS_REF_CTL__POR,
+ [TAPAN_A_BIAS_CENTRAL_BG_CTL] = TAPAN_A_BIAS_CENTRAL_BG_CTL__POR,
+ [TAPAN_A_BIAS_PRECHRG_CTL] = TAPAN_A_BIAS_PRECHRG_CTL__POR,
+ [TAPAN_A_BIAS_CURR_CTL_1] = TAPAN_A_BIAS_CURR_CTL_1__POR,
+ [TAPAN_A_BIAS_CURR_CTL_2] = TAPAN_A_BIAS_CURR_CTL_2__POR,
+ [TAPAN_A_BIAS_OSC_BG_CTL] = TAPAN_A_BIAS_OSC_BG_CTL__POR,
+ [TAPAN_A_CLK_BUFF_EN1] = TAPAN_A_CLK_BUFF_EN1__POR,
+ [TAPAN_A_CLK_BUFF_EN2] = TAPAN_A_CLK_BUFF_EN2__POR,
+ [TAPAN_A_LDO_H_MODE_1] = TAPAN_A_LDO_H_MODE_1__POR,
+ [TAPAN_A_LDO_H_MODE_2] = TAPAN_A_LDO_H_MODE_2__POR,
+ [TAPAN_A_LDO_H_LOOP_CTL] = TAPAN_A_LDO_H_LOOP_CTL__POR,
+ [TAPAN_A_LDO_H_COMP_1] = TAPAN_A_LDO_H_COMP_1__POR,
+ [TAPAN_A_LDO_H_COMP_2] = TAPAN_A_LDO_H_COMP_2__POR,
+ [TAPAN_A_LDO_H_BIAS_1] = TAPAN_A_LDO_H_BIAS_1__POR,
+ [TAPAN_A_LDO_H_BIAS_2] = TAPAN_A_LDO_H_BIAS_2__POR,
+ [TAPAN_A_LDO_H_BIAS_3] = TAPAN_A_LDO_H_BIAS_3__POR,
+ [TAPAN_A_MICB_CFILT_1_CTL] = TAPAN_A_MICB_CFILT_1_CTL__POR,
+ [TAPAN_A_MICB_CFILT_1_VAL] = TAPAN_A_MICB_CFILT_1_VAL__POR,
+ [TAPAN_A_MICB_CFILT_1_PRECHRG] = TAPAN_A_MICB_CFILT_1_PRECHRG__POR,
+ [TAPAN_A_MICB_1_CTL] = TAPAN_A_MICB_1_CTL__POR,
+ [TAPAN_A_MICB_1_INT_RBIAS] = TAPAN_A_MICB_1_INT_RBIAS__POR,
+ [TAPAN_A_MICB_1_MBHC] = TAPAN_A_MICB_1_MBHC__POR,
+ [TAPAN_A_MICB_CFILT_2_CTL] = TAPAN_A_MICB_CFILT_2_CTL__POR,
+ [TAPAN_A_MICB_CFILT_2_VAL] = TAPAN_A_MICB_CFILT_2_VAL__POR,
+ [TAPAN_A_MICB_CFILT_2_PRECHRG] = TAPAN_A_MICB_CFILT_2_PRECHRG__POR,
+ [TAPAN_A_MICB_2_CTL] = TAPAN_A_MICB_2_CTL__POR,
+ [TAPAN_A_MICB_2_INT_RBIAS] = TAPAN_A_MICB_2_INT_RBIAS__POR,
+ [TAPAN_A_MICB_2_MBHC] = TAPAN_A_MICB_2_MBHC__POR,
+ [TAPAN_A_MICB_CFILT_3_CTL] = TAPAN_A_MICB_CFILT_3_CTL__POR,
+ [TAPAN_A_MICB_CFILT_3_VAL] = TAPAN_A_MICB_CFILT_3_VAL__POR,
+ [TAPAN_A_MICB_CFILT_3_PRECHRG] = TAPAN_A_MICB_CFILT_3_PRECHRG__POR,
+ [TAPAN_A_MICB_3_CTL] = TAPAN_A_MICB_3_CTL__POR,
+ [TAPAN_A_MICB_3_INT_RBIAS] = TAPAN_A_MICB_3_INT_RBIAS__POR,
+ [TAPAN_A_MICB_3_MBHC] = TAPAN_A_MICB_3_MBHC__POR,
+ [TAPAN_A_MBHC_INSERT_DETECT] = TAPAN_A_MBHC_INSERT_DETECT__POR,
+ [TAPAN_A_MBHC_INSERT_DET_STATUS] = TAPAN_A_MBHC_INSERT_DET_STATUS__POR,
+ [TAPAN_A_TX_COM_BIAS] = TAPAN_A_TX_COM_BIAS__POR,
+ [TAPAN_A_MBHC_SCALING_MUX_1] = TAPAN_A_MBHC_SCALING_MUX_1__POR,
+ [TAPAN_A_MBHC_SCALING_MUX_2] = TAPAN_A_MBHC_SCALING_MUX_2__POR,
+ [TAPAN_A_RESERVED_MAD_ANA_CTRL] = TAPAN_A_RESERVED_MAD_ANA_CTRL__POR,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_1] = TAPAN_A_TX_SUP_SWITCH_CTRL_1__POR,
+ [TAPAN_A_TX_SUP_SWITCH_CTRL_2] = TAPAN_A_TX_SUP_SWITCH_CTRL_2__POR,
+ [TAPAN_A_TX_1_EN] = TAPAN_A_TX_1_EN__POR,
+ [TAPAN_A_TX_2_EN] = TAPAN_A_TX_2_EN__POR,
+ [TAPAN_A_TX_1_2_ADC_CH1] = TAPAN_A_TX_1_2_ADC_CH1__POR,
+ [TAPAN_A_TX_1_2_ADC_CH2] = TAPAN_A_TX_1_2_ADC_CH2__POR,
+ [TAPAN_A_TX_1_2_ATEST_REFCTRL] = TAPAN_A_TX_1_2_ATEST_REFCTRL__POR,
+ [TAPAN_A_TX_1_2_TEST_CTL] = TAPAN_A_TX_1_2_TEST_CTL__POR,
+ [TAPAN_A_TX_1_2_TEST_BLOCK_EN] = TAPAN_A_TX_1_2_TEST_BLOCK_EN__POR,
+ [TAPAN_A_TX_1_2_TXFE_CLKDIV] = TAPAN_A_TX_1_2_TXFE_CLKDIV__POR,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH1] = TAPAN_A_TX_1_2_SAR_ERR_CH1__POR,
+ [TAPAN_A_TX_1_2_SAR_ERR_CH2] = TAPAN_A_TX_1_2_SAR_ERR_CH2__POR,
+ [TAPAN_A_TX_3_EN] = TAPAN_A_TX_3_EN__POR,
+ [TAPAN_A_TX_1_2_TEST_EN] = TAPAN_A_TX_1_2_TEST_EN__POR,
+ [TAPAN_A_TX_4_5_TXFE_SC_CTL] = TAPAN_A_TX_4_5_TXFE_SC_CTL__POR,
+ [TAPAN_A_TX_4_5_TEST_EN] = TAPAN_A_TX_4_5_TEST_EN__POR,
+ [TAPAN_A_TX_4_EN] = TAPAN_A_TX_4_EN__POR,
+ [TAPAN_A_TX_5_EN] = TAPAN_A_TX_5_EN__POR,
+ [TAPAN_A_TX_4_5_ADC_CH4] = TAPAN_A_TX_4_5_ADC_CH4__POR,
+ [TAPAN_A_TX_4_5_ADC_CH5] = TAPAN_A_TX_4_5_ADC_CH5__POR,
+ [TAPAN_A_TX_4_5_ATEST_REFCTRL] = TAPAN_A_TX_4_5_ATEST_REFCTRL__POR,
+ [TAPAN_A_TX_4_5_TEST_CTL] = TAPAN_A_TX_4_5_TEST_CTL__POR,
+ [TAPAN_A_TX_4_5_TEST_BLOCK_EN] = TAPAN_A_TX_4_5_TEST_BLOCK_EN__POR,
+ [TAPAN_A_TX_4_5_TXFE_CKDIV] = TAPAN_A_TX_4_5_TXFE_CKDIV__POR,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH4] = TAPAN_A_TX_4_5_SAR_ERR_CH4__POR,
+ [TAPAN_A_TX_4_5_SAR_ERR_CH5] = TAPAN_A_TX_4_5_SAR_ERR_CH5__POR,
+ [TAPAN_A_TX_7_MBHC_EN] = TAPAN_A_TX_7_MBHC_EN__POR,
+ [TAPAN_A_TX_7_MBHC_ATEST_REFCTRL] =
+ TAPAN_A_TX_7_MBHC_ATEST_REFCTRL__POR,
+ [TAPAN_A_TX_7_MBHC_ADC] = TAPAN_A_TX_7_MBHC_ADC__POR,
+ [TAPAN_A_TX_7_MBHC_TEST_CTL] = TAPAN_A_TX_7_MBHC_TEST_CTL__POR,
+ [TAPAN_A_TX_7_MBHC_SAR_ERR] = TAPAN_A_TX_7_MBHC_SAR_ERR__POR,
+ [TAPAN_A_TX_7_TXFE_CLKDIV] = TAPAN_A_TX_7_TXFE_CLKDIV__POR,
+ [TAPAN_A_BUCK_MODE_1] = TAPAN_A_BUCK_MODE_1__POR,
+ [TAPAN_A_BUCK_MODE_2] = TAPAN_A_BUCK_MODE_2__POR,
+ [TAPAN_A_BUCK_MODE_3] = TAPAN_A_BUCK_MODE_3__POR,
+ [TAPAN_A_BUCK_MODE_4] = TAPAN_A_BUCK_MODE_4__POR,
+ [TAPAN_A_BUCK_MODE_5] = TAPAN_A_BUCK_MODE_5__POR,
+ [TAPAN_A_BUCK_CTRL_VCL_1] = TAPAN_A_BUCK_CTRL_VCL_1__POR,
+ [TAPAN_A_BUCK_CTRL_VCL_2] = TAPAN_A_BUCK_CTRL_VCL_2__POR,
+ [TAPAN_A_BUCK_CTRL_VCL_3] = TAPAN_A_BUCK_CTRL_VCL_3__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_1] = TAPAN_A_BUCK_CTRL_CCL_1__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_2] = TAPAN_A_BUCK_CTRL_CCL_2__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_3] = TAPAN_A_BUCK_CTRL_CCL_3__POR,
+ [TAPAN_A_BUCK_CTRL_CCL_4] = TAPAN_A_BUCK_CTRL_CCL_4__POR,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_1] = TAPAN_A_BUCK_CTRL_PWM_DRVR_1__POR,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_2] = TAPAN_A_BUCK_CTRL_PWM_DRVR_2__POR,
+ [TAPAN_A_BUCK_CTRL_PWM_DRVR_3] = TAPAN_A_BUCK_CTRL_PWM_DRVR_3__POR,
+ [TAPAN_A_BUCK_TMUX_A_D] = TAPAN_A_BUCK_TMUX_A_D__POR,
+ [TAPAN_A_NCP_BUCKREF] = TAPAN_A_NCP_BUCKREF__POR,
+ [TAPAN_A_NCP_EN] = TAPAN_A_NCP_EN__POR,
+ [TAPAN_A_NCP_CLK] = TAPAN_A_NCP_CLK__POR,
+ [TAPAN_A_NCP_STATIC] = TAPAN_A_NCP_STATIC__POR,
+ [TAPAN_A_NCP_VTH_LOW] = TAPAN_A_NCP_VTH_LOW__POR,
+ [TAPAN_A_NCP_VTH_HIGH] = TAPAN_A_NCP_VTH_HIGH__POR,
+ [TAPAN_A_NCP_ATEST] = TAPAN_A_NCP_ATEST__POR,
+ [TAPAN_A_NCP_DTEST] = TAPAN_A_NCP_DTEST__POR,
+ [TAPAN_A_NCP_DLY1] = TAPAN_A_NCP_DLY1__POR,
+ [TAPAN_A_NCP_DLY2] = TAPAN_A_NCP_DLY2__POR,
+ [TAPAN_A_RX_AUX_SW_CTL] = TAPAN_A_RX_AUX_SW_CTL__POR,
+ [TAPAN_A_RX_PA_AUX_IN_CONN] = TAPAN_A_RX_PA_AUX_IN_CONN__POR,
+ [TAPAN_A_RX_COM_TIMER_DIV] = TAPAN_A_RX_COM_TIMER_DIV__POR,
+ [TAPAN_A_RX_COM_OCP_CTL] = TAPAN_A_RX_COM_OCP_CTL__POR,
+ [TAPAN_A_RX_COM_OCP_COUNT] = TAPAN_A_RX_COM_OCP_COUNT__POR,
+ [TAPAN_A_RX_COM_DAC_CTL] = TAPAN_A_RX_COM_DAC_CTL__POR,
+ [TAPAN_A_RX_COM_BIAS] = TAPAN_A_RX_COM_BIAS__POR,
+ [TAPAN_A_RX_HPH_AUTO_CHOP] = TAPAN_A_RX_HPH_AUTO_CHOP__POR,
+ [TAPAN_A_RX_HPH_CHOP_CTL] = TAPAN_A_RX_HPH_CHOP_CTL__POR,
+ [TAPAN_A_RX_HPH_BIAS_PA] = TAPAN_A_RX_HPH_BIAS_PA__POR,
+ [TAPAN_A_RX_HPH_BIAS_LDO] = TAPAN_A_RX_HPH_BIAS_LDO__POR,
+ [TAPAN_A_RX_HPH_BIAS_CNP] = TAPAN_A_RX_HPH_BIAS_CNP__POR,
+ [TAPAN_A_RX_HPH_BIAS_WG_OCP] = TAPAN_A_RX_HPH_BIAS_WG_OCP__POR,
+ [TAPAN_A_RX_HPH_OCP_CTL] = TAPAN_A_RX_HPH_OCP_CTL__POR,
+ [TAPAN_A_RX_HPH_CNP_EN] = TAPAN_A_RX_HPH_CNP_EN__POR,
+ [TAPAN_A_RX_HPH_CNP_WG_CTL] = TAPAN_A_RX_HPH_CNP_WG_CTL__POR,
+ [TAPAN_A_RX_HPH_CNP_WG_TIME] = TAPAN_A_RX_HPH_CNP_WG_TIME__POR,
+ [TAPAN_A_RX_HPH_L_GAIN] = TAPAN_A_RX_HPH_L_GAIN__POR,
+ [TAPAN_A_RX_HPH_L_TEST] = TAPAN_A_RX_HPH_L_TEST__POR,
+ [TAPAN_A_RX_HPH_L_PA_CTL] = TAPAN_A_RX_HPH_L_PA_CTL__POR,
+ [TAPAN_A_RX_HPH_L_DAC_CTL] = TAPAN_A_RX_HPH_L_DAC_CTL__POR,
+ [TAPAN_A_RX_HPH_L_ATEST] = TAPAN_A_RX_HPH_L_ATEST__POR,
+ [TAPAN_A_RX_HPH_L_STATUS] = TAPAN_A_RX_HPH_L_STATUS__POR,
+ [TAPAN_A_RX_HPH_R_GAIN] = TAPAN_A_RX_HPH_R_GAIN__POR,
+ [TAPAN_A_RX_HPH_R_TEST] = TAPAN_A_RX_HPH_R_TEST__POR,
+ [TAPAN_A_RX_HPH_R_PA_CTL] = TAPAN_A_RX_HPH_R_PA_CTL__POR,
+ [TAPAN_A_RX_HPH_R_DAC_CTL] = TAPAN_A_RX_HPH_R_DAC_CTL__POR,
+ [TAPAN_A_RX_HPH_R_ATEST] = TAPAN_A_RX_HPH_R_ATEST__POR,
+ [TAPAN_A_RX_HPH_R_STATUS] = TAPAN_A_RX_HPH_R_STATUS__POR,
+ [TAPAN_A_RX_EAR_BIAS_PA] = TAPAN_A_RX_EAR_BIAS_PA__POR,
+ [TAPAN_A_RX_EAR_BIAS_CMBUFF] = TAPAN_A_RX_EAR_BIAS_CMBUFF__POR,
+ [TAPAN_A_RX_EAR_EN] = TAPAN_A_RX_EAR_EN__POR,
+ [TAPAN_A_RX_EAR_GAIN] = TAPAN_A_RX_EAR_GAIN__POR,
+ [TAPAN_A_RX_EAR_CMBUFF] = TAPAN_A_RX_EAR_CMBUFF__POR,
+ [TAPAN_A_RX_EAR_ICTL] = TAPAN_A_RX_EAR_ICTL__POR,
+ [TAPAN_A_RX_EAR_CCOMP] = TAPAN_A_RX_EAR_CCOMP__POR,
+ [TAPAN_A_RX_EAR_VCM] = TAPAN_A_RX_EAR_VCM__POR,
+ [TAPAN_A_RX_EAR_CNP] = TAPAN_A_RX_EAR_CNP__POR,
+ [TAPAN_A_RX_EAR_DAC_CTL_ATEST] = TAPAN_A_RX_EAR_DAC_CTL_ATEST__POR,
+ [TAPAN_A_RX_EAR_STATUS] = TAPAN_A_RX_EAR_STATUS__POR,
+ [TAPAN_A_RX_LINE_BIAS_PA] = TAPAN_A_RX_LINE_BIAS_PA__POR,
+ [TAPAN_A_RX_BUCK_BIAS1] = TAPAN_A_RX_BUCK_BIAS1__POR,
+ [TAPAN_A_RX_BUCK_BIAS2] = TAPAN_A_RX_BUCK_BIAS2__POR,
+ [TAPAN_A_RX_LINE_COM] = TAPAN_A_RX_LINE_COM__POR,
+ [TAPAN_A_RX_LINE_CNP_EN] = TAPAN_A_RX_LINE_CNP_EN__POR,
+ [TAPAN_A_RX_LINE_CNP_WG_CTL] = TAPAN_A_RX_LINE_CNP_WG_CTL__POR,
+ [TAPAN_A_RX_LINE_CNP_WG_TIME] = TAPAN_A_RX_LINE_CNP_WG_TIME__POR,
+ [TAPAN_A_RX_LINE_1_GAIN] = TAPAN_A_RX_LINE_1_GAIN__POR,
+ [TAPAN_A_RX_LINE_1_TEST] = TAPAN_A_RX_LINE_1_TEST__POR,
+ [TAPAN_A_RX_LINE_1_DAC_CTL] = TAPAN_A_RX_LINE_1_DAC_CTL__POR,
+ [TAPAN_A_RX_LINE_1_STATUS] = TAPAN_A_RX_LINE_1_STATUS__POR,
+ [TAPAN_A_RX_LINE_2_GAIN] = TAPAN_A_RX_LINE_2_GAIN__POR,
+ [TAPAN_A_RX_LINE_2_TEST] = TAPAN_A_RX_LINE_2_TEST__POR,
+ [TAPAN_A_RX_LINE_2_DAC_CTL] = TAPAN_A_RX_LINE_2_DAC_CTL__POR,
+ [TAPAN_A_RX_LINE_2_STATUS] = TAPAN_A_RX_LINE_2_STATUS__POR,
+ [TAPAN_A_RX_LINE_CNP_DBG] = TAPAN_A_RX_LINE_CNP_DBG__POR,
+ [TAPAN_A_SPKR_DRV_EN] = TAPAN_A_SPKR_DRV_EN__POR,
+ [TAPAN_A_SPKR_DRV_GAIN] = TAPAN_A_SPKR_DRV_GAIN__POR,
+ [TAPAN_A_SPKR_DRV_DAC_CTL] = TAPAN_A_SPKR_DRV_DAC_CTL__POR,
+ [TAPAN_A_SPKR_DRV_OCP_CTL] = TAPAN_A_SPKR_DRV_OCP_CTL__POR,
+ [TAPAN_A_SPKR_DRV_CLIP_DET] = TAPAN_A_SPKR_DRV_CLIP_DET__POR,
+ [TAPAN_A_SPKR_DRV_IEC] = TAPAN_A_SPKR_DRV_IEC__POR,
+ [TAPAN_A_SPKR_DRV_DBG_DAC] = TAPAN_A_SPKR_DRV_DBG_DAC__POR,
+ [TAPAN_A_SPKR_DRV_DBG_PA] = TAPAN_A_SPKR_DRV_DBG_PA__POR,
+ [TAPAN_A_SPKR_DRV_DBG_PWRSTG] = TAPAN_A_SPKR_DRV_DBG_PWRSTG__POR,
+ [TAPAN_A_SPKR_DRV_BIAS_LDO] = TAPAN_A_SPKR_DRV_BIAS_LDO__POR,
+ [TAPAN_A_SPKR_DRV_BIAS_INT] = TAPAN_A_SPKR_DRV_BIAS_INT__POR,
+ [TAPAN_A_SPKR_DRV_BIAS_PA] = TAPAN_A_SPKR_DRV_BIAS_PA__POR,
+ [TAPAN_A_SPKR_DRV_STATUS_OCP] = TAPAN_A_SPKR_DRV_STATUS_OCP__POR,
+ [TAPAN_A_SPKR_DRV_STATUS_PA] = TAPAN_A_SPKR_DRV_STATUS_PA__POR,
+ [TAPAN_A_RC_OSC_FREQ] = TAPAN_A_RC_OSC_FREQ__POR,
+ [TAPAN_A_RC_OSC_TEST] = TAPAN_A_RC_OSC_TEST__POR,
+ [TAPAN_A_RC_OSC_STATUS] = TAPAN_A_RC_OSC_STATUS__POR,
+ [TAPAN_A_RC_OSC_TUNER] = TAPAN_A_RC_OSC_TUNER__POR,
+ [TAPAN_A_MBHC_HPH] = TAPAN_A_MBHC_HPH__POR,
+ [TAPAN_A_CDC_ANC1_B1_CTL] = TAPAN_A_CDC_ANC1_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC2_B1_CTL] = TAPAN_A_CDC_ANC2_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC1_SHIFT] = TAPAN_A_CDC_ANC1_SHIFT__POR,
+ [TAPAN_A_CDC_ANC2_SHIFT] = TAPAN_A_CDC_ANC2_SHIFT__POR,
+ [TAPAN_A_CDC_ANC1_IIR_B1_CTL] = TAPAN_A_CDC_ANC1_IIR_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC2_IIR_B1_CTL] = TAPAN_A_CDC_ANC2_IIR_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC1_IIR_B2_CTL] = TAPAN_A_CDC_ANC1_IIR_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC2_IIR_B2_CTL] = TAPAN_A_CDC_ANC2_IIR_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC1_IIR_B3_CTL] = TAPAN_A_CDC_ANC1_IIR_B3_CTL__POR,
+ [TAPAN_A_CDC_ANC2_IIR_B3_CTL] = TAPAN_A_CDC_ANC2_IIR_B3_CTL__POR,
+ [TAPAN_A_CDC_ANC1_LPF_B1_CTL] = TAPAN_A_CDC_ANC1_LPF_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC2_LPF_B1_CTL] = TAPAN_A_CDC_ANC2_LPF_B1_CTL__POR,
+ [TAPAN_A_CDC_ANC1_LPF_B2_CTL] = TAPAN_A_CDC_ANC1_LPF_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC2_LPF_B2_CTL] = TAPAN_A_CDC_ANC2_LPF_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC1_SPARE] = TAPAN_A_CDC_ANC1_SPARE__POR,
+ [TAPAN_A_CDC_ANC2_SPARE] = TAPAN_A_CDC_ANC2_SPARE__POR,
+ [TAPAN_A_CDC_ANC1_SMLPF_CTL] = TAPAN_A_CDC_ANC1_SMLPF_CTL__POR,
+ [TAPAN_A_CDC_ANC2_SMLPF_CTL] = TAPAN_A_CDC_ANC2_SMLPF_CTL__POR,
+ [TAPAN_A_CDC_ANC1_DCFLT_CTL] = TAPAN_A_CDC_ANC1_DCFLT_CTL__POR,
+ [TAPAN_A_CDC_ANC2_DCFLT_CTL] = TAPAN_A_CDC_ANC2_DCFLT_CTL__POR,
+ [TAPAN_A_CDC_ANC1_GAIN_CTL] = TAPAN_A_CDC_ANC1_GAIN_CTL__POR,
+ [TAPAN_A_CDC_ANC2_GAIN_CTL] = TAPAN_A_CDC_ANC2_GAIN_CTL__POR,
+ [TAPAN_A_CDC_ANC1_B2_CTL] = TAPAN_A_CDC_ANC1_B2_CTL__POR,
+ [TAPAN_A_CDC_ANC2_B2_CTL] = TAPAN_A_CDC_ANC2_B2_CTL__POR,
+ [TAPAN_A_CDC_TX1_VOL_CTL_TIMER] = TAPAN_A_CDC_TX1_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX2_VOL_CTL_TIMER] = TAPAN_A_CDC_TX2_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX3_VOL_CTL_TIMER] = TAPAN_A_CDC_TX3_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX4_VOL_CTL_TIMER] = TAPAN_A_CDC_TX4_VOL_CTL_TIMER__POR,
+ [TAPAN_A_CDC_TX1_VOL_CTL_GAIN] = TAPAN_A_CDC_TX1_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX2_VOL_CTL_GAIN] = TAPAN_A_CDC_TX2_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX3_VOL_CTL_GAIN] = TAPAN_A_CDC_TX3_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX4_VOL_CTL_GAIN] = TAPAN_A_CDC_TX4_VOL_CTL_GAIN__POR,
+ [TAPAN_A_CDC_TX1_VOL_CTL_CFG] = TAPAN_A_CDC_TX1_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX2_VOL_CTL_CFG] = TAPAN_A_CDC_TX2_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX3_VOL_CTL_CFG] = TAPAN_A_CDC_TX3_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX4_VOL_CTL_CFG] = TAPAN_A_CDC_TX4_VOL_CTL_CFG__POR,
+ [TAPAN_A_CDC_TX1_MUX_CTL] = TAPAN_A_CDC_TX1_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX2_MUX_CTL] = TAPAN_A_CDC_TX2_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX3_MUX_CTL] = TAPAN_A_CDC_TX3_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX4_MUX_CTL] = TAPAN_A_CDC_TX4_MUX_CTL__POR,
+ [TAPAN_A_CDC_TX1_CLK_FS_CTL] = TAPAN_A_CDC_TX1_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX2_CLK_FS_CTL] = TAPAN_A_CDC_TX2_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX3_CLK_FS_CTL] = TAPAN_A_CDC_TX3_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX4_CLK_FS_CTL] = TAPAN_A_CDC_TX4_CLK_FS_CTL__POR,
+ [TAPAN_A_CDC_TX1_DMIC_CTL] = TAPAN_A_CDC_TX1_DMIC_CTL__POR,
+ [TAPAN_A_CDC_TX2_DMIC_CTL] = TAPAN_A_CDC_TX2_DMIC_CTL__POR,
+ [TAPAN_A_CDC_TX3_DMIC_CTL] = TAPAN_A_CDC_TX3_DMIC_CTL__POR,
+ [TAPAN_A_CDC_TX4_DMIC_CTL] = TAPAN_A_CDC_TX4_DMIC_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B1_CTL] = TAPAN_A_CDC_DEBUG_B1_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B2_CTL] = TAPAN_A_CDC_DEBUG_B2_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B3_CTL] = TAPAN_A_CDC_DEBUG_B3_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B4_CTL] = TAPAN_A_CDC_DEBUG_B4_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B5_CTL] = TAPAN_A_CDC_DEBUG_B5_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B6_CTL] = TAPAN_A_CDC_DEBUG_B6_CTL__POR,
+ [TAPAN_A_CDC_DEBUG_B7_CTL] = TAPAN_A_CDC_DEBUG_B7_CTL__POR,
+ [TAPAN_A_CDC_SRC1_PDA_CFG] = TAPAN_A_CDC_SRC1_PDA_CFG__POR,
+ [TAPAN_A_CDC_SRC2_PDA_CFG] = TAPAN_A_CDC_SRC2_PDA_CFG__POR,
+ [TAPAN_A_CDC_SRC1_FS_CTL] = TAPAN_A_CDC_SRC1_FS_CTL__POR,
+ [TAPAN_A_CDC_SRC2_FS_CTL] = TAPAN_A_CDC_SRC2_FS_CTL__POR,
+ [TAPAN_A_CDC_RX1_B1_CTL] = TAPAN_A_CDC_RX1_B1_CTL__POR,
+ [TAPAN_A_CDC_RX2_B1_CTL] = TAPAN_A_CDC_RX2_B1_CTL__POR,
+ [TAPAN_A_CDC_RX3_B1_CTL] = TAPAN_A_CDC_RX3_B1_CTL__POR,
+ [TAPAN_A_CDC_RX4_B1_CTL] = TAPAN_A_CDC_RX4_B1_CTL__POR,
+ [TAPAN_A_CDC_RX1_B2_CTL] = TAPAN_A_CDC_RX1_B2_CTL__POR,
+ [TAPAN_A_CDC_RX2_B2_CTL] = TAPAN_A_CDC_RX2_B2_CTL__POR,
+ [TAPAN_A_CDC_RX3_B2_CTL] = TAPAN_A_CDC_RX3_B2_CTL__POR,
+ [TAPAN_A_CDC_RX4_B2_CTL] = TAPAN_A_CDC_RX4_B2_CTL__POR,
+ [TAPAN_A_CDC_RX1_B3_CTL] = TAPAN_A_CDC_RX1_B3_CTL__POR,
+ [TAPAN_A_CDC_RX2_B3_CTL] = TAPAN_A_CDC_RX2_B3_CTL__POR,
+ [TAPAN_A_CDC_RX3_B3_CTL] = TAPAN_A_CDC_RX3_B3_CTL__POR,
+ [TAPAN_A_CDC_RX4_B3_CTL] = TAPAN_A_CDC_RX4_B3_CTL__POR,
+ [TAPAN_A_CDC_RX1_B4_CTL] = TAPAN_A_CDC_RX1_B4_CTL__POR,
+ [TAPAN_A_CDC_RX2_B4_CTL] = TAPAN_A_CDC_RX2_B4_CTL__POR,
+ [TAPAN_A_CDC_RX3_B4_CTL] = TAPAN_A_CDC_RX3_B4_CTL__POR,
+ [TAPAN_A_CDC_RX4_B4_CTL] = TAPAN_A_CDC_RX4_B4_CTL__POR,
+ [TAPAN_A_CDC_RX1_B5_CTL] = TAPAN_A_CDC_RX1_B5_CTL__POR,
+ [TAPAN_A_CDC_RX2_B5_CTL] = TAPAN_A_CDC_RX2_B5_CTL__POR,
+ [TAPAN_A_CDC_RX3_B5_CTL] = TAPAN_A_CDC_RX3_B5_CTL__POR,
+ [TAPAN_A_CDC_RX4_B5_CTL] = TAPAN_A_CDC_RX4_B5_CTL__POR,
+ [TAPAN_A_CDC_RX1_B6_CTL] = TAPAN_A_CDC_RX1_B6_CTL__POR,
+ [TAPAN_A_CDC_RX2_B6_CTL] = TAPAN_A_CDC_RX2_B6_CTL__POR,
+ [TAPAN_A_CDC_RX3_B6_CTL] = TAPAN_A_CDC_RX3_B6_CTL__POR,
+ [TAPAN_A_CDC_RX4_B6_CTL] = TAPAN_A_CDC_RX4_B6_CTL__POR,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL__POR,
+ [TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_ANC_RESET_CTL] = TAPAN_A_CDC_CLK_ANC_RESET_CTL__POR,
+ [TAPAN_A_CDC_CLK_RX_RESET_CTL] = TAPAN_A_CDC_CLK_RX_RESET_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_RESET_B1_CTL] =
+ TAPAN_A_CDC_CLK_TX_RESET_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_RESET_B2_CTL] =
+ TAPAN_A_CDC_CLK_TX_RESET_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_DMIC_B1_CTL] = TAPAN_A_CDC_CLK_DMIC_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_DMIC_B2_CTL] = TAPAN_A_CDC_CLK_DMIC_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_I2S_CTL] = TAPAN_A_CDC_CLK_I2S_CTL__POR,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL] =
+ TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL] =
+ TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL] =
+ TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL] =
+ TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_OTHR_CTL] = TAPAN_A_CDC_CLK_OTHR_CTL__POR,
+ [TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL] =
+ TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL__POR,
+ [TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL] = TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL__POR,
+ [TAPAN_A_CDC_CLK_RX_B1_CTL] = TAPAN_A_CDC_CLK_RX_B1_CTL__POR,
+ [TAPAN_A_CDC_CLK_RX_B2_CTL] = TAPAN_A_CDC_CLK_RX_B2_CTL__POR,
+ [TAPAN_A_CDC_CLK_MCLK_CTL] = TAPAN_A_CDC_CLK_MCLK_CTL__POR,
+ [TAPAN_A_CDC_CLK_PDM_CTL] = TAPAN_A_CDC_CLK_PDM_CTL__POR,
+ [TAPAN_A_CDC_CLK_SD_CTL] = TAPAN_A_CDC_CLK_SD_CTL__POR,
+ [TAPAN_A_CDC_CLK_POWER_CTL] = TAPAN_A_CDC_CLK_POWER_CTL__POR,
+ [TAPAN_A_CDC_CLSH_B1_CTL] = TAPAN_A_CDC_CLSH_B1_CTL__POR,
+ [TAPAN_A_CDC_CLSH_B2_CTL] = TAPAN_A_CDC_CLSH_B2_CTL__POR,
+ [TAPAN_A_CDC_CLSH_B3_CTL] = TAPAN_A_CDC_CLSH_B3_CTL__POR,
+ [TAPAN_A_CDC_CLSH_BUCK_NCP_VARS] = TAPAN_A_CDC_CLSH_BUCK_NCP_VARS__POR,
+ [TAPAN_A_CDC_CLSH_IDLE_HPH_THSD] = TAPAN_A_CDC_CLSH_IDLE_HPH_THSD__POR,
+ [TAPAN_A_CDC_CLSH_IDLE_EAR_THSD] = TAPAN_A_CDC_CLSH_IDLE_EAR_THSD__POR,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD] =
+ TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR,
+ [TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD] =
+ TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR,
+ [TAPAN_A_CDC_CLSH_K_ADDR] = TAPAN_A_CDC_CLSH_K_ADDR__POR,
+ [TAPAN_A_CDC_CLSH_K_DATA] = TAPAN_A_CDC_CLSH_K_DATA__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L__POR,
+ [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U] =
+ TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_EAR] = TAPAN_A_CDC_CLSH_V_PA_HD_EAR__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_HD_HPH] = TAPAN_A_CDC_CLSH_V_PA_HD_HPH__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_EAR] = TAPAN_A_CDC_CLSH_V_PA_MIN_EAR__POR,
+ [TAPAN_A_CDC_CLSH_V_PA_MIN_HPH] = TAPAN_A_CDC_CLSH_V_PA_MIN_HPH__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B1_CTL] = TAPAN_A_CDC_IIR1_GAIN_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B1_CTL] = TAPAN_A_CDC_IIR2_GAIN_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B2_CTL] = TAPAN_A_CDC_IIR1_GAIN_B2_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B2_CTL] = TAPAN_A_CDC_IIR2_GAIN_B2_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B3_CTL] = TAPAN_A_CDC_IIR1_GAIN_B3_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B3_CTL] = TAPAN_A_CDC_IIR2_GAIN_B3_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B4_CTL] = TAPAN_A_CDC_IIR1_GAIN_B4_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B4_CTL] = TAPAN_A_CDC_IIR2_GAIN_B4_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B5_CTL] = TAPAN_A_CDC_IIR1_GAIN_B5_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B5_CTL] = TAPAN_A_CDC_IIR2_GAIN_B5_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B6_CTL] = TAPAN_A_CDC_IIR1_GAIN_B6_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B6_CTL] = TAPAN_A_CDC_IIR2_GAIN_B6_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B7_CTL] = TAPAN_A_CDC_IIR1_GAIN_B7_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B7_CTL] = TAPAN_A_CDC_IIR2_GAIN_B7_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_B8_CTL] = TAPAN_A_CDC_IIR1_GAIN_B8_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_B8_CTL] = TAPAN_A_CDC_IIR2_GAIN_B8_CTL__POR,
+ [TAPAN_A_CDC_IIR1_CTL] = TAPAN_A_CDC_IIR1_CTL__POR,
+ [TAPAN_A_CDC_IIR2_CTL] = TAPAN_A_CDC_IIR2_CTL__POR,
+ [TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL] =
+ TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL__POR,
+ [TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL] =
+ TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL__POR,
+ [TAPAN_A_CDC_IIR1_COEF_B1_CTL] = TAPAN_A_CDC_IIR1_COEF_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR2_COEF_B1_CTL] = TAPAN_A_CDC_IIR2_COEF_B1_CTL__POR,
+ [TAPAN_A_CDC_IIR1_COEF_B2_CTL] = TAPAN_A_CDC_IIR1_COEF_B2_CTL__POR,
+ [TAPAN_A_CDC_IIR2_COEF_B2_CTL] = TAPAN_A_CDC_IIR2_COEF_B2_CTL__POR,
+ [TAPAN_A_CDC_TOP_GAIN_UPDATE] = TAPAN_A_CDC_TOP_GAIN_UPDATE__POR,
+ [TAPAN_A_CDC_COMP0_B1_CTL] = TAPAN_A_CDC_COMP0_B1_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B1_CTL] = TAPAN_A_CDC_COMP1_B1_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B1_CTL] = TAPAN_A_CDC_COMP2_B1_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B2_CTL] = TAPAN_A_CDC_COMP0_B2_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B2_CTL] = TAPAN_A_CDC_COMP1_B2_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B2_CTL] = TAPAN_A_CDC_COMP2_B2_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B3_CTL] = TAPAN_A_CDC_COMP0_B3_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B3_CTL] = TAPAN_A_CDC_COMP1_B3_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B3_CTL] = TAPAN_A_CDC_COMP2_B3_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B4_CTL] = TAPAN_A_CDC_COMP0_B4_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B4_CTL] = TAPAN_A_CDC_COMP1_B4_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B4_CTL] = TAPAN_A_CDC_COMP2_B4_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B5_CTL] = TAPAN_A_CDC_COMP0_B5_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B5_CTL] = TAPAN_A_CDC_COMP1_B5_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B5_CTL] = TAPAN_A_CDC_COMP2_B5_CTL__POR,
+ [TAPAN_A_CDC_COMP0_B6_CTL] = TAPAN_A_CDC_COMP0_B6_CTL__POR,
+ [TAPAN_A_CDC_COMP1_B6_CTL] = TAPAN_A_CDC_COMP1_B6_CTL__POR,
+ [TAPAN_A_CDC_COMP2_B6_CTL] = TAPAN_A_CDC_COMP2_B6_CTL__POR,
+ [TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS] =
+ TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS__POR,
+ [TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS] =
+ TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS__POR,
+ [TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS] =
+ TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS__POR,
+ [TAPAN_A_CDC_COMP0_FS_CFG] = TAPAN_A_CDC_COMP0_FS_CFG__POR,
+ [TAPAN_A_CDC_COMP1_FS_CFG] = TAPAN_A_CDC_COMP1_FS_CFG__POR,
+ [TAPAN_A_CDC_COMP2_FS_CFG] = TAPAN_A_CDC_COMP2_FS_CFG__POR,
+ [TAPAN_A_CDC_CONN_RX1_B1_CTL] = TAPAN_A_CDC_CONN_RX1_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX1_B2_CTL] = TAPAN_A_CDC_CONN_RX1_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX1_B3_CTL] = TAPAN_A_CDC_CONN_RX1_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX2_B1_CTL] = TAPAN_A_CDC_CONN_RX2_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX2_B2_CTL] = TAPAN_A_CDC_CONN_RX2_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX2_B3_CTL] = TAPAN_A_CDC_CONN_RX2_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX3_B1_CTL] = TAPAN_A_CDC_CONN_RX3_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX3_B2_CTL] = TAPAN_A_CDC_CONN_RX3_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX4_B1_CTL] = TAPAN_A_CDC_CONN_RX4_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX4_B2_CTL] = TAPAN_A_CDC_CONN_RX4_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX4_B3_CTL] = TAPAN_A_CDC_CONN_RX4_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_ANC_B1_CTL] = TAPAN_A_CDC_CONN_ANC_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_ANC_B2_CTL] = TAPAN_A_CDC_CONN_ANC_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B1_CTL] = TAPAN_A_CDC_CONN_TX_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B2_CTL] = TAPAN_A_CDC_CONN_TX_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B3_CTL] = TAPAN_A_CDC_CONN_TX_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_B4_CTL] = TAPAN_A_CDC_CONN_TX_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B1_CTL] = TAPAN_A_CDC_CONN_EQ1_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B2_CTL] = TAPAN_A_CDC_CONN_EQ1_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B3_CTL] = TAPAN_A_CDC_CONN_EQ1_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ1_B4_CTL] = TAPAN_A_CDC_CONN_EQ1_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B1_CTL] = TAPAN_A_CDC_CONN_EQ2_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B2_CTL] = TAPAN_A_CDC_CONN_EQ2_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B3_CTL] = TAPAN_A_CDC_CONN_EQ2_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_EQ2_B4_CTL] = TAPAN_A_CDC_CONN_EQ2_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC1_B1_CTL] = TAPAN_A_CDC_CONN_SRC1_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC1_B2_CTL] = TAPAN_A_CDC_CONN_SRC1_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC2_B1_CTL] = TAPAN_A_CDC_CONN_SRC2_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_SRC2_B2_CTL] = TAPAN_A_CDC_CONN_SRC2_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B1_CTL] = TAPAN_A_CDC_CONN_TX_SB_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B2_CTL] = TAPAN_A_CDC_CONN_TX_SB_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B3_CTL] = TAPAN_A_CDC_CONN_TX_SB_B3_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B4_CTL] = TAPAN_A_CDC_CONN_TX_SB_B4_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B5_CTL] = TAPAN_A_CDC_CONN_TX_SB_B5_CTL__POR,
+ [TAPAN_A_CDC_CONN_TX_SB_B11_CTL] = TAPAN_A_CDC_CONN_TX_SB_B11_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX_SB_B1_CTL] = TAPAN_A_CDC_CONN_RX_SB_B1_CTL__POR,
+ [TAPAN_A_CDC_CONN_RX_SB_B2_CTL] = TAPAN_A_CDC_CONN_RX_SB_B2_CTL__POR,
+ [TAPAN_A_CDC_CONN_CLSH_CTL] = TAPAN_A_CDC_CONN_CLSH_CTL__POR,
+ [TAPAN_A_CDC_CONN_MISC] = TAPAN_A_CDC_CONN_MISC__POR,
+ [TAPAN_A_CDC_MBHC_EN_CTL] = TAPAN_A_CDC_MBHC_EN_CTL__POR,
+ [TAPAN_A_CDC_MBHC_FIR_B1_CFG] = TAPAN_A_CDC_MBHC_FIR_B1_CFG__POR,
+ [TAPAN_A_CDC_MBHC_FIR_B2_CFG] = TAPAN_A_CDC_MBHC_FIR_B2_CFG__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B1_CTL] = TAPAN_A_CDC_MBHC_TIMER_B1_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B2_CTL] = TAPAN_A_CDC_MBHC_TIMER_B2_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B3_CTL] = TAPAN_A_CDC_MBHC_TIMER_B3_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B4_CTL] = TAPAN_A_CDC_MBHC_TIMER_B4_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B5_CTL] = TAPAN_A_CDC_MBHC_TIMER_B5_CTL__POR,
+ [TAPAN_A_CDC_MBHC_TIMER_B6_CTL] = TAPAN_A_CDC_MBHC_TIMER_B6_CTL__POR,
+ [TAPAN_A_CDC_MBHC_B1_STATUS] = TAPAN_A_CDC_MBHC_B1_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B2_STATUS] = TAPAN_A_CDC_MBHC_B2_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B3_STATUS] = TAPAN_A_CDC_MBHC_B3_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B4_STATUS] = TAPAN_A_CDC_MBHC_B4_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B5_STATUS] = TAPAN_A_CDC_MBHC_B5_STATUS__POR,
+ [TAPAN_A_CDC_MBHC_B1_CTL] = TAPAN_A_CDC_MBHC_B1_CTL__POR,
+ [TAPAN_A_CDC_MBHC_B2_CTL] = TAPAN_A_CDC_MBHC_B2_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B1_CTL] = TAPAN_A_CDC_MBHC_VOLT_B1_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B2_CTL] = TAPAN_A_CDC_MBHC_VOLT_B2_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B3_CTL] = TAPAN_A_CDC_MBHC_VOLT_B3_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B4_CTL] = TAPAN_A_CDC_MBHC_VOLT_B4_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B5_CTL] = TAPAN_A_CDC_MBHC_VOLT_B5_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B6_CTL] = TAPAN_A_CDC_MBHC_VOLT_B6_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B7_CTL] = TAPAN_A_CDC_MBHC_VOLT_B7_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B8_CTL] = TAPAN_A_CDC_MBHC_VOLT_B8_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B9_CTL] = TAPAN_A_CDC_MBHC_VOLT_B9_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B10_CTL] = TAPAN_A_CDC_MBHC_VOLT_B10_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B11_CTL] = TAPAN_A_CDC_MBHC_VOLT_B11_CTL__POR,
+ [TAPAN_A_CDC_MBHC_VOLT_B12_CTL] = TAPAN_A_CDC_MBHC_VOLT_B12_CTL__POR,
+ [TAPAN_A_CDC_MBHC_CLK_CTL] = TAPAN_A_CDC_MBHC_CLK_CTL__POR,
+ [TAPAN_A_CDC_MBHC_INT_CTL] = TAPAN_A_CDC_MBHC_INT_CTL__POR,
+ [TAPAN_A_CDC_MBHC_DEBUG_CTL] = TAPAN_A_CDC_MBHC_DEBUG_CTL__POR,
+ [TAPAN_A_CDC_MBHC_SPARE] = TAPAN_A_CDC_MBHC_SPARE__POR,
+};
diff --git a/sound/soc/codecs/wcd9306.c b/sound/soc/codecs/wcd9306.c
new file mode 100644
index 0000000..b0cf27b
--- /dev/null
+++ b/sound/soc/codecs/wcd9306.c
@@ -0,0 +1,3856 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/firmware.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+#include <linux/debugfs.h>
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+#include <linux/mfd/wcd9xxx/wcd9306_registers.h>
+#include <linux/mfd/wcd9xxx/pdata.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include "wcd9306.h"
+#include "wcd9xxx-resmgr.h"
+
+#define WCD9306_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
+
+#define NUM_DECIMATORS 4
+#define NUM_INTERPOLATORS 4
+#define BITS_PER_REG 8
+#define TAPAN_TX_PORT_NUMBER 16
+
+#define TAPAN_I2S_MASTER_MODE_MASK 0x08
+
+enum {
+ AIF1_PB = 0,
+ AIF1_CAP,
+ AIF2_PB,
+ AIF2_CAP,
+ AIF3_PB,
+ AIF3_CAP,
+ NUM_CODEC_DAIS,
+};
+
+enum {
+ RX_MIX1_INP_SEL_ZERO = 0,
+ RX_MIX1_INP_SEL_SRC1,
+ RX_MIX1_INP_SEL_SRC2,
+ RX_MIX1_INP_SEL_IIR1,
+ RX_MIX1_INP_SEL_IIR2,
+ RX_MIX1_INP_SEL_RX1,
+ RX_MIX1_INP_SEL_RX2,
+ RX_MIX1_INP_SEL_RX3,
+ RX_MIX1_INP_SEL_RX4,
+ RX_MIX1_INP_SEL_RX5,
+ RX_MIX1_INP_SEL_RX6,
+ RX_MIX1_INP_SEL_RX7,
+ RX_MIX1_INP_SEL_AUXRX,
+};
+
+#define TAPAN_COMP_DIGITAL_GAIN_OFFSET 3
+
+static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
+static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
+static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
+static struct snd_soc_dai_driver tapan_dai[];
+static const DECLARE_TLV_DB_SCALE(aux_pga_gain, 0, 2, 0);
+
+/* Codec supports 2 IIR filters */
+enum {
+ IIR1 = 0,
+ IIR2,
+ IIR_MAX,
+};
+/* Codec supports 5 bands */
+enum {
+ BAND1 = 0,
+ BAND2,
+ BAND3,
+ BAND4,
+ BAND5,
+ BAND_MAX,
+};
+
+enum {
+ COMPANDER_1 = 0,
+ COMPANDER_2,
+ COMPANDER_MAX,
+};
+
+enum {
+ COMPANDER_FS_8KHZ = 0,
+ COMPANDER_FS_16KHZ,
+ COMPANDER_FS_32KHZ,
+ COMPANDER_FS_48KHZ,
+ COMPANDER_FS_96KHZ,
+ COMPANDER_FS_192KHZ,
+ COMPANDER_FS_MAX,
+};
+
+struct comp_sample_dependent_params {
+ u32 peak_det_timeout;
+ u32 rms_meter_div_fact;
+ u32 rms_meter_resamp_fact;
+};
+
+struct hpf_work {
+ struct tapan_priv *tapan;
+ u32 decimator;
+ u8 tx_hpf_cut_of_freq;
+ struct delayed_work dwork;
+};
+
+static struct hpf_work tx_hpf_work[NUM_DECIMATORS];
+
+static const struct wcd9xxx_ch tapan_rx_chs[TAPAN_RX_MAX] = {
+ WCD9XXX_CH(16, 0),
+ WCD9XXX_CH(17, 1),
+ WCD9XXX_CH(18, 2),
+ WCD9XXX_CH(19, 3),
+ WCD9XXX_CH(20, 4),
+};
+
+static const struct wcd9xxx_ch tapan_tx_chs[TAPAN_TX_MAX] = {
+ WCD9XXX_CH(0, 0),
+ WCD9XXX_CH(1, 1),
+ WCD9XXX_CH(2, 2),
+ WCD9XXX_CH(3, 3),
+ WCD9XXX_CH(4, 4),
+};
+
+static const u32 vport_check_table[NUM_CODEC_DAIS] = {
+ 0, /* AIF1_PB */
+ (1 << AIF2_CAP) | (1 << AIF3_CAP), /* AIF1_CAP */
+ 0, /* AIF2_PB */
+ (1 << AIF1_CAP) | (1 << AIF3_CAP), /* AIF2_CAP */
+ 0, /* AIF2_PB */
+ (1 << AIF1_CAP) | (1 << AIF2_CAP), /* AIF2_CAP */
+};
+
+struct tapan_priv {
+ struct snd_soc_codec *codec;
+ u32 adc_count;
+ u32 rx_bias_count;
+ s32 dmic_1_2_clk_cnt;
+ s32 dmic_3_4_clk_cnt;
+ s32 dmic_5_6_clk_cnt;
+
+ u32 anc_slot;
+
+ /*track tapan interface type*/
+ u8 intf_type;
+
+ /* num of slim ports required */
+ struct wcd9xxx_codec_dai_data dai[NUM_CODEC_DAIS];
+
+ /* Maintain the status of AUX PGA */
+ int aux_pga_cnt;
+ u8 aux_l_gain;
+ u8 aux_r_gain;
+
+ /* resmgr module */
+ struct wcd9xxx_resmgr resmgr;
+ /* mbhc module */
+ struct wcd9xxx_mbhc mbhc;
+};
+
+static const u32 comp_shift[] = {
+ 0,
+ 2,
+};
+
+static unsigned short rx_digital_gain_reg[] = {
+ TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL,
+ TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL,
+ TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL,
+ TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL,
+};
+
+static unsigned short tx_digital_gain_reg[] = {
+ TAPAN_A_CDC_TX1_VOL_CTL_GAIN,
+ TAPAN_A_CDC_TX2_VOL_CTL_GAIN,
+ TAPAN_A_CDC_TX3_VOL_CTL_GAIN,
+ TAPAN_A_CDC_TX4_VOL_CTL_GAIN,
+};
+
+static int tapan_codec_enable_class_h_clk(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLSH_B1_CTL, 0x01, 0x01);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x80, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLSH_B1_CTL, 0x01, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_class_h(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_5, 0x02, 0x02);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_4, 0xFF, 0xFF);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x04, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x04, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x08, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_1, 0x80, 0x80);
+ usleep_range(1000, 1000);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x01, 0x01);
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x0f, 0x01);
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(1000, 1000);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x01, 0x00);
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x0f, 0x08);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_pa_gain_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ u8 ear_pa_gain;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ear_pa_gain = snd_soc_read(codec, TAPAN_A_RX_EAR_GAIN);
+
+ ear_pa_gain = ear_pa_gain >> 5;
+
+ if (ear_pa_gain == 0x00) {
+ ucontrol->value.integer.value[0] = 0;
+ } else if (ear_pa_gain == 0x04) {
+ ucontrol->value.integer.value[0] = 1;
+ } else {
+ pr_err("%s: ERROR: Unsupported Ear Gain = 0x%x\n",
+ __func__, ear_pa_gain);
+ return -EINVAL;
+ }
+
+ dev_dbg(codec->dev, "%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain);
+
+ return 0;
+}
+
+static int tapan_pa_gain_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ u8 ear_pa_gain;
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
+ __func__, ucontrol->value.integer.value[0]);
+
+ switch (ucontrol->value.integer.value[0]) {
+ case 0:
+ ear_pa_gain = 0x00;
+ break;
+ case 1:
+ ear_pa_gain = 0x80;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ snd_soc_update_bits(codec, TAPAN_A_RX_EAR_GAIN, 0xE0, ear_pa_gain);
+ return 0;
+}
+
+static int tapan_get_iir_enable_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_read(codec, (TAPAN_A_CDC_IIR1_CTL + 16 * iir_idx)) &
+ (1 << band_idx);
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__,
+ iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[0]);
+ return 0;
+}
+
+static int tapan_put_iir_enable_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+ int value = ucontrol->value.integer.value[0];
+
+ /* Mask first 5 bits, 6-8 are reserved */
+ snd_soc_update_bits(codec, (TAPAN_A_CDC_IIR1_CTL + 16 * iir_idx),
+ (1 << band_idx), (value << band_idx));
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__,
+ iir_idx, band_idx, value);
+ return 0;
+}
+static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec,
+ int iir_idx, int band_idx,
+ int coeff_idx)
+{
+ /* Address does not automatically update if reading */
+ snd_soc_write(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
+ (band_idx * BAND_MAX + coeff_idx) & 0x1F);
+
+ /* Mask bits top 2 bits since they are reserved */
+ return ((snd_soc_read(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx)) << 24)) &
+ 0x3FFFFFFF;
+}
+
+static int tapan_get_iir_band_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ ucontrol->value.integer.value[0] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 0);
+ ucontrol->value.integer.value[1] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 1);
+ ucontrol->value.integer.value[2] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 2);
+ ucontrol->value.integer.value[3] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 3);
+ ucontrol->value.integer.value[4] =
+ get_iir_band_coeff(codec, iir_idx, band_idx, 4);
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n"
+ "%s: IIR #%d band #%d b1 = 0x%x\n"
+ "%s: IIR #%d band #%d b2 = 0x%x\n"
+ "%s: IIR #%d band #%d a1 = 0x%x\n"
+ "%s: IIR #%d band #%d a2 = 0x%x\n",
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[0],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[1],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[2],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[3],
+ __func__, iir_idx, band_idx,
+ (uint32_t)ucontrol->value.integer.value[4]);
+ return 0;
+}
+
+static void set_iir_band_coeff(struct snd_soc_codec *codec,
+ int iir_idx, int band_idx,
+ int coeff_idx, uint32_t value)
+{
+ /* Mask top 3 bits, 6-8 are reserved */
+ /* Update address manually each time */
+ snd_soc_write(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
+ (band_idx * BAND_MAX + coeff_idx) & 0x1F);
+
+ /* Mask top 2 bits, 7-8 are reserved */
+ snd_soc_write(codec,
+ (TAPAN_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx),
+ (value >> 24) & 0x3F);
+
+}
+
+static int tapan_put_iir_band_audio_mixer(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int iir_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->reg;
+ int band_idx = ((struct soc_multi_mixer_control *)
+ kcontrol->private_value)->shift;
+
+ set_iir_band_coeff(codec, iir_idx, band_idx, 0,
+ ucontrol->value.integer.value[0]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 1,
+ ucontrol->value.integer.value[1]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 2,
+ ucontrol->value.integer.value[2]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 3,
+ ucontrol->value.integer.value[3]);
+ set_iir_band_coeff(codec, iir_idx, band_idx, 4,
+ ucontrol->value.integer.value[4]);
+
+ dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n"
+ "%s: IIR #%d band #%d b1 = 0x%x\n"
+ "%s: IIR #%d band #%d b2 = 0x%x\n"
+ "%s: IIR #%d band #%d a1 = 0x%x\n"
+ "%s: IIR #%d band #%d a2 = 0x%x\n",
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 0),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 1),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 2),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 3),
+ __func__, iir_idx, band_idx,
+ get_iir_band_coeff(codec, iir_idx, band_idx, 4));
+ return 0;
+}
+
+static const char * const tapan_ear_pa_gain_text[] = {"POS_6_DB", "POS_2_DB"};
+static const struct soc_enum tapan_ear_pa_gain_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, tapan_ear_pa_gain_text),
+};
+
+/*cut of frequency for high pass filter*/
+static const char * const cf_text[] = {
+ "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
+};
+
+static const struct soc_enum cf_dec1_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec2_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec3_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX3_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec4_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_TX4_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_rxmix1_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX1_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix2_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX2_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix3_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX3_B4_CTL, 1, 3, cf_text);
+
+static const struct soc_enum cf_rxmix4_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_RX4_B4_CTL, 1, 3, cf_text);
+
+static const struct snd_kcontrol_new tapan_snd_controls[] = {
+
+ SOC_ENUM_EXT("EAR PA Gain", tapan_ear_pa_gain_enum[0],
+ tapan_pa_gain_get, tapan_pa_gain_put),
+
+ SOC_SINGLE_TLV("LINEOUT1 Volume", TAPAN_A_RX_LINE_1_GAIN, 0, 12, 1,
+ line_gain),
+ SOC_SINGLE_TLV("LINEOUT2 Volume", TAPAN_A_RX_LINE_2_GAIN, 0, 12, 1,
+ line_gain),
+
+ SOC_SINGLE_TLV("HPHL Volume", TAPAN_A_RX_HPH_L_GAIN, 0, 12, 1,
+ line_gain),
+ SOC_SINGLE_TLV("HPHR Volume", TAPAN_A_RX_HPH_R_GAIN, 0, 12, 1,
+ line_gain),
+
+ SOC_SINGLE_S8_TLV("RX1 Digital Volume", TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX2 Digital Volume", TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX3 Digital Volume", TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX4 Digital Volume", TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL,
+ -84, 40, digital_gain),
+
+ SOC_SINGLE_S8_TLV("DEC1 Volume", TAPAN_A_CDC_TX1_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+ SOC_SINGLE_S8_TLV("DEC2 Volume", TAPAN_A_CDC_TX2_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+ SOC_SINGLE_S8_TLV("DEC3 Volume", TAPAN_A_CDC_TX3_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+ SOC_SINGLE_S8_TLV("DEC4 Volume", TAPAN_A_CDC_TX4_VOL_CTL_GAIN, -84, 40,
+ digital_gain),
+
+ SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", TAPAN_A_CDC_IIR1_GAIN_B1_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", TAPAN_A_CDC_IIR1_GAIN_B2_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", TAPAN_A_CDC_IIR1_GAIN_B3_CTL, -84,
+ 40, digital_gain),
+ SOC_SINGLE_S8_TLV("IIR1 INP4 Volume", TAPAN_A_CDC_IIR1_GAIN_B4_CTL, -84,
+ 40, digital_gain),
+
+ SOC_SINGLE("MICBIAS1 CAPLESS Switch", TAPAN_A_MICB_1_CTL, 4, 1, 1),
+ SOC_SINGLE("MICBIAS2 CAPLESS Switch", TAPAN_A_MICB_2_CTL, 4, 1, 1),
+ SOC_SINGLE("MICBIAS3 CAPLESS Switch", TAPAN_A_MICB_3_CTL, 4, 1, 1),
+
+ SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
+ SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
+ SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
+ SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
+
+ SOC_SINGLE("TX1 HPF Switch", TAPAN_A_CDC_TX1_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX2 HPF Switch", TAPAN_A_CDC_TX2_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX3 HPF Switch", TAPAN_A_CDC_TX3_MUX_CTL, 3, 1, 0),
+ SOC_SINGLE("TX4 HPF Switch", TAPAN_A_CDC_TX4_MUX_CTL, 3, 1, 0),
+
+ SOC_SINGLE("RX1 HPF Switch", TAPAN_A_CDC_RX1_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX2 HPF Switch", TAPAN_A_CDC_RX2_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX3 HPF Switch", TAPAN_A_CDC_RX3_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX4 HPF Switch", TAPAN_A_CDC_RX4_B5_CTL, 2, 1, 0),
+
+ SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
+ SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
+ SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
+ SOC_ENUM("RX4 HPF cut off", cf_rxmix4_enum),
+
+ SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+ SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0,
+ tapan_get_iir_enable_audio_mixer, tapan_put_iir_enable_audio_mixer),
+
+ SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+ SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5,
+ tapan_get_iir_band_audio_mixer, tapan_put_iir_band_audio_mixer),
+
+};
+
+static const char * const rx_mix1_text[] = {
+ "ZERO", "SRC1", "SRC2", "IIR1", "IIR2", "RX1", "RX2", "RX3", "RX4",
+ "RX5", "RX6", "RX7"
+};
+
+static const char * const rx_mix2_text[] = {
+ "ZERO", "SRC1", "SRC2", "IIR1", "IIR2"
+};
+
+static const char * const rx_rdac5_text[] = {
+ "DEM4", "DEM3_INV"
+};
+
+static const char * const rx_rdac7_text[] = {
+ "DEM6", "DEM5_INV"
+};
+
+static const char * const sb_tx1_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC1"
+};
+
+static const char * const sb_tx2_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC2"
+};
+
+static const char * const sb_tx3_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC3"
+};
+
+static const char * const sb_tx4_mux_text[] = {
+ "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
+ "DEC4"
+};
+
+static const char * const dec1_mux_text[] = {
+ "ZERO", "DMIC1", "ADC6",
+};
+
+static const char * const dec2_mux_text[] = {
+ "ZERO", "DMIC2", "ADC5",
+};
+
+static const char * const dec3_mux_text[] = {
+ "ZERO", "DMIC3", "ADC4",
+};
+
+static const char * const dec4_mux_text[] = {
+ "ZERO", "DMIC4", "ADC3",
+};
+
+static const char * const anc_mux_text[] = {
+ "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC_MB",
+ "RSVD_1", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", "DMIC6"
+};
+
+static const char * const anc1_fb_mux_text[] = {
+ "ZERO", "EAR_HPH_L", "EAR_LINE_1",
+};
+
+static const char * const iir1_inp1_text[] = {
+ "ZERO", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", "DEC7", "DEC8",
+ "DEC9", "DEC10", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
+};
+
+static const struct soc_enum rx_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp3_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B2_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx3_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX3_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx3_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX3_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx4_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX4_B1_CTL, 0, 12, rx_mix1_text);
+
+static const struct soc_enum rx4_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX4_B1_CTL, 4, 12, rx_mix1_text);
+
+static const struct soc_enum rx1_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B3_CTL, 0, 5, rx_mix2_text);
+
+static const struct soc_enum rx1_mix2_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B3_CTL, 3, 5, rx_mix2_text);
+
+static const struct soc_enum rx2_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B3_CTL, 0, 5, rx_mix2_text);
+
+static const struct soc_enum rx2_mix2_inp2_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX2_B3_CTL, 3, 5, rx_mix2_text);
+
+static const struct soc_enum rx_rdac5_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_MISC, 2, 2, rx_rdac5_text);
+
+static const struct soc_enum rx_rdac7_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_MISC, 1, 2, rx_rdac7_text);
+
+static const struct soc_enum sb_tx1_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
+
+static const struct soc_enum sb_tx2_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B2_CTL, 0, 9, sb_tx2_mux_text);
+
+static const struct soc_enum sb_tx3_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B3_CTL, 0, 9, sb_tx3_mux_text);
+
+static const struct soc_enum sb_tx4_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_SB_B4_CTL, 0, 9, sb_tx4_mux_text);
+
+static const struct soc_enum dec1_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 0, 3, dec1_mux_text);
+
+static const struct soc_enum dec2_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 2, 3, dec2_mux_text);
+
+static const struct soc_enum dec3_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 4, 3, dec3_mux_text);
+
+static const struct soc_enum dec4_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_TX_B1_CTL, 6, 3, dec4_mux_text);
+
+static const struct soc_enum iir1_inp1_mux_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_EQ1_B1_CTL, 0, 18, iir1_inp1_text);
+
+static const struct snd_kcontrol_new rx_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp3_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx4_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX4 MIX1 INP1 Mux", rx4_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx4_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX4 MIX1 INP2 Mux", rx4_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx1_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix2_inp2_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP2 Mux", rx1_mix2_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp2_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP2 Mux", rx2_mix2_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx_dac5_mux =
+ SOC_DAPM_ENUM("RDAC5 MUX Mux", rx_rdac5_enum);
+
+static const struct snd_kcontrol_new sb_tx1_mux =
+ SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx2_mux =
+ SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx3_mux =
+ SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
+
+static const struct snd_kcontrol_new sb_tx4_mux =
+ SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
+
+/*static const struct snd_kcontrol_new sb_tx5_mux =
+ SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
+*/
+
+static int wcd9306_put_dec_enum(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *w = wlist->widgets[0];
+ struct snd_soc_codec *codec = w->codec;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int dec_mux, decimator;
+ char *dec_name = NULL;
+ char *widget_name = NULL;
+ char *temp;
+ u16 tx_mux_ctl_reg;
+ u8 adc_dmic_sel = 0x0;
+ int ret = 0;
+
+ if (ucontrol->value.enumerated.item[0] > e->max - 1)
+ return -EINVAL;
+
+ dec_mux = ucontrol->value.enumerated.item[0];
+
+ widget_name = kstrndup(w->name, 15, GFP_KERNEL);
+ if (!widget_name)
+ return -ENOMEM;
+ temp = widget_name;
+
+ dec_name = strsep(&widget_name, " ");
+ widget_name = temp;
+ if (!dec_name) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = kstrtouint(strpbrk(dec_name, "1234"), 10, &decimator);
+ if (ret < 0) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n"
+ , __func__, w->name, decimator, dec_mux);
+
+ switch (decimator) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ if (dec_mux == 1)
+ adc_dmic_sel = 0x1;
+ else
+ adc_dmic_sel = 0x0;
+ break;
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ if ((dec_mux == 1) || (dec_mux == 2))
+ adc_dmic_sel = 0x1;
+ else
+ adc_dmic_sel = 0x0;
+ break;
+ default:
+ pr_err("%s: Invalid Decimator = %u\n", __func__, decimator);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ tx_mux_ctl_reg = TAPAN_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
+
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel);
+
+ ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
+
+out:
+ kfree(widget_name);
+ return ret;
+}
+
+#define WCD9306_DEC_ENUM(xname, xenum) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .info = snd_soc_info_enum_double, \
+ .get = snd_soc_dapm_get_enum_double, \
+ .put = wcd9306_put_dec_enum, \
+ .private_value = (unsigned long)&xenum }
+
+static const struct snd_kcontrol_new dec1_mux =
+ WCD9306_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum);
+
+static const struct snd_kcontrol_new dec2_mux =
+ WCD9306_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum);
+
+static const struct snd_kcontrol_new dec3_mux =
+ WCD9306_DEC_ENUM("DEC3 MUX Mux", dec3_mux_enum);
+
+static const struct snd_kcontrol_new dec4_mux =
+ WCD9306_DEC_ENUM("DEC4 MUX Mux", dec4_mux_enum);
+
+static const struct snd_kcontrol_new iir1_inp1_mux =
+ SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
+
+static const struct snd_kcontrol_new dac1_switch[] = {
+ SOC_DAPM_SINGLE("Switch", TAPAN_A_RX_EAR_EN, 5, 1, 0)
+};
+static const struct snd_kcontrol_new hphl_switch[] = {
+ SOC_DAPM_SINGLE("Switch", TAPAN_A_RX_HPH_L_DAC_CTL, 6, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphl_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 7, 1, 0),
+};
+
+static const struct snd_kcontrol_new hphr_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 6, 1, 0),
+};
+
+static const struct snd_kcontrol_new ear_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 5, 1, 0),
+};
+static const struct snd_kcontrol_new lineout1_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 4, 1, 0),
+};
+
+static const struct snd_kcontrol_new lineout2_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 3, 1, 0),
+};
+
+static const struct snd_kcontrol_new lineout3_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 2, 1, 0),
+};
+
+static const struct snd_kcontrol_new lineout4_pa_mix[] = {
+ SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAPAN_A_RX_PA_AUX_IN_CONN,
+ 1, 1, 0),
+};
+
+/* virtual port entries */
+static int slim_tx_mixer_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+
+ ucontrol->value.integer.value[0] = widget->value;
+ return 0;
+}
+
+static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+ struct snd_soc_codec *codec = widget->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
+ struct soc_multi_mixer_control *mixer =
+ ((struct soc_multi_mixer_control *)kcontrol->private_value);
+ u32 dai_id = widget->shift;
+ u32 port_id = mixer->shift;
+ u32 enable = ucontrol->value.integer.value[0];
+
+ dev_dbg(codec->dev, "%s: wname %s cname %s\n",
+ __func__, widget->name, ucontrol->id.name);
+ dev_dbg(codec->dev, "%s: value %u shift %d item %ld\n",
+ __func__, widget->value, widget->shift,
+ ucontrol->value.integer.value[0]);
+
+ mutex_lock(&codec->mutex);
+
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ if (dai_id != AIF1_CAP) {
+ dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
+ __func__);
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+ }
+ }
+ switch (dai_id) {
+ case AIF1_CAP:
+ case AIF2_CAP:
+ case AIF3_CAP:
+ /* only add to the list if value not set
+ */
+ if (enable && !(widget->value & 1 << port_id)) {
+ if (wcd9xxx_tx_vport_validation(
+ vport_check_table[dai_id],
+ port_id,
+ tapan_p->dai)) {
+ dev_dbg(codec->dev, "%s: TX%u is used by other virtual port\n",
+ __func__, port_id + 1);
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+ }
+ widget->value |= 1 << port_id;
+ list_add_tail(&core->tx_chs[port_id].list,
+ &tapan_p->dai[dai_id].wcd9xxx_ch_list
+ );
+ } else if (!enable && (widget->value & 1 << port_id)) {
+ widget->value &= ~(1 << port_id);
+ list_del_init(&core->tx_chs[port_id].list);
+ } else {
+ if (enable)
+ dev_dbg(codec->dev, "%s: TX%u port is used by this virtual port\n",
+ __func__, port_id + 1);
+ else
+ dev_dbg(codec->dev, "%s: TX%u port is not used by this virtual port\n",
+ __func__, port_id + 1);
+ /* avoid update power function */
+ mutex_unlock(&codec->mutex);
+ return 0;
+ }
+ break;
+ default:
+ pr_err("Unknown AIF %d\n", dai_id);
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+ }
+ dev_dbg(codec->dev, "%s: name %s sname %s updated value %u shift %d\n",
+ __func__, widget->name, widget->sname,
+ widget->value, widget->shift);
+
+ snd_soc_dapm_mixer_update_power(widget, kcontrol, enable);
+
+ mutex_unlock(&codec->mutex);
+ return 0;
+}
+
+static int slim_rx_mux_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+
+ ucontrol->value.enumerated.item[0] = widget->value;
+ return 0;
+}
+
+static const char *const slim_rx_mux_text[] = {
+ "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB"
+};
+
+static int slim_rx_mux_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+ struct snd_soc_codec *codec = widget->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ u32 port_id = widget->shift;
+
+ dev_dbg(codec->dev, "%s: wname %s cname %s value %u shift %d item %ld\n",
+ __func__, widget->name, ucontrol->id.name, widget->value,
+ widget->shift, ucontrol->value.integer.value[0]);
+
+ widget->value = ucontrol->value.enumerated.item[0];
+
+ mutex_lock(&codec->mutex);
+
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ if (widget->value > 1) {
+ dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
+ __func__);
+ goto err;
+ }
+ }
+ /* value need to match the Virtual port and AIF number
+ */
+ switch (widget->value) {
+ case 0:
+ list_del_init(&core->rx_chs[port_id].list);
+ break;
+ case 1:
+ if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list))
+ goto pr_err;
+ list_add_tail(&core->rx_chs[port_id].list,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list);
+ break;
+ case 2:
+ if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list))
+ goto pr_err;
+ list_add_tail(&core->rx_chs[port_id].list,
+ &tapan_p->dai[AIF2_PB].wcd9xxx_ch_list);
+ break;
+ case 3:
+ if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
+ &tapan_p->dai[AIF1_PB].wcd9xxx_ch_list))
+ goto pr_err;
+ list_add_tail(&core->rx_chs[port_id].list,
+ &tapan_p->dai[AIF3_PB].wcd9xxx_ch_list);
+ break;
+ default:
+ pr_err("Unknown AIF %d\n", widget->value);
+ goto err;
+ }
+
+ snd_soc_dapm_mux_update_power(widget, kcontrol, 1, widget->value, e);
+
+ mutex_unlock(&codec->mutex);
+ return 0;
+pr_err:
+ pr_err("%s: RX%u is used by current requesting AIF_PB itself\n",
+ __func__, port_id + 1);
+err:
+ mutex_unlock(&codec->mutex);
+ return -EINVAL;
+}
+
+static const struct soc_enum slim_rx_mux_enum =
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
+
+static const struct snd_kcontrol_new slim_rx_mux[TAPAN_RX_MAX] = {
+ SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+ SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
+ slim_rx_mux_get, slim_rx_mux_put),
+};
+
+static const struct snd_kcontrol_new aif_cap_mixer[] = {
+ SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, TAPAN_TX1, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, TAPAN_TX2, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, TAPAN_TX3, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, TAPAN_TX4, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+ SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, TAPAN_TX5, 1, 0,
+ slim_tx_mixer_get, slim_tx_mixer_put),
+};
+
+static int tapan_codec_enable_aux_pga(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s: %d\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ WCD9XXX_BCL_LOCK(&tapan->resmgr);
+ wcd9xxx_resmgr_get_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ /* AUX PGA requires RCO or MCLK */
+ wcd9xxx_resmgr_get_clk_block(&tapan->resmgr, WCD9XXX_CLK_RCO);
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 1);
+ WCD9XXX_BCL_UNLOCK(&tapan->resmgr);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ WCD9XXX_BCL_LOCK(&tapan->resmgr);
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 0);
+ wcd9xxx_resmgr_put_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ wcd9xxx_resmgr_put_clk_block(&tapan->resmgr, WCD9XXX_CLK_RCO);
+ WCD9XXX_BCL_UNLOCK(&tapan->resmgr);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_lineout(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ u16 lineout_gain_reg;
+
+ dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
+
+ switch (w->shift) {
+ case 0:
+ lineout_gain_reg = TAPAN_A_RX_LINE_1_GAIN;
+ break;
+ case 1:
+ lineout_gain_reg = TAPAN_A_RX_LINE_2_GAIN;
+ break;
+ default:
+ pr_err("%s: Error, incorrect lineout register value\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x40);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ dev_dbg(codec->dev, "%s: sleeping 16 ms after %s PA turn on\n",
+ __func__, w->name);
+ usleep_range(16000, 16000);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ dev_dbg(w->codec->dev, "%s %d %s\n", __func__, event, w->name);
+ return 0;
+}
+
+static int tapan_codec_enable_dmic(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u8 dmic_clk_en;
+ u16 dmic_clk_reg;
+ s32 *dmic_clk_cnt;
+ unsigned int dmic;
+ int ret;
+
+ ret = kstrtouint(strpbrk(w->name, "123456"), 10, &dmic);
+ if (ret < 0) {
+ pr_err("%s: Invalid DMIC line on the codec\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (dmic) {
+ case 1:
+ case 2:
+ dmic_clk_en = 0x01;
+ dmic_clk_cnt = &(tapan->dmic_1_2_clk_cnt);
+ dmic_clk_reg = TAPAN_A_CDC_CLK_DMIC_B1_CTL;
+ dev_dbg(codec->dev, "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n",
+ __func__, event, dmic, *dmic_clk_cnt);
+
+ break;
+
+ case 3:
+ case 4:
+ dmic_clk_en = 0x10;
+ dmic_clk_cnt = &(tapan->dmic_3_4_clk_cnt);
+ dmic_clk_reg = TAPAN_A_CDC_CLK_DMIC_B1_CTL;
+
+ dev_dbg(codec->dev, "%s() event %d DMIC%d dmic_3_4_clk_cnt %d\n",
+ __func__, event, dmic, *dmic_clk_cnt);
+ break;
+
+ case 5:
+ case 6:
+ dmic_clk_en = 0x01;
+ dmic_clk_cnt = &(tapan->dmic_5_6_clk_cnt);
+ dmic_clk_reg = TAPAN_A_CDC_CLK_DMIC_B2_CTL;
+
+ dev_dbg(codec->dev, "%s() event %d DMIC%d dmic_5_6_clk_cnt %d\n",
+ __func__, event, dmic, *dmic_clk_cnt);
+
+ break;
+
+ default:
+ pr_err("%s: Invalid DMIC Selection\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+
+ (*dmic_clk_cnt)++;
+ if (*dmic_clk_cnt == 1)
+ snd_soc_update_bits(codec, dmic_clk_reg,
+ dmic_clk_en, dmic_clk_en);
+
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+
+ (*dmic_clk_cnt)--;
+ if (*dmic_clk_cnt == 0)
+ snd_soc_update_bits(codec, dmic_clk_reg,
+ dmic_clk_en, 0);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_anc(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ const char *filename;
+ const struct firmware *fw;
+ int i;
+ int ret;
+ int num_anc_slots;
+ struct anc_header *anc_head;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u32 anc_writes_size = 0;
+ int anc_size_remaining;
+ u32 *anc_ptr;
+ u16 reg;
+ u8 mask, val;
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+
+ filename = "wcd9306/wcd9306_anc.bin";
+
+ ret = request_firmware(&fw, filename, codec->dev);
+ if (ret != 0) {
+ dev_err(codec->dev, "Failed to acquire ANC data: %d\n",
+ ret);
+ return -ENODEV;
+ }
+
+ if (fw->size < sizeof(struct anc_header)) {
+ dev_err(codec->dev, "Not enough data\n");
+ release_firmware(fw);
+ return -ENOMEM;
+ }
+
+ /* First number is the number of register writes */
+ anc_head = (struct anc_header *)(fw->data);
+ anc_ptr = (u32 *)((u32)fw->data + sizeof(struct anc_header));
+ anc_size_remaining = fw->size - sizeof(struct anc_header);
+ num_anc_slots = anc_head->num_anc_slots;
+
+ if (tapan->anc_slot >= num_anc_slots) {
+ dev_err(codec->dev, "Invalid ANC slot selected\n");
+ release_firmware(fw);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_anc_slots; i++) {
+
+ if (anc_size_remaining < TAPAN_PACKED_REG_SIZE) {
+ dev_err(codec->dev, "Invalid register format\n");
+ release_firmware(fw);
+ return -EINVAL;
+ }
+ anc_writes_size = (u32)(*anc_ptr);
+ anc_size_remaining -= sizeof(u32);
+ anc_ptr += 1;
+
+ if (anc_writes_size * TAPAN_PACKED_REG_SIZE
+ > anc_size_remaining) {
+ dev_err(codec->dev, "Invalid register format\n");
+ release_firmware(fw);
+ return -ENOMEM;
+ }
+
+ if (tapan->anc_slot == i)
+ break;
+
+ anc_size_remaining -= (anc_writes_size *
+ TAPAN_PACKED_REG_SIZE);
+ anc_ptr += anc_writes_size;
+ }
+ if (i == num_anc_slots) {
+ dev_err(codec->dev, "Selected ANC slot not present\n");
+ release_firmware(fw);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < anc_writes_size; i++) {
+ TAPAN_CODEC_UNPACK_ENTRY(anc_ptr[i], reg,
+ mask, val);
+ snd_soc_write(codec, reg, val);
+ }
+ release_firmware(fw);
+
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_write(codec, TAPAN_A_CDC_CLK_ANC_RESET_CTL, 0xFF);
+ snd_soc_write(codec, TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL, 0);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_micbias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u16 micb_int_reg;
+ u8 cfilt_sel_val = 0;
+ char *internal1_text = "Internal1";
+ char *internal2_text = "Internal2";
+ char *internal3_text = "Internal3";
+ enum wcd9xxx_notify_event e_post_off, e_pre_on, e_post_on;
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+ switch (w->reg) {
+ case TAPAN_A_MICB_1_CTL:
+ micb_int_reg = TAPAN_A_MICB_1_INT_RBIAS;
+ cfilt_sel_val = tapan->resmgr.pdata->micbias.bias1_cfilt_sel;
+ e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_1_ON;
+ e_post_on = WCD9XXX_EVENT_POST_MICBIAS_1_ON;
+ e_post_off = WCD9XXX_EVENT_POST_MICBIAS_1_OFF;
+ break;
+ case TAPAN_A_MICB_2_CTL:
+ micb_int_reg = TAPAN_A_MICB_2_INT_RBIAS;
+ cfilt_sel_val = tapan->resmgr.pdata->micbias.bias2_cfilt_sel;
+ e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_2_ON;
+ e_post_on = WCD9XXX_EVENT_POST_MICBIAS_2_ON;
+ e_post_off = WCD9XXX_EVENT_POST_MICBIAS_2_OFF;
+ break;
+ case TAPAN_A_MICB_3_CTL:
+ micb_int_reg = TAPAN_A_MICB_3_INT_RBIAS;
+ cfilt_sel_val = tapan->resmgr.pdata->micbias.bias3_cfilt_sel;
+ e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_3_ON;
+ e_post_on = WCD9XXX_EVENT_POST_MICBIAS_3_ON;
+ e_post_off = WCD9XXX_EVENT_POST_MICBIAS_3_OFF;
+ break;
+ default:
+ pr_err("%s: Error, invalid micbias register\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Let MBHC module know so micbias switch to be off */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_pre_on);
+
+ /* Get cfilt */
+ wcd9xxx_resmgr_cfilt_get(&tapan->resmgr, cfilt_sel_val);
+
+ if (strnstr(w->name, internal1_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0xE0, 0xE0);
+ else if (strnstr(w->name, internal2_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x1C, 0x1C);
+ else if (strnstr(w->name, internal3_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x3, 0x3);
+
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(20000, 20000);
+ /* Let MBHC module know so micbias is on */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_on);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ /* Let MBHC module know so micbias switch to be off */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_off);
+
+ if (strnstr(w->name, internal1_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x00);
+ else if (strnstr(w->name, internal2_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x00);
+ else if (strnstr(w->name, internal3_text, 30))
+ snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
+
+ /* Put cfilt */
+ wcd9xxx_resmgr_cfilt_put(&tapan->resmgr, cfilt_sel_val);
+ break;
+ }
+
+ return 0;
+}
+
+static void tx_hpf_corner_freq_callback(struct work_struct *work)
+{
+ struct delayed_work *hpf_delayed_work;
+ struct hpf_work *hpf_work;
+ struct tapan_priv *tapan;
+ struct snd_soc_codec *codec;
+ u16 tx_mux_ctl_reg;
+ u8 hpf_cut_of_freq;
+
+ hpf_delayed_work = to_delayed_work(work);
+ hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
+ tapan = hpf_work->tapan;
+ codec = hpf_work->tapan->codec;
+ hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq;
+
+ tx_mux_ctl_reg = TAPAN_A_CDC_TX1_MUX_CTL +
+ (hpf_work->decimator - 1) * 8;
+
+ dev_dbg(codec->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n",
+ __func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq);
+
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4);
+}
+
+#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30
+#define CF_MIN_3DB_4HZ 0x0
+#define CF_MIN_3DB_75HZ 0x1
+#define CF_MIN_3DB_150HZ 0x2
+
+static int tapan_codec_enable_dec(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ unsigned int decimator;
+ char *dec_name = NULL;
+ char *widget_name = NULL;
+ char *temp;
+ int ret = 0;
+ u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
+ u8 dec_hpf_cut_of_freq;
+ int offset;
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+
+ widget_name = kstrndup(w->name, 15, GFP_KERNEL);
+ if (!widget_name)
+ return -ENOMEM;
+ temp = widget_name;
+
+ dec_name = strsep(&widget_name, " ");
+ widget_name = temp;
+ if (!dec_name) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = kstrtouint(strpbrk(dec_name, "123456789"), 10, &decimator);
+ if (ret < 0) {
+ pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ dev_dbg(codec->dev, "%s(): widget = %s dec_name = %s decimator = %u\n",
+ __func__, w->name, dec_name, decimator);
+
+ if (w->reg == TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL) {
+ dec_reset_reg = TAPAN_A_CDC_CLK_TX_RESET_B1_CTL;
+ offset = 0;
+ } else if (w->reg == TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL) {
+ dec_reset_reg = TAPAN_A_CDC_CLK_TX_RESET_B2_CTL;
+ offset = 8;
+ } else {
+ pr_err("%s: Error, incorrect dec\n", __func__);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ tx_vol_ctl_reg = TAPAN_A_CDC_TX1_VOL_CTL_CFG + 8 * (decimator - 1);
+ tx_mux_ctl_reg = TAPAN_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+
+ /* Enableable TX digital mute */
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
+
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
+ 1 << w->shift);
+ snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
+
+ dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg);
+
+ dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4;
+
+ tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq =
+ dec_hpf_cut_of_freq;
+
+ if ((dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ)) {
+
+ /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
+ CF_MIN_3DB_150HZ << 4);
+ }
+
+ /* enable HPF */
+ snd_soc_update_bits(codec, tx_mux_ctl_reg , 0x08, 0x00);
+
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+
+ /* Disable TX digital mute */
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
+
+ if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq !=
+ CF_MIN_3DB_150HZ) {
+
+ schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork,
+ msecs_to_jiffies(300));
+ }
+ /* apply the digital gain after the decimator is enabled*/
+ if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg))
+ snd_soc_write(codec,
+ tx_digital_gain_reg[w->shift + offset],
+ snd_soc_read(codec,
+ tx_digital_gain_reg[w->shift + offset])
+ );
+
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+
+ snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
+ cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
+ snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
+ (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4);
+
+ break;
+ }
+out:
+ kfree(widget_name);
+ return ret;
+}
+
+static int tapan_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 1 << w->shift);
+ snd_soc_update_bits(codec, TAPAN_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 0x0);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ /* apply the digital gain after the interpolator is enabled*/
+ if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
+ snd_soc_write(codec,
+ rx_digital_gain_reg[w->shift],
+ snd_soc_read(codec,
+ rx_digital_gain_reg[w->shift])
+ );
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_ldo_h(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ case SND_SOC_DAPM_POST_PMD:
+ usleep_range(1000, 1000);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s %d\n", __func__, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 1);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ wcd9xxx_resmgr_enable_rx_bias(&tapan->resmgr, 0);
+ break;
+ }
+ return 0;
+}
+static int tapan_hphr_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_hph_pa_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ enum wcd9xxx_notify_event e_pre_on, e_post_off;
+
+ dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event);
+ if (w->shift == 5) {
+ e_pre_on = WCD9XXX_EVENT_PRE_HPHR_PA_ON;
+ e_post_off = WCD9XXX_EVENT_POST_HPHR_PA_OFF;
+ } else if (w->shift == 4) {
+ e_pre_on = WCD9XXX_EVENT_PRE_HPHL_PA_ON;
+ e_post_off = WCD9XXX_EVENT_POST_HPHL_PA_OFF;
+ } else {
+ pr_err("%s: Invalid w->shift %d\n", __func__, w->shift);
+ return -EINVAL;
+ }
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /* Let MBHC module know PA is turning on */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_pre_on);
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(10000, 10000);
+
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_5, 0x02, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x20, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x08, 0x00);
+
+ usleep_range(10, 10);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ /* Let MBHC module know PA turned off */
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_off);
+
+ /*
+ * schedule work is required because at the time HPH PA DAPM
+ * event callback is called by DAPM framework, CODEC dapm mutex
+ * would have been locked while snd_soc_jack_report also
+ * attempts to acquire same lock.
+ */
+ dev_dbg(codec->dev, "%s: sleep 10 ms after %s PA disable.\n",
+ __func__, w->name);
+ usleep_range(5000, 5000);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_lineout_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
+ break;
+
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int tapan_spk_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+ return 0;
+}
+
+static const struct snd_soc_dapm_route audio_i2s_map[] = {
+ {"RX_I2S_CLK", NULL, "CDC_CONN"},
+ {"SLIM RX1", NULL, "RX_I2S_CLK"},
+ {"SLIM RX2", NULL, "RX_I2S_CLK"},
+
+ {"SLIM TX1 MUX", NULL, "TX_I2S_CLK"},
+ {"SLIM TX2 MUX", NULL, "TX_I2S_CLK"},
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+ /* SLIMBUS Connections */
+ {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
+ {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
+ {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
+
+ /* SLIM_MIXER("AIF1_CAP Mixer"),*/
+ {"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
+ {"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
+ /* SLIM_MIXER("AIF2_CAP Mixer"),*/
+ {"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
+ {"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
+ /* SLIM_MIXER("AIF3_CAP Mixer"),*/
+ {"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
+ {"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
+
+ {"SLIM TX1 MUX", "DEC1", "DEC1 MUX"},
+
+ {"SLIM TX2 MUX", "DEC2", "DEC2 MUX"},
+
+ {"SLIM TX3 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX3 MUX", "RMIX1", "RX1 MIX1"},
+ {"SLIM TX3 MUX", "RMIX2", "RX2 MIX1"},
+ {"SLIM TX3 MUX", "RMIX3", "RX3 MIX1"},
+ {"SLIM TX3 MUX", "RMIX4", "RX4 MIX1"},
+ {"SLIM TX3 MUX", "RMIX5", "RX5 MIX1"},
+ {"SLIM TX3 MUX", "RMIX6", "RX6 MIX1"},
+ {"SLIM TX3 MUX", "RMIX7", "RX7 MIX1"},
+
+ {"SLIM TX4 MUX", "DEC4", "DEC4 MUX"},
+
+ {"SLIM TX5 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX5 MUX", "RMIX1", "RX1 MIX1"},
+ {"SLIM TX5 MUX", "RMIX2", "RX2 MIX1"},
+ {"SLIM TX5 MUX", "RMIX3", "RX3 MIX1"},
+ {"SLIM TX5 MUX", "RMIX4", "RX4 MIX1"},
+ {"SLIM TX5 MUX", "RMIX5", "RX5 MIX1"},
+ {"SLIM TX5 MUX", "RMIX6", "RX6 MIX1"},
+ {"SLIM TX5 MUX", "RMIX7", "RX7 MIX1"},
+
+ {"SLIM TX6 MUX", "DEC6", "DEC6 MUX"},
+
+ {"SLIM TX7 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX7 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX7 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX7 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX7 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX7 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX7 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX7 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX7 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX7 MUX", "DEC10", "DEC10 MUX"},
+ {"SLIM TX7 MUX", "RMIX1", "RX1 MIX1"},
+ {"SLIM TX7 MUX", "RMIX2", "RX2 MIX1"},
+ {"SLIM TX7 MUX", "RMIX3", "RX3 MIX1"},
+ {"SLIM TX7 MUX", "RMIX4", "RX4 MIX1"},
+ {"SLIM TX7 MUX", "RMIX5", "RX5 MIX1"},
+ {"SLIM TX7 MUX", "RMIX6", "RX6 MIX1"},
+ {"SLIM TX7 MUX", "RMIX7", "RX7 MIX1"},
+
+ {"SLIM TX8 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX8 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX8 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX8 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX8 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX8 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX8 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX8 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX8 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX8 MUX", "DEC10", "DEC10 MUX"},
+
+ {"SLIM TX9 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX9 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX9 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX9 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX9 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX9 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX9 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX9 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX9 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX9 MUX", "DEC10", "DEC10 MUX"},
+
+ {"SLIM TX10 MUX", "DEC1", "DEC1 MUX"},
+ {"SLIM TX10 MUX", "DEC2", "DEC2 MUX"},
+ {"SLIM TX10 MUX", "DEC3", "DEC3 MUX"},
+ {"SLIM TX10 MUX", "DEC4", "DEC4 MUX"},
+ {"SLIM TX10 MUX", "DEC5", "DEC5 MUX"},
+ {"SLIM TX10 MUX", "DEC6", "DEC6 MUX"},
+ {"SLIM TX10 MUX", "DEC7", "DEC7 MUX"},
+ {"SLIM TX10 MUX", "DEC8", "DEC8 MUX"},
+ {"SLIM TX10 MUX", "DEC9", "DEC9 MUX"},
+ {"SLIM TX10 MUX", "DEC10", "DEC10 MUX"},
+
+ /* Earpiece (RX MIX1) */
+ {"EAR", NULL, "EAR PA"},
+ {"EAR PA", NULL, "EAR_PA_MIXER"},
+ {"EAR_PA_MIXER", NULL, "DAC1"},
+ {"DAC1", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_EAR"},
+ {"CLASS_H_EAR", NULL, "CLASS_H_CLK"},
+
+ {"ANC1 FB MUX", "EAR_HPH_L", "RX1 MIX2"},
+ {"ANC1 FB MUX", "EAR_LINE_1", "RX2 MIX2"},
+ {"ANC", NULL, "ANC1 FB MUX"},
+
+ /* Headset (RX MIX1 and RX MIX2) */
+ {"HEADPHONE", NULL, "HPHL"},
+ {"HEADPHONE", NULL, "HPHR"},
+
+ {"HPHL", NULL, "HPHL_PA_MIXER"},
+ {"HPHL_PA_MIXER", NULL, "HPHL DAC"},
+
+ {"HPHR", NULL, "HPHR_PA_MIXER"},
+ {"HPHR_PA_MIXER", NULL, "HPHR DAC"},
+
+ {"HPHL DAC", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_HPH_L"},
+ {"CLASS_H_HPH_L", NULL, "CLASS_H_CLK"},
+
+ {"HPHR DAC", NULL, "CP"},
+ {"CP", NULL, "CLASS_H_HPH_R"},
+ {"CLASS_H_HPH_R", NULL, "CLASS_H_CLK"},
+
+ {"ANC", NULL, "ANC1 MUX"},
+ {"ANC", NULL, "ANC2 MUX"},
+ {"ANC1 MUX", "ADC1", "ADC1"},
+ {"ANC1 MUX", "ADC2", "ADC2"},
+ {"ANC1 MUX", "ADC3", "ADC3"},
+ {"ANC1 MUX", "ADC4", "ADC4"},
+ {"ANC2 MUX", "ADC1", "ADC1"},
+ {"ANC2 MUX", "ADC2", "ADC2"},
+ {"ANC2 MUX", "ADC3", "ADC3"},
+ {"ANC2 MUX", "ADC4", "ADC4"},
+
+ {"ANC", NULL, "CDC_CONN"},
+
+ {"DAC1", "Switch", "RX1 CHAIN"},
+ {"HPHL DAC", "Switch", "RX1 CHAIN"},
+ {"HPHR DAC", NULL, "RX2 CHAIN"},
+
+ {"LINEOUT1", NULL, "LINEOUT1 PA"},
+ {"LINEOUT2", NULL, "LINEOUT2 PA"},
+ {"LINEOUT3", NULL, "LINEOUT3 PA"},
+ {"LINEOUT4", NULL, "LINEOUT4 PA"},
+ {"SPK_OUT", NULL, "SPK PA"},
+
+ {"LINEOUT1 PA", NULL, "CP"},
+ {"LINEOUT1 PA", NULL, "LINEOUT1_PA_MIXER"},
+ {"LINEOUT1_PA_MIXER", NULL, "LINEOUT1 DAC"},
+
+ {"LINEOUT2 PA", NULL, "CP"},
+ {"LINEOUT2 PA", NULL, "LINEOUT2_PA_MIXER"},
+ {"LINEOUT2_PA_MIXER", NULL, "LINEOUT2 DAC"},
+
+ {"LINEOUT3 PA", NULL, "CP"},
+ {"LINEOUT3 PA", NULL, "LINEOUT3_PA_MIXER"},
+ {"LINEOUT3_PA_MIXER", NULL, "LINEOUT3 DAC"},
+
+ {"LINEOUT4 PA", NULL, "CP"},
+ {"LINEOUT4 PA", NULL, "LINEOUT4_PA_MIXER"},
+ {"LINEOUT4_PA_MIXER", NULL, "LINEOUT4 DAC"},
+
+ {"CP", NULL, "CLASS_H_LINEOUTS_PA"},
+ {"CLASS_H_LINEOUTS_PA", NULL, "CLASS_H_CLK"},
+
+ {"LINEOUT1 DAC", NULL, "RX3 MIX1"},
+
+ {"RDAC5 MUX", "DEM3_INV", "RX3 MIX1"},
+ {"RDAC5 MUX", "DEM4", "RX4 MIX1"},
+
+ {"LINEOUT3 DAC", NULL, "RDAC5 MUX"},
+
+ {"LINEOUT2 DAC", NULL, "RX5 MIX1"},
+
+ {"RDAC7 MUX", "DEM5_INV", "RX5 MIX1"},
+ {"RDAC7 MUX", "DEM6", "RX6 MIX1"},
+
+ {"LINEOUT4 DAC", NULL, "RDAC7 MUX"},
+
+ {"SPK PA", NULL, "SPK DAC"},
+ {"SPK DAC", NULL, "RX7 MIX2"},
+
+ {"RX1 CHAIN", NULL, "RX1 MIX2"},
+ {"RX2 CHAIN", NULL, "RX2 MIX2"},
+ {"RX1 CHAIN", NULL, "ANC"},
+ {"RX2 CHAIN", NULL, "ANC"},
+
+ {"CLASS_H_CLK", NULL, "RX_BIAS"},
+ {"LINEOUT1 DAC", NULL, "RX_BIAS"},
+ {"LINEOUT2 DAC", NULL, "RX_BIAS"},
+ {"LINEOUT3 DAC", NULL, "RX_BIAS"},
+ {"LINEOUT4 DAC", NULL, "RX_BIAS"},
+ {"SPK DAC", NULL, "RX_BIAS"},
+
+ {"RX1 MIX1", NULL, "COMP1_CLK"},
+ {"RX2 MIX1", NULL, "COMP1_CLK"},
+ {"RX3 MIX1", NULL, "COMP2_CLK"},
+ {"RX5 MIX1", NULL, "COMP2_CLK"},
+
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
+ {"RX4 MIX1", NULL, "RX4 MIX1 INP1"},
+ {"RX4 MIX1", NULL, "RX4 MIX1 INP2"},
+ {"RX5 MIX1", NULL, "RX5 MIX1 INP1"},
+ {"RX5 MIX1", NULL, "RX5 MIX1 INP2"},
+ {"RX6 MIX1", NULL, "RX6 MIX1 INP1"},
+ {"RX6 MIX1", NULL, "RX6 MIX1 INP2"},
+ {"RX7 MIX1", NULL, "RX7 MIX1 INP1"},
+ {"RX7 MIX1", NULL, "RX7 MIX1 INP2"},
+ {"RX1 MIX2", NULL, "RX1 MIX1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP2"},
+ {"RX2 MIX2", NULL, "RX2 MIX1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP2"},
+ {"RX7 MIX2", NULL, "RX7 MIX1"},
+ {"RX7 MIX2", NULL, "RX7 MIX2 INP1"},
+ {"RX7 MIX2", NULL, "RX7 MIX2 INP2"},
+
+ /* SLIM_MUX("AIF1_PB", "AIF1 PB"),*/
+ {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
+ {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
+ /* SLIM_MUX("AIF2_PB", "AIF2 PB"),*/
+ {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
+ {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
+ /* SLIM_MUX("AIF3_PB", "AIF3 PB"),*/
+ {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
+ {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
+
+ {"SLIM RX1", NULL, "SLIM RX1 MUX"},
+ {"SLIM RX2", NULL, "SLIM RX2 MUX"},
+ {"SLIM RX3", NULL, "SLIM RX3 MUX"},
+ {"SLIM RX4", NULL, "SLIM RX4 MUX"},
+ {"SLIM RX5", NULL, "SLIM RX5 MUX"},
+ {"SLIM RX6", NULL, "SLIM RX6 MUX"},
+ {"SLIM RX7", NULL, "SLIM RX7 MUX"},
+
+ {"RX1 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX1 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX1 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX1 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX1 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX1 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX1 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX1 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX1 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX1 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX1 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX1 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX1 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX1 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX1 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP3", "RX1", "SLIM RX1"},
+ {"RX1 MIX1 INP3", "RX2", "SLIM RX2"},
+ {"RX1 MIX1 INP3", "RX3", "SLIM RX3"},
+ {"RX1 MIX1 INP3", "RX4", "SLIM RX4"},
+ {"RX1 MIX1 INP3", "RX5", "SLIM RX5"},
+ {"RX1 MIX1 INP3", "RX6", "SLIM RX6"},
+ {"RX1 MIX1 INP3", "RX7", "SLIM RX7"},
+ {"RX2 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX2 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX2 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX2 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX2 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX2 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX2 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX2 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX2 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX2 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX2 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX2 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX2 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX2 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX2 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX3 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX3 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX3 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX3 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX3 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX3 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX3 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX3 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX3 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX3 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX3 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX3 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX3 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX3 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX3 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX3 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX4 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX4 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX4 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX4 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX4 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX4 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX4 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX4 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX4 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX4 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX4 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX4 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX4 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX4 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX4 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX4 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX5 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX5 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX5 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX5 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX5 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX5 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX5 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX5 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX5 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX5 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX5 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX5 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX5 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX5 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX5 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX5 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX6 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX6 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX6 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX6 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX6 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX6 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX6 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX6 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX6 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX6 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX6 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX6 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX6 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX6 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX6 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX6 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX7 MIX1 INP1", "RX1", "SLIM RX1"},
+ {"RX7 MIX1 INP1", "RX2", "SLIM RX2"},
+ {"RX7 MIX1 INP1", "RX3", "SLIM RX3"},
+ {"RX7 MIX1 INP1", "RX4", "SLIM RX4"},
+ {"RX7 MIX1 INP1", "RX5", "SLIM RX5"},
+ {"RX7 MIX1 INP1", "RX6", "SLIM RX6"},
+ {"RX7 MIX1 INP1", "RX7", "SLIM RX7"},
+ {"RX7 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX7 MIX1 INP2", "RX1", "SLIM RX1"},
+ {"RX7 MIX1 INP2", "RX2", "SLIM RX2"},
+ {"RX7 MIX1 INP2", "RX3", "SLIM RX3"},
+ {"RX7 MIX1 INP2", "RX4", "SLIM RX4"},
+ {"RX7 MIX1 INP2", "RX5", "SLIM RX5"},
+ {"RX7 MIX1 INP2", "RX6", "SLIM RX6"},
+ {"RX7 MIX1 INP2", "RX7", "SLIM RX7"},
+ {"RX7 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX1 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX1 MIX2 INP2", "IIR1", "IIR1"},
+ {"RX2 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX2 INP2", "IIR1", "IIR1"},
+ {"RX7 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX7 MIX2 INP2", "IIR1", "IIR1"},
+
+ /* Decimator Inputs */
+ {"DEC1 MUX", "DMIC1", "DMIC1"},
+ {"DEC1 MUX", "ADC6", "ADC6"},
+ {"DEC1 MUX", NULL, "CDC_CONN"},
+ {"DEC2 MUX", "DMIC2", "DMIC2"},
+ {"DEC2 MUX", "ADC5", "ADC5"},
+ {"DEC2 MUX", NULL, "CDC_CONN"},
+ {"DEC3 MUX", "DMIC3", "DMIC3"},
+ {"DEC3 MUX", "ADC4", "ADC4"},
+ {"DEC3 MUX", NULL, "CDC_CONN"},
+ {"DEC4 MUX", "DMIC4", "DMIC4"},
+ {"DEC4 MUX", "ADC3", "ADC3"},
+ {"DEC4 MUX", NULL, "CDC_CONN"},
+ {"DEC5 MUX", "DMIC5", "DMIC5"},
+ {"DEC5 MUX", "ADC2", "ADC2"},
+ {"DEC5 MUX", NULL, "CDC_CONN"},
+ {"DEC6 MUX", "DMIC6", "DMIC6"},
+ {"DEC6 MUX", "ADC1", "ADC1"},
+ {"DEC6 MUX", NULL, "CDC_CONN"},
+ {"DEC7 MUX", "DMIC1", "DMIC1"},
+ {"DEC7 MUX", "DMIC6", "DMIC6"},
+ {"DEC7 MUX", "ADC1", "ADC1"},
+ {"DEC7 MUX", "ADC6", "ADC6"},
+ {"DEC7 MUX", NULL, "CDC_CONN"},
+ {"DEC8 MUX", "DMIC2", "DMIC2"},
+ {"DEC8 MUX", "DMIC5", "DMIC5"},
+ {"DEC8 MUX", "ADC2", "ADC2"},
+ {"DEC8 MUX", "ADC5", "ADC5"},
+ {"DEC8 MUX", NULL, "CDC_CONN"},
+ {"DEC9 MUX", "DMIC4", "DMIC4"},
+ {"DEC9 MUX", "DMIC5", "DMIC5"},
+ {"DEC9 MUX", "ADC2", "ADC2"},
+ {"DEC9 MUX", "ADC3", "ADC3"},
+ {"DEC9 MUX", NULL, "CDC_CONN"},
+ {"DEC10 MUX", "DMIC3", "DMIC3"},
+ {"DEC10 MUX", "DMIC6", "DMIC6"},
+ {"DEC10 MUX", "ADC1", "ADC1"},
+ {"DEC10 MUX", "ADC4", "ADC4"},
+ {"DEC10 MUX", NULL, "CDC_CONN"},
+
+ /* ADC Connections */
+ {"ADC1", NULL, "AMIC1"},
+ {"ADC2", NULL, "AMIC2"},
+ {"ADC3", NULL, "AMIC3"},
+ {"ADC4", NULL, "AMIC4"},
+ {"ADC5", NULL, "AMIC5"},
+ {"ADC6", NULL, "AMIC6"},
+
+ /* AUX PGA Connections */
+ {"EAR_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"HPHL_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"HPHR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"LINEOUT1_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"LINEOUT2_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"LINEOUT3_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
+ {"LINEOUT4_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
+ {"AUX_PGA_Left", NULL, "AMIC5"},
+ {"AUX_PGA_Right", NULL, "AMIC6"},
+
+ {"IIR1", NULL, "IIR1 INP1 MUX"},
+ {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
+ {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
+ {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"},
+ {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"},
+ {"IIR1 INP1 MUX", "DEC5", "DEC5 MUX"},
+ {"IIR1 INP1 MUX", "DEC6", "DEC6 MUX"},
+ {"IIR1 INP1 MUX", "DEC7", "DEC7 MUX"},
+ {"IIR1 INP1 MUX", "DEC8", "DEC8 MUX"},
+ {"IIR1 INP1 MUX", "DEC9", "DEC9 MUX"},
+ {"IIR1 INP1 MUX", "DEC10", "DEC10 MUX"},
+
+ {"MIC BIAS1 Internal1", NULL, "LDO_H"},
+ {"MIC BIAS1 Internal2", NULL, "LDO_H"},
+ {"MIC BIAS1 External", NULL, "LDO_H"},
+ {"MIC BIAS2 Internal1", NULL, "LDO_H"},
+ {"MIC BIAS2 Internal2", NULL, "LDO_H"},
+ {"MIC BIAS2 Internal3", NULL, "LDO_H"},
+ {"MIC BIAS2 External", NULL, "LDO_H"},
+ {"MIC BIAS3 Internal1", NULL, "LDO_H"},
+ {"MIC BIAS3 Internal2", NULL, "LDO_H"},
+ {"MIC BIAS3 External", NULL, "LDO_H"},
+ {"MIC BIAS4 External", NULL, "LDO_H"},
+};
+
+static int tapan_readable(struct snd_soc_codec *ssc, unsigned int reg)
+{
+ return tapan_reg_readable[reg];
+}
+
+static bool tapan_is_digital_gain_register(unsigned int reg)
+{
+ bool rtn = false;
+ switch (reg) {
+ case TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL:
+ case TAPAN_A_CDC_TX1_VOL_CTL_GAIN:
+ case TAPAN_A_CDC_TX2_VOL_CTL_GAIN:
+ case TAPAN_A_CDC_TX3_VOL_CTL_GAIN:
+ case TAPAN_A_CDC_TX4_VOL_CTL_GAIN:
+ rtn = true;
+ break;
+ default:
+ break;
+ }
+ return rtn;
+}
+
+static int tapan_volatile(struct snd_soc_codec *ssc, unsigned int reg)
+{
+ /* Registers lower than 0x100 are top level registers which can be
+ * written by the Taiko core driver.
+ */
+
+ if ((reg >= TAPAN_A_CDC_MBHC_EN_CTL) || (reg < 0x100))
+ return 1;
+
+ /* IIR Coeff registers are not cacheable */
+ if ((reg >= TAPAN_A_CDC_IIR1_COEF_B1_CTL) &&
+ (reg <= TAPAN_A_CDC_IIR2_COEF_B2_CTL))
+ return 1;
+
+ /* Digital gain register is not cacheable so we have to write
+ * the setting even it is the same
+ */
+ if (tapan_is_digital_gain_register(reg))
+ return 1;
+
+ /* HPH status registers */
+ if (reg == TAPAN_A_RX_HPH_L_STATUS || reg == TAPAN_A_RX_HPH_R_STATUS)
+ return 1;
+
+ if (reg == TAPAN_A_MBHC_INSERT_DET_STATUS)
+ return 1;
+
+ return 0;
+}
+
+#define TAPAN_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
+static int tapan_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
+{
+ int ret;
+
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > TAPAN_MAX_REGISTER);
+
+ if (!tapan_volatile(codec, reg)) {
+ ret = snd_soc_cache_write(codec, reg, value);
+ if (ret != 0)
+ dev_err(codec->dev, "Cache write to %x failed: %d\n",
+ reg, ret);
+ }
+
+ return wcd9xxx_reg_write(codec->control_data, reg, value);
+}
+static unsigned int tapan_read(struct snd_soc_codec *codec,
+ unsigned int reg)
+{
+ unsigned int val;
+ int ret;
+
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > TAPAN_MAX_REGISTER);
+
+ if (!tapan_volatile(codec, reg) && tapan_readable(codec, reg) &&
+ reg < codec->driver->reg_cache_size) {
+ ret = snd_soc_cache_read(codec, reg, &val);
+ if (ret >= 0) {
+ return val;
+ } else
+ dev_err(codec->dev, "Cache read from %x failed: %d\n",
+ reg, ret);
+ }
+
+ val = wcd9xxx_reg_read(codec->control_data, reg);
+ return val;
+}
+
+static int tapan_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct wcd9xxx *tapan_core = dev_get_drvdata(dai->codec->dev->parent);
+ dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
+ __func__, substream->name, substream->stream);
+ if ((tapan_core != NULL) &&
+ (tapan_core->dev != NULL) &&
+ (tapan_core->dev->parent != NULL))
+ pm_runtime_get_sync(tapan_core->dev->parent);
+
+ return 0;
+}
+
+static void tapan_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct wcd9xxx *tapan_core = dev_get_drvdata(dai->codec->dev->parent);
+ dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
+ __func__, substream->name, substream->stream);
+ if ((tapan_core != NULL) &&
+ (tapan_core->dev != NULL) &&
+ (tapan_core->dev->parent != NULL)) {
+ pm_runtime_mark_last_busy(tapan_core->dev->parent);
+ pm_runtime_put(tapan_core->dev->parent);
+ }
+}
+
+int tapan_mclk_enable(struct snd_soc_codec *codec, int mclk_enable, bool dapm)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n", __func__,
+ mclk_enable, dapm);
+
+ WCD9XXX_BCL_LOCK(&tapan->resmgr);
+ if (mclk_enable) {
+ wcd9xxx_resmgr_get_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ wcd9xxx_resmgr_get_clk_block(&tapan->resmgr, WCD9XXX_CLK_MCLK);
+ } else {
+ /* Put clock and BG */
+ wcd9xxx_resmgr_put_clk_block(&tapan->resmgr, WCD9XXX_CLK_MCLK);
+ wcd9xxx_resmgr_put_bandgap(&tapan->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ }
+ WCD9XXX_BCL_UNLOCK(&tapan->resmgr);
+
+ return 0;
+}
+
+static int tapan_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ dev_dbg(dai->codec->dev, "%s\n", __func__);
+ return 0;
+}
+
+static int tapan_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ return 0;
+}
+
+static int tapan_set_channel_map(struct snd_soc_dai *dai,
+ unsigned int tx_num, unsigned int *tx_slot,
+ unsigned int rx_num, unsigned int *rx_slot)
+
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(dai->codec);
+ struct wcd9xxx *core = dev_get_drvdata(dai->codec->dev->parent);
+ if (!tx_slot && !rx_slot) {
+ pr_err("%s: Invalid\n", __func__);
+ return -EINVAL;
+ }
+ dev_dbg(dai->codec->dev, "%s(): dai_name = %s DAI-ID %x\n",
+ __func__, dai->name, dai->id);
+ dev_dbg(dai->codec->dev, "%s(): tx_ch %d rx_ch %d\n intf_type %d\n",
+ __func__, tx_num, rx_num, tapan->intf_type);
+
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ wcd9xxx_init_slimslave(core, core->slim->laddr,
+ tx_num, tx_slot, rx_num, rx_slot);
+ return 0;
+}
+
+static int tapan_get_channel_map(struct snd_soc_dai *dai,
+ unsigned int *tx_num, unsigned int *tx_slot,
+ unsigned int *rx_num, unsigned int *rx_slot)
+
+{
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(dai->codec);
+ u32 i = 0;
+ struct wcd9xxx_ch *ch;
+
+ switch (dai->id) {
+ case AIF1_PB:
+ case AIF2_PB:
+ case AIF3_PB:
+ if (!rx_slot || !rx_num) {
+ pr_err("%s: Invalid rx_slot %d or rx_num %d\n",
+ __func__, (u32) rx_slot, (u32) rx_num);
+ return -EINVAL;
+ }
+ list_for_each_entry(ch, &tapan_p->dai[dai->id].wcd9xxx_ch_list,
+ list) {
+ dev_dbg(dai->codec->dev, "%s: rx_slot[%d] %d ch->ch_num %d\n",
+ __func__, i, rx_slot[i], ch->ch_num);
+ rx_slot[i++] = ch->ch_num;
+ }
+ dev_dbg(dai->codec->dev, "%s: rx_num %d\n", __func__, i);
+ *rx_num = i;
+ break;
+ case AIF1_CAP:
+ case AIF2_CAP:
+ case AIF3_CAP:
+ if (!tx_slot || !tx_num) {
+ pr_err("%s: Invalid tx_slot %d or tx_num %d\n",
+ __func__, (u32) tx_slot, (u32) tx_num);
+ return -EINVAL;
+ }
+ list_for_each_entry(ch, &tapan_p->dai[dai->id].wcd9xxx_ch_list,
+ list) {
+ dev_dbg(dai->codec->dev, "%s: tx_slot[%d] %d, ch->ch_num %d\n",
+ __func__, i, tx_slot[i], ch->ch_num);
+ tx_slot[i++] = ch->ch_num;
+ }
+ dev_dbg(dai->codec->dev, "%s: tx_num %d\n", __func__, i);
+ *tx_num = i;
+ break;
+
+ default:
+ pr_err("%s: Invalid DAI ID %x\n", __func__, dai->id);
+ break;
+ }
+
+ return 0;
+}
+
+static int tapan_set_interpolator_rate(struct snd_soc_dai *dai,
+ u8 rx_fs_rate_reg_val, u32 sample_rate)
+{
+ u32 j;
+ u8 rx_mix1_inp;
+ u16 rx_mix_1_reg_1, rx_mix_1_reg_2;
+ u16 rx_fs_reg;
+ u8 rx_mix_1_reg_1_val, rx_mix_1_reg_2_val;
+ struct snd_soc_codec *codec = dai->codec;
+ struct wcd9xxx_ch *ch;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ list_for_each_entry(ch, &tapan->dai[dai->id].wcd9xxx_ch_list, list) {
+ /* for RX port starting from 16 instead of 10 like tabla */
+ rx_mix1_inp = ch->port + RX_MIX1_INP_SEL_RX1 -
+ TAPAN_TX_PORT_NUMBER;
+ if ((rx_mix1_inp < RX_MIX1_INP_SEL_RX1) ||
+ (rx_mix1_inp > RX_MIX1_INP_SEL_RX7)) {
+ pr_err("%s: Invalid TAPAN_RX%u port. Dai ID is %d\n",
+ __func__, rx_mix1_inp - 5 , dai->id);
+ return -EINVAL;
+ }
+
+ rx_mix_1_reg_1 = TAPAN_A_CDC_CONN_RX1_B1_CTL;
+
+ for (j = 0; j < NUM_INTERPOLATORS; j++) {
+ rx_mix_1_reg_2 = rx_mix_1_reg_1 + 1;
+
+ rx_mix_1_reg_1_val = snd_soc_read(codec,
+ rx_mix_1_reg_1);
+ rx_mix_1_reg_2_val = snd_soc_read(codec,
+ rx_mix_1_reg_2);
+
+ if (((rx_mix_1_reg_1_val & 0x0F) == rx_mix1_inp) ||
+ (((rx_mix_1_reg_1_val >> 4) & 0x0F)
+ == rx_mix1_inp) ||
+ ((rx_mix_1_reg_2_val & 0x0F) == rx_mix1_inp)) {
+
+ rx_fs_reg = TAPAN_A_CDC_RX1_B5_CTL + 8 * j;
+
+ dev_dbg(codec->dev, "%s: AIF_PB DAI(%d) connected to RX%u\n",
+ __func__, dai->id, j + 1);
+
+ dev_dbg(codec->dev, "%s: set RX%u sample rate to %u\n",
+ __func__, j + 1, sample_rate);
+
+ snd_soc_update_bits(codec, rx_fs_reg,
+ 0xE0, rx_fs_rate_reg_val);
+
+ }
+ if (j <= 2)
+ rx_mix_1_reg_1 += 3;
+ else
+ rx_mix_1_reg_1 += 2;
+ }
+ }
+ return 0;
+}
+
+static int tapan_set_decimator_rate(struct snd_soc_dai *dai,
+ u8 tx_fs_rate_reg_val, u32 sample_rate)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct wcd9xxx_ch *ch;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ u32 tx_port;
+ u16 tx_port_reg, tx_fs_reg;
+ u8 tx_port_reg_val;
+ s8 decimator;
+
+ list_for_each_entry(ch, &tapan->dai[dai->id].wcd9xxx_ch_list, list) {
+
+ tx_port = ch->port + 1;
+ dev_dbg(codec->dev, "%s: dai->id = %d, tx_port = %d",
+ __func__, dai->id, tx_port);
+
+ if ((tx_port < 1) || (tx_port > NUM_DECIMATORS)) {
+ pr_err("%s: Invalid SLIM TX%u port. DAI ID is %d\n",
+ __func__, tx_port, dai->id);
+ return -EINVAL;
+ }
+
+ tx_port_reg = TAPAN_A_CDC_CONN_TX_SB_B1_CTL + (tx_port - 1);
+ tx_port_reg_val = snd_soc_read(codec, tx_port_reg);
+
+ decimator = 0;
+
+ if ((tx_port >= 1) && (tx_port <= 6)) {
+
+ tx_port_reg_val = tx_port_reg_val & 0x0F;
+ if (tx_port_reg_val == 0x8)
+ decimator = tx_port;
+
+ } else if ((tx_port >= 7) && (tx_port <= NUM_DECIMATORS)) {
+
+ tx_port_reg_val = tx_port_reg_val & 0x1F;
+
+ if ((tx_port_reg_val >= 0x8) &&
+ (tx_port_reg_val <= 0x11)) {
+
+ decimator = (tx_port_reg_val - 0x8) + 1;
+ }
+ }
+
+ if (decimator) { /* SLIM_TX port has a DEC as input */
+
+ tx_fs_reg = TAPAN_A_CDC_TX1_CLK_FS_CTL +
+ 8 * (decimator - 1);
+
+ dev_dbg(codec->dev, "%s: set DEC%u (-> SLIM_TX%u) rate to %u\n",
+ __func__, decimator, tx_port, sample_rate);
+
+ snd_soc_update_bits(codec, tx_fs_reg, 0x07,
+ tx_fs_rate_reg_val);
+
+ } else {
+ if ((tx_port_reg_val >= 0x1) &&
+ (tx_port_reg_val <= 0x7)) {
+
+ dev_dbg(codec->dev, "%s: RMIX%u going to SLIM TX%u\n",
+ __func__, tx_port_reg_val, tx_port);
+
+ } else if ((tx_port_reg_val >= 0x8) &&
+ (tx_port_reg_val <= 0x11)) {
+
+ pr_err("%s: ERROR: Should not be here\n",
+ __func__);
+ pr_err("%s: ERROR: DEC connected to SLIM TX%u\n",
+ __func__, tx_port);
+ return -EINVAL;
+
+ } else if (tx_port_reg_val == 0) {
+ dev_dbg(codec->dev, "%s: no signal to SLIM TX%u\n",
+ __func__, tx_port);
+ } else {
+ pr_err("%s: ERROR: wrong signal to SLIM TX%u\n",
+ __func__, tx_port);
+ pr_err("%s: ERROR: wrong signal = %u\n",
+ __func__, tx_port_reg_val);
+ return -EINVAL;
+ }
+ }
+ }
+ return 0;
+}
+
+static int tapan_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(dai->codec);
+ u8 tx_fs_rate, rx_fs_rate;
+ int ret;
+
+ dev_dbg(dai->codec->dev, "%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n",
+ __func__, dai->name, dai->id,
+ params_rate(params), params_channels(params));
+
+ switch (params_rate(params)) {
+ case 8000:
+ tx_fs_rate = 0x00;
+ rx_fs_rate = 0x00;
+ break;
+ case 16000:
+ tx_fs_rate = 0x01;
+ rx_fs_rate = 0x20;
+ break;
+ case 32000:
+ tx_fs_rate = 0x02;
+ rx_fs_rate = 0x40;
+ break;
+ case 48000:
+ tx_fs_rate = 0x03;
+ rx_fs_rate = 0x60;
+ break;
+ case 96000:
+ tx_fs_rate = 0x04;
+ rx_fs_rate = 0x80;
+ break;
+ case 192000:
+ tx_fs_rate = 0x05;
+ rx_fs_rate = 0xA0;
+ break;
+ default:
+ pr_err("%s: Invalid sampling rate %d\n", __func__,
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ switch (substream->stream) {
+ case SNDRV_PCM_STREAM_CAPTURE:
+ ret = tapan_set_decimator_rate(dai, tx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ pr_err("%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
+ pr_err("%s: I2C interface not yet supported\n",
+ __func__);
+ else
+ tapan->dai[dai->id].rate = params_rate(params);
+
+ break;
+
+ case SNDRV_PCM_STREAM_PLAYBACK:
+ ret = tapan_set_interpolator_rate(dai, rx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ pr_err("%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
+ pr_err("%s: I2C interface not yet supported\n",
+ __func__);
+ else
+ tapan->dai[dai->id].rate = params_rate(params);
+
+ break;
+ default:
+ pr_err("%s: Invalid stream type %d\n", __func__,
+ substream->stream);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct snd_soc_dai_ops tapan_dai_ops = {
+ .startup = tapan_startup,
+ .shutdown = tapan_shutdown,
+ .hw_params = tapan_hw_params,
+ .set_sysclk = tapan_set_dai_sysclk,
+ .set_fmt = tapan_set_dai_fmt,
+ .set_channel_map = tapan_set_channel_map,
+ .get_channel_map = tapan_get_channel_map,
+};
+
+static struct snd_soc_dai_driver tapan_dai[] = {
+ {
+ .name = "tapan_rx1",
+ .id = AIF1_PB,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_tx1",
+ .id = AIF1_CAP,
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_rx2",
+ .id = AIF2_PB,
+ .playback = {
+ .stream_name = "AIF2 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_tx2",
+ .id = AIF2_CAP,
+ .capture = {
+ .stream_name = "AIF2 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_tx3",
+ .id = AIF3_CAP,
+ .capture = {
+ .stream_name = "AIF3 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 48000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_rx3",
+ .id = AIF3_PB,
+ .playback = {
+ .stream_name = "AIF3 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 1,
+ .channels_max = 2,
+ },
+ .ops = &tapan_dai_ops,
+ },
+};
+
+static struct snd_soc_dai_driver tapan_i2s_dai[] = {
+ {
+ .name = "tapan_i2s_rx1",
+ .id = AIF1_PB,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+ {
+ .name = "tapan_i2s_tx1",
+ .id = AIF1_CAP,
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .rates = WCD9306_RATES,
+ .formats = TAPAN_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &tapan_dai_ops,
+ },
+};
+
+static int tapan_codec_enable_slimrx(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct wcd9xxx *core;
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ u32 ret = 0;
+ struct wcd9xxx_codec_dai_data *dai;
+
+ core = dev_get_drvdata(codec->dev->parent);
+
+ dev_dbg(codec->dev, "%s: event called! codec name %s\n",
+ __func__, w->codec->name);
+ dev_dbg(codec->dev, "%s: num_dai %d stream name %s event %d\n",
+ __func__, w->codec->num_dai, w->sname, event);
+
+ /* Execute the callback only if interface type is slimbus */
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ return 0;
+
+ dai = &tapan_p->dai[w->shift];
+ dev_dbg(codec->dev, "%s: w->name %s w->shift %d event %d\n",
+ __func__, w->name, w->shift, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
+ dai->rate, dai->bit_width,
+ &dai->grph);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ ret = wcd9xxx_close_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
+ dai->grph);
+ usleep_range(15000, 15000);
+ break;
+ }
+ return ret;
+}
+
+static int tapan_codec_enable_slimtx(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct wcd9xxx *core;
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan_p = snd_soc_codec_get_drvdata(codec);
+ u32 ret = 0;
+ struct wcd9xxx_codec_dai_data *dai;
+
+ core = dev_get_drvdata(codec->dev->parent);
+
+ dev_dbg(codec->dev, "%s: event called! codec name %s\n",
+ __func__, w->codec->name);
+ dev_dbg(codec->dev, "%s: num_dai %d stream name %s\n",
+ __func__, w->codec->num_dai, w->sname);
+
+ /* Execute the callback only if interface type is slimbus */
+ if (tapan_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ return 0;
+
+ dev_dbg(codec->dev, "%s(): w->name %s event %d w->shift %d\n",
+ __func__, w->name, event, w->shift);
+
+ dai = &tapan_p->dai[w->shift];
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
+ dai->rate, dai->bit_width,
+ &dai->grph);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
+ dai->grph);
+ break;
+ }
+ return ret;
+}
+
+static int tapan_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+
+ dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+
+ case SND_SOC_DAPM_POST_PMU:
+
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_5, 0x02, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_NCP_STATIC, 0x20, 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x04, 0x04);
+ snd_soc_update_bits(codec, TAPAN_A_BUCK_MODE_3, 0x08, 0x00);
+
+ usleep_range(5000, 5000);
+ break;
+ }
+ return 0;
+}
+
+/* Todo: Have seperate dapm widgets for I2S and Slimbus.
+ * Might Need to have callbacks registered only for slimbus
+ */
+static const struct snd_soc_dapm_widget tapan_dapm_widgets[] = {
+ /*RX stuff */
+ SND_SOC_DAPM_OUTPUT("EAR"),
+
+ SND_SOC_DAPM_PGA_E("EAR PA", TAPAN_A_RX_EAR_EN, 4, 0, NULL, 0,
+ tapan_codec_enable_ear_pa, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_MIXER("DAC1", TAPAN_A_RX_EAR_EN, 6, 0, dac1_switch,
+ ARRAY_SIZE(dac1_switch)),
+
+ SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
+ AIF1_PB, 0, tapan_codec_enable_slimrx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
+ AIF2_PB, 0, tapan_codec_enable_slimrx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
+ AIF3_PB, 0, tapan_codec_enable_slimrx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, TAPAN_RX1, 0,
+ &slim_rx_mux[TAPAN_RX1]),
+ SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, TAPAN_RX2, 0,
+ &slim_rx_mux[TAPAN_RX2]),
+ SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, TAPAN_RX3, 0,
+ &slim_rx_mux[TAPAN_RX3]),
+ SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, TAPAN_RX4, 0,
+ &slim_rx_mux[TAPAN_RX4]),
+ SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, TAPAN_RX5, 0,
+ &slim_rx_mux[TAPAN_RX5]),
+
+ SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ /* Headphone */
+ SND_SOC_DAPM_OUTPUT("HEADPHONE"),
+ SND_SOC_DAPM_PGA_E("HPHL", TAPAN_A_RX_HPH_CNP_EN, 5, 0, NULL, 0,
+ tapan_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER("HPHL DAC", TAPAN_A_RX_HPH_L_DAC_CTL, 7, 0,
+ hphl_switch, ARRAY_SIZE(hphl_switch)),
+
+ SND_SOC_DAPM_PGA_E("HPHR", TAPAN_A_RX_HPH_CNP_EN, 4, 0, NULL, 0,
+ tapan_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("HPHR DAC", NULL, TAPAN_A_RX_HPH_R_DAC_CTL, 7, 0,
+ tapan_hphr_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /* Speaker */
+ SND_SOC_DAPM_OUTPUT("LINEOUT1"),
+ SND_SOC_DAPM_OUTPUT("LINEOUT2"),
+ SND_SOC_DAPM_OUTPUT("SPK_OUT"),
+
+ SND_SOC_DAPM_PGA_E("LINEOUT1 PA", TAPAN_A_RX_LINE_CNP_EN, 0, 0, NULL,
+ 0, tapan_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_PGA_E("LINEOUT2 PA", TAPAN_A_RX_LINE_CNP_EN, 1, 0, NULL,
+ 0, tapan_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_PGA_E("SPK PA", TAPAN_A_SPKR_DRV_EN, 7, 0 , NULL,
+ 0, tapan_codec_enable_spk_pa, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("LINEOUT1 DAC", NULL, TAPAN_A_RX_LINE_1_DAC_CTL, 7, 0
+ , tapan_lineout_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_DAC_E("LINEOUT2 DAC", NULL, TAPAN_A_RX_LINE_2_DAC_CTL, 7, 0
+ , tapan_lineout_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_DAC_E("SPK DAC", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_spk_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+ SND_SOC_DAPM_MIXER_E("RX1 MIX2", TAPAN_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX2 MIX2", TAPAN_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX3 MIX1", TAPAN_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX4 MIX1", TAPAN_A_CDC_CLK_RX_B1_CTL, 3, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_MIXER_E("RX5 MIX1", TAPAN_A_CDC_CLK_RX_B1_CTL, 4, 0, NULL,
+ 0, tapan_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_MIXER("RX1 CHAIN", TAPAN_A_CDC_RX1_B6_CTL, 5, 0, NULL, 0),
+ SND_SOC_DAPM_MIXER("RX2 CHAIN", TAPAN_A_CDC_RX2_B6_CTL, 5, 0, NULL, 0),
+
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp3_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX4 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx4_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX4 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx4_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP2", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp2_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp2_mux),
+
+ SND_SOC_DAPM_MUX("RDAC5 MUX", SND_SOC_NOPM, 0, 0,
+ &rx_dac5_mux),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_CLK", TAPAN_A_CDC_CLK_OTHR_CTL, 0, 0,
+ tapan_codec_enable_class_h_clk, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_PRE_PMD),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_EAR", TAPAN_A_CDC_CLSH_B1_CTL, 4, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_HPH_L", TAPAN_A_CDC_CLSH_B1_CTL, 3, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_HPH_R", TAPAN_A_CDC_CLSH_B1_CTL, 2, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CLASS_H_LINEOUTS_PA", SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_class_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_SUPPLY("CP", TAPAN_A_NCP_EN, 0, 0,
+ tapan_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+ SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* TX */
+
+ SND_SOC_DAPM_SUPPLY("CDC_CONN", TAPAN_A_CDC_CLK_OTHR_CTL, 2, 0, NULL,
+ 0),
+
+ SND_SOC_DAPM_SUPPLY("LDO_H", TAPAN_A_LDO_H_MODE_1, 7, 0,
+ tapan_codec_enable_ldo_h, SND_SOC_DAPM_POST_PMU),
+
+ SND_SOC_DAPM_INPUT("AMIC1"),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 External", TAPAN_A_MICB_1_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal1", TAPAN_A_MICB_1_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal2", TAPAN_A_MICB_1_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_INPUT("AMIC3"),
+
+ SND_SOC_DAPM_INPUT("AMIC4"),
+
+ SND_SOC_DAPM_INPUT("AMIC5"),
+
+ SND_SOC_DAPM_MUX_E("DEC1 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
+ &dec1_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX_E("DEC2 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
+ &dec2_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX_E("DEC3 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 2, 0,
+ &dec3_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX_E("DEC4 MUX", TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL, 3, 0,
+ &dec4_mux, tapan_codec_enable_dec,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER_E("ANC", SND_SOC_NOPM, 0, 0, NULL, 0,
+ tapan_codec_enable_anc, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_INPUT("AMIC2"),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 External", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal1", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal2", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal3", TAPAN_A_MICB_2_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 External", TAPAN_A_MICB_3_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal1", TAPAN_A_MICB_3_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal2", TAPAN_A_MICB_3_CTL, 7, 0,
+ tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
+ AIF1_CAP, 0, tapan_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
+ AIF2_CAP, 0, tapan_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
+ AIF3_CAP, 0, tapan_codec_enable_slimtx,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
+ aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
+
+ SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
+ aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
+
+ SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
+ aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
+
+ SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, TAPAN_TX1, 0,
+ &sb_tx1_mux),
+ SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, TAPAN_TX2, 0,
+ &sb_tx2_mux),
+ SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, TAPAN_TX3, 0,
+ &sb_tx3_mux),
+ SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, TAPAN_TX4, 0,
+ &sb_tx4_mux),
+
+ /* Digital Mic Inputs */
+ SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
+ tapan_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* Sidetone */
+ SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
+ SND_SOC_DAPM_PGA("IIR1", TAPAN_A_CDC_CLK_SD_CTL, 0, 0, NULL, 0),
+
+ /* AUX PGA */
+ SND_SOC_DAPM_ADC_E("AUX_PGA_Left", NULL, TAPAN_A_RX_AUX_SW_CTL, 7, 0,
+ tapan_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_ADC_E("AUX_PGA_Right", NULL, TAPAN_A_RX_AUX_SW_CTL, 6, 0,
+ tapan_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ /* Lineout, ear and HPH PA Mixers */
+
+ SND_SOC_DAPM_MIXER("EAR_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ ear_pa_mix, ARRAY_SIZE(ear_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("HPHL_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ hphl_pa_mix, ARRAY_SIZE(hphl_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("HPHR_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ hphr_pa_mix, ARRAY_SIZE(hphr_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("LINEOUT1_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ lineout1_pa_mix, ARRAY_SIZE(lineout1_pa_mix)),
+
+ SND_SOC_DAPM_MIXER("LINEOUT2_PA_MIXER", SND_SOC_NOPM, 0, 0,
+ lineout2_pa_mix, ARRAY_SIZE(lineout2_pa_mix)),
+
+};
+
+static unsigned long slimbus_value;
+
+static irqreturn_t tapan_slimbus_irq(int irq, void *data)
+{
+ struct tapan_priv *priv = data;
+ struct snd_soc_codec *codec = priv->codec;
+ int i, j;
+ u8 val;
+
+ for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++) {
+ slimbus_value = wcd9xxx_interface_reg_read(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_STATUS0 + i);
+ for_each_set_bit(j, &slimbus_value, BITS_PER_BYTE) {
+ val = wcd9xxx_interface_reg_read(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_SOURCE0 + i*8 + j);
+ if (val & 0x1)
+ pr_err_ratelimited(
+ "overflow error on port %x, value %x\n",
+ i*8 + j, val);
+ if (val & 0x2)
+ pr_err_ratelimited(
+ "underflow error on port %x, value %x\n",
+ i*8 + j, val);
+ }
+ wcd9xxx_interface_reg_write(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_CLR0 + i, 0xFF);
+
+ }
+ return IRQ_HANDLED;
+}
+
+static const struct tapan_reg_mask_val tapan_1_0_class_h_ear[] = {
+
+ /* CLASS-H EAR IDLE_THRESHOLD Table */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_IDLE_EAR_THSD, 0x26),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD, 0x2C),
+
+ /* CLASS-H EAR I_PA_FACT Table. */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L, 0xA9),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U, 0x07),
+
+ /* CLASS-H EAR Voltage Headroom , Voltage Min. */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_HD_EAR, 0x0D),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_MIN_EAR, 0x3A),
+
+ /* CLASS-H EAR K values --chnages from load. */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_ADDR, 0x08),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x1B),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x2D),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x36),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x37),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ /** end of Ear PA load 32 */
+};
+
+static const struct tapan_reg_mask_val tapan_1_0_class_h_hph[] = {
+
+ /* CLASS-H HPH IDLE_THRESHOLD Table */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_IDLE_HPH_THSD, 0x13),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD, 0x19),
+
+ /* CLASS-H HPH I_PA_FACT Table */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L, 0x9A),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U, 0x06),
+
+ /* CLASS-H HPH Voltage Headroom , Voltage Min */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_HD_HPH, 0x0D),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_V_PA_MIN_HPH, 0x1D),
+
+ /* CLASS-H HPH K values --chnages from load .*/
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_ADDR, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0xAE),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x01),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x1C),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x25),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x27),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_K_DATA, 0x00),
+};
+
+static int tapan_config_ear_class_h(struct snd_soc_codec *codec, u32 ear_load)
+{
+ u32 i;
+
+ if (ear_load != 32)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_1_0_class_h_ear); i++)
+ snd_soc_write(codec, tapan_1_0_class_h_ear[i].reg,
+ tapan_1_0_class_h_ear[i].val);
+ return 0;
+}
+
+static int tapan_config_hph_class_h(struct snd_soc_codec *codec, u32 hph_load)
+{
+ u32 i;
+ if (hph_load != 16)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_1_0_class_h_hph); i++)
+ snd_soc_write(codec, tapan_1_0_class_h_hph[i].reg,
+ tapan_1_0_class_h_hph[i].val);
+ return 0;
+}
+
+static int tapan_handle_pdata(struct tapan_priv *tapan)
+{
+ struct snd_soc_codec *codec = tapan->codec;
+ struct wcd9xxx_pdata *pdata = tapan->resmgr.pdata;
+ int k1, k2, k3, rc = 0;
+ u8 leg_mode, txfe_bypass, txfe_buff, flag;
+ u8 value = 0;
+
+ if (!pdata) {
+ pr_err("%s: NULL pdata\n", __func__);
+ rc = -ENODEV;
+ goto done;
+ }
+
+ leg_mode = pdata->amic_settings.legacy_mode;
+ txfe_bypass = pdata->amic_settings.txfe_enable;
+ txfe_buff = pdata->amic_settings.txfe_buff;
+ flag = pdata->amic_settings.use_pdata;
+
+ /* Make sure settings are correct */
+ if ((pdata->micbias.ldoh_v > WCD9XXX_LDOH_3P0_V) ||
+ (pdata->micbias.bias1_cfilt_sel > WCD9XXX_CFILT3_SEL) ||
+ (pdata->micbias.bias2_cfilt_sel > WCD9XXX_CFILT3_SEL) ||
+ (pdata->micbias.bias3_cfilt_sel > WCD9XXX_CFILT3_SEL)) {
+ rc = -EINVAL;
+ goto done;
+ }
+ /* figure out k value */
+ k1 = wcd9xxx_resmgr_get_k_val(&tapan->resmgr, pdata->micbias.cfilt1_mv);
+ k2 = wcd9xxx_resmgr_get_k_val(&tapan->resmgr, pdata->micbias.cfilt2_mv);
+ k3 = wcd9xxx_resmgr_get_k_val(&tapan->resmgr, pdata->micbias.cfilt3_mv);
+
+ if (IS_ERR_VALUE(k1) || IS_ERR_VALUE(k2) || IS_ERR_VALUE(k3)) {
+ rc = -EINVAL;
+ goto done;
+ }
+ /* Set voltage level and always use LDO */
+ snd_soc_update_bits(codec, TAPAN_A_LDO_H_MODE_1, 0x0C,
+ (pdata->micbias.ldoh_v << 2));
+
+ snd_soc_update_bits(codec, TAPAN_A_MICB_CFILT_1_VAL, 0xFC, (k1 << 2));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_CFILT_2_VAL, 0xFC, (k2 << 2));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_CFILT_3_VAL, 0xFC, (k3 << 2));
+
+ snd_soc_update_bits(codec, TAPAN_A_MICB_1_CTL, 0x60,
+ (pdata->micbias.bias1_cfilt_sel << 5));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_2_CTL, 0x60,
+ (pdata->micbias.bias2_cfilt_sel << 5));
+ snd_soc_update_bits(codec, TAPAN_A_MICB_3_CTL, 0x60,
+ (pdata->micbias.bias3_cfilt_sel << 5));
+
+ if (flag & 0x40) {
+ value = (leg_mode & 0x40) ? 0x10 : 0x00;
+ value = value | ((txfe_bypass & 0x40) ? 0x02 : 0x00);
+ value = value | ((txfe_buff & 0x40) ? 0x01 : 0x00);
+ snd_soc_update_bits(codec, TAPAN_A_TX_7_MBHC_EN,
+ 0x13, value);
+ }
+
+ if (pdata->ocp.use_pdata) {
+ /* not defined in CODEC specification */
+ if (pdata->ocp.hph_ocp_limit == 1 ||
+ pdata->ocp.hph_ocp_limit == 5) {
+ rc = -EINVAL;
+ goto done;
+ }
+ snd_soc_update_bits(codec, TAPAN_A_RX_COM_OCP_CTL,
+ 0x0F, pdata->ocp.num_attempts);
+ snd_soc_write(codec, TAPAN_A_RX_COM_OCP_COUNT,
+ ((pdata->ocp.run_time << 4) | pdata->ocp.wait_time));
+ snd_soc_update_bits(codec, TAPAN_A_RX_HPH_OCP_CTL,
+ 0xE0, (pdata->ocp.hph_ocp_limit << 5));
+ }
+
+ tapan_config_ear_class_h(codec, 32);
+ tapan_config_hph_class_h(codec, 16);
+
+done:
+ return rc;
+}
+
+static const struct tapan_reg_mask_val tapan_reg_defaults[] = {
+
+ /* set MCLk to 9.6 */
+ TAPAN_REG_VAL(TAPAN_A_CHIP_CTL, 0x0A),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLK_POWER_CTL, 0x03),
+
+ /* EAR PA deafults */
+ TAPAN_REG_VAL(TAPAN_A_RX_EAR_CMBUFF, 0x05),
+
+ /** BUCK and NCP defaults for EAR and HS */
+ TAPAN_REG_VAL(TAPAN_A_BUCK_CTRL_CCL_4, 0x50),
+ TAPAN_REG_VAL(TAPAN_A_BUCK_CTRL_CCL_1, 0x5B),
+
+ /* CLASS-H defaults for EAR and HS */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_BUCK_NCP_VARS, 0x00),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_BUCK_NCP_VARS, 0x04),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B2_CTL, 0x01),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B2_CTL, 0x05),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B2_CTL, 0x35),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B3_CTL, 0x30),
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B3_CTL, 0x3B),
+
+ /*
+ * For CLASS-H, Enable ANC delay buffer,
+ * set HPHL and EAR PA ref gain to 0 DB.
+ */
+ TAPAN_REG_VAL(TAPAN_A_CDC_CLSH_B1_CTL, 0x26),
+
+ /* RX deafults */
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX1_B5_CTL, 0x78),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX2_B5_CTL, 0x78),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX3_B5_CTL, 0x78),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX4_B5_CTL, 0x78),
+
+ /* RX1 and RX2 defaults */
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX1_B6_CTL, 0xA0),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX2_B6_CTL, 0xA0),
+
+ /* RX3 to RX7 defaults */
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX3_B6_CTL, 0x80),
+ TAPAN_REG_VAL(TAPAN_A_CDC_RX4_B6_CTL, 0x80),
+
+ /*
+ * The following only need to be written for Taiko 1.0 parts.
+ * Taiko 2.0 will have appropriate defaults for these registers.
+ */
+ /* Choose max non-overlap time for NCP */
+ TAPAN_REG_VAL(TAPAN_A_NCP_CLK, 0xFC),
+ /* Use 25mV/50mV for deltap/m to reduce ripple */
+ TAPAN_REG_VAL(TAPAN_A_BUCK_CTRL_VCL_1, 0x08),
+ /*
+ * Set DISABLE_MODE_SEL<1:0> to 0b10 (disable PWM in auto mode).
+ * Note that the other bits of this register will be changed during
+ * Rx PA bring up.
+ */
+ TAPAN_REG_VAL(TAPAN_A_BUCK_MODE_3, 0xCE),
+ /* Reduce HPH DAC bias to 70% */
+ TAPAN_REG_VAL(TAPAN_A_RX_HPH_BIAS_PA, 0x7A),
+ /*Reduce EAR DAC bias to 70% */
+ TAPAN_REG_VAL(TAPAN_A_RX_EAR_BIAS_PA, 0x76),
+ /* Reduce LINE DAC bias to 70% */
+ TAPAN_REG_VAL(TAPAN_A_RX_LINE_BIAS_PA, 0x78),
+
+ /*
+ * There is a diode to pull down the micbias while doing
+ * insertion detection. This diode can cause leakage.
+ * Set bit 0 to 1 to prevent leakage.
+ * Setting this bit of micbias 2 prevents leakage for all other micbias.
+ */
+ TAPAN_REG_VAL(TAPAN_A_MICB_2_MBHC, 0x41),
+
+ /* Disable TX7 internal biasing path which can cause leakage */
+ TAPAN_REG_VAL(TAPAN_A_TX_SUP_SWITCH_CTRL_1, 0xBF),
+};
+
+static void tapan_update_reg_defaults(struct snd_soc_codec *codec)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_reg_defaults); i++)
+ snd_soc_write(codec, tapan_reg_defaults[i].reg,
+ tapan_reg_defaults[i].val);
+}
+
+static const struct tapan_reg_mask_val tapan_codec_reg_init_val[] = {
+ /* Initialize current threshold to 350MA
+ * number of wait and run cycles to 4096
+ */
+ {TAPAN_A_RX_HPH_OCP_CTL, 0xE1, 0x61},
+ {TAPAN_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
+
+ /* Initialize gain registers to use register gain */
+ {TAPAN_A_RX_HPH_L_GAIN, 0x20, 0x20},
+ {TAPAN_A_RX_HPH_R_GAIN, 0x20, 0x20},
+ {TAPAN_A_RX_LINE_1_GAIN, 0x20, 0x20},
+ {TAPAN_A_RX_LINE_2_GAIN, 0x20, 0x20},
+
+ /* CLASS H config */
+ {TAPAN_A_CDC_CONN_CLSH_CTL, 0x3C, 0x14},
+
+ /* Use 16 bit sample size for TX1 to TX6 */
+ {TAPAN_A_CDC_CONN_TX_SB_B1_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B2_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B3_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B4_CTL, 0x30, 0x20},
+ {TAPAN_A_CDC_CONN_TX_SB_B5_CTL, 0x30, 0x20},
+
+ /* Use 16 bit sample size for RX */
+ {TAPAN_A_CDC_CONN_RX_SB_B1_CTL, 0xFF, 0xAA},
+ {TAPAN_A_CDC_CONN_RX_SB_B2_CTL, 0xFF, 0x2A},
+
+ /*enable HPF filter for TX paths */
+ {TAPAN_A_CDC_TX1_MUX_CTL, 0x8, 0x0},
+ {TAPAN_A_CDC_TX2_MUX_CTL, 0x8, 0x0},
+ {TAPAN_A_CDC_TX3_MUX_CTL, 0x8, 0x0},
+ {TAPAN_A_CDC_TX4_MUX_CTL, 0x8, 0x0},
+
+ /* config Decimator for DMIC CLK_MODE_1(3.2Mhz@9.6Mhz mclk) */
+ {TAPAN_A_CDC_TX1_DMIC_CTL, 0x7, 0x1},
+ {TAPAN_A_CDC_TX2_DMIC_CTL, 0x7, 0x1},
+ {TAPAN_A_CDC_TX3_DMIC_CTL, 0x7, 0x1},
+ {TAPAN_A_CDC_TX4_DMIC_CTL, 0x7, 0x1},
+
+ /* config DMIC clk to CLK_MODE_1 (3.2Mhz@9.6Mhz mclk) */
+ {TAPAN_A_CDC_CLK_DMIC_B1_CTL, 0xEE, 0x22},
+ {TAPAN_A_CDC_CLK_DMIC_B2_CTL, 0x0E, 0x02},
+
+};
+
+static void tapan_codec_init_reg(struct snd_soc_codec *codec)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(tapan_codec_reg_init_val); i++)
+ snd_soc_update_bits(codec, tapan_codec_reg_init_val[i].reg,
+ tapan_codec_reg_init_val[i].mask,
+ tapan_codec_reg_init_val[i].val);
+}
+
+static int tapan_setup_irqs(struct tapan_priv *tapan)
+{
+ int i;
+ int ret = 0;
+ struct snd_soc_codec *codec = tapan->codec;
+
+ ret = wcd9xxx_request_irq(codec->control_data, WCD9XXX_IRQ_SLIMBUS,
+ tapan_slimbus_irq, "SLIMBUS Slave", tapan);
+ if (ret) {
+ pr_err("%s: Failed to request irq %d\n", __func__,
+ WCD9XXX_IRQ_SLIMBUS);
+ goto exit;
+ }
+
+ for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++)
+ wcd9xxx_interface_reg_write(codec->control_data,
+ TAPAN_SLIM_PGD_PORT_INT_EN0 + i,
+ 0xFF);
+exit:
+ return ret;
+}
+
+int tapan_hs_detect(struct snd_soc_codec *codec,
+ struct wcd9xxx_mbhc_config *mbhc_cfg)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+ return wcd9xxx_mbhc_start(&tapan->mbhc, mbhc_cfg);
+}
+EXPORT_SYMBOL_GPL(tapan_hs_detect);
+
+static struct wcd9xxx_reg_address tapan_reg_address = {
+};
+
+static int tapan_codec_probe(struct snd_soc_codec *codec)
+{
+ struct wcd9xxx *control;
+ struct tapan_priv *tapan;
+ struct wcd9xxx_pdata *pdata;
+ struct wcd9xxx *wcd9xxx;
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ int ret = 0;
+ int i;
+ void *ptr = NULL;
+
+ codec->control_data = dev_get_drvdata(codec->dev->parent);
+ control = codec->control_data;
+
+ dev_info(codec->dev, "%s()\n", __func__);
+
+ tapan = kzalloc(sizeof(struct tapan_priv), GFP_KERNEL);
+ if (!tapan) {
+ dev_err(codec->dev, "Failed to allocate private data\n");
+ return -ENOMEM;
+ }
+ for (i = 0 ; i < NUM_DECIMATORS; i++) {
+ tx_hpf_work[i].tapan = tapan;
+ tx_hpf_work[i].decimator = i + 1;
+ INIT_DELAYED_WORK(&tx_hpf_work[i].dwork,
+ tx_hpf_corner_freq_callback);
+ }
+
+ snd_soc_codec_set_drvdata(codec, tapan);
+
+ /* codec resmgr module init */
+ wcd9xxx = codec->control_data;
+ pdata = dev_get_platdata(codec->dev->parent);
+ ret = wcd9xxx_resmgr_init(&tapan->resmgr, codec, wcd9xxx, pdata,
+ &tapan_reg_address);
+ if (ret) {
+ pr_err("%s: wcd9xxx init failed %d\n", __func__, ret);
+ goto err_codec;
+ }
+
+ /* init and start mbhc */
+ ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec);
+ if (ret) {
+ pr_err("%s: mbhc init failed %d\n", __func__, ret);
+ goto err_codec;
+ }
+
+ tapan->codec = codec;
+
+ tapan->intf_type = wcd9xxx_get_intf_type();
+ tapan->aux_pga_cnt = 0;
+ tapan->aux_l_gain = 0x1F;
+ tapan->aux_r_gain = 0x1F;
+ tapan_update_reg_defaults(codec);
+ tapan_codec_init_reg(codec);
+ ret = tapan_handle_pdata(tapan);
+ if (IS_ERR_VALUE(ret)) {
+ pr_err("%s: bad pdata\n", __func__);
+ goto err_codec;
+ }
+
+ ptr = kmalloc((sizeof(tapan_rx_chs) +
+ sizeof(tapan_tx_chs)), GFP_KERNEL);
+ if (!ptr) {
+ pr_err("%s: no mem for slim chan ctl data\n", __func__);
+ ret = -ENOMEM;
+ goto err_nomem_slimch;
+ }
+
+ if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
+ pr_err("%s: I2C interface not supported yet\n",
+ __func__);
+ } else if (tapan->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ for (i = 0; i < NUM_CODEC_DAIS; i++) {
+ INIT_LIST_HEAD(&tapan->dai[i].wcd9xxx_ch_list);
+ init_waitqueue_head(&tapan->dai[i].dai_wait);
+ }
+ }
+
+ control->num_rx_port = TAPAN_RX_MAX;
+ control->rx_chs = ptr;
+ memcpy(control->rx_chs, tapan_rx_chs, sizeof(tapan_rx_chs));
+ control->num_tx_port = TAPAN_TX_MAX;
+ control->tx_chs = ptr + sizeof(tapan_rx_chs);
+ memcpy(control->tx_chs, tapan_tx_chs, sizeof(tapan_tx_chs));
+
+ snd_soc_dapm_sync(dapm);
+
+ (void) tapan_setup_irqs(tapan);
+
+ codec->ignore_pmdown_time = 1;
+ return ret;
+
+err_nomem_slimch:
+ kfree(ptr);
+err_codec:
+ kfree(tapan);
+ return ret;
+}
+
+static int tapan_codec_remove(struct snd_soc_codec *codec)
+{
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
+
+ /* cleanup MBHC */
+ wcd9xxx_mbhc_deinit(&tapan->mbhc);
+ /* cleanup resmgr */
+ wcd9xxx_resmgr_deinit(&tapan->resmgr);
+
+ kfree(tapan);
+ return 0;
+}
+
+static struct snd_soc_codec_driver soc_codec_dev_tapan = {
+ .probe = tapan_codec_probe,
+ .remove = tapan_codec_remove,
+
+ .read = tapan_read,
+ .write = tapan_write,
+
+ .readable_register = tapan_readable,
+ .volatile_register = tapan_volatile,
+
+ .reg_cache_size = TAPAN_CACHE_SIZE,
+ .reg_cache_default = tapan_reset_reg_defaults,
+ .reg_word_size = 1,
+
+ .controls = tapan_snd_controls,
+ .num_controls = ARRAY_SIZE(tapan_snd_controls),
+ .dapm_widgets = tapan_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(tapan_dapm_widgets),
+ .dapm_routes = audio_map,
+ .num_dapm_routes = ARRAY_SIZE(audio_map),
+};
+
+#ifdef CONFIG_PM
+static int tapan_suspend(struct device *dev)
+{
+ dev_dbg(dev, "%s: system suspend\n", __func__);
+ return 0;
+}
+
+static int tapan_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct tapan_priv *tapan = platform_get_drvdata(pdev);
+ dev_dbg(dev, "%s: system resume\n", __func__);
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr, WCD9XXX_EVENT_POST_RESUME);
+ return 0;
+}
+
+static const struct dev_pm_ops tapan_pm_ops = {
+ .suspend = tapan_suspend,
+ .resume = tapan_resume,
+};
+#endif
+
+static int __devinit tapan_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tapan,
+ tapan_dai, ARRAY_SIZE(tapan_dai));
+ else if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
+ ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tapan,
+ tapan_i2s_dai, ARRAY_SIZE(tapan_i2s_dai));
+ return ret;
+}
+static int __devexit tapan_remove(struct platform_device *pdev)
+{
+ snd_soc_unregister_codec(&pdev->dev);
+ return 0;
+}
+static struct platform_driver tapan_codec_driver = {
+ .probe = tapan_probe,
+ .remove = tapan_remove,
+ .driver = {
+ .name = "tapan_codec",
+ .owner = THIS_MODULE,
+#ifdef CONFIG_PM
+ .pm = &tapan_pm_ops,
+#endif
+ },
+};
+
+static int __init tapan_codec_init(void)
+{
+ return platform_driver_register(&tapan_codec_driver);
+}
+
+static void __exit tapan_codec_exit(void)
+{
+ platform_driver_unregister(&tapan_codec_driver);
+}
+
+module_init(tapan_codec_init);
+module_exit(tapan_codec_exit);
+
+MODULE_DESCRIPTION("Tapan codec driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/wcd9306.h b/sound/soc/codecs/wcd9306.h
new file mode 100644
index 0000000..61d47b5
--- /dev/null
+++ b/sound/soc/codecs/wcd9306.h
@@ -0,0 +1,84 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef WCD9306_H
+#define WCD9306_H
+
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-slimslave.h>
+#include "wcd9xxx-mbhc.h"
+#include "wcd9xxx-resmgr.h"
+
+#define TAPAN_NUM_REGISTERS 0x400
+#define TAPAN_MAX_REGISTER (TAPAN_NUM_REGISTERS-1)
+#define TAPAN_CACHE_SIZE TAPAN_NUM_REGISTERS
+
+#define TAPAN_REG_VAL(reg, val) {reg, 0, val}
+
+extern const u8 tapan_reg_readable[TAPAN_CACHE_SIZE];
+extern const u8 tapan_reset_reg_defaults[TAPAN_CACHE_SIZE];
+struct tapan_codec_dai_data {
+ u32 rate;
+ u32 *ch_num;
+ u32 ch_act;
+ u32 ch_tot;
+};
+
+enum tapan_pid_current {
+ TAPAN_PID_MIC_2P5_UA,
+ TAPAN_PID_MIC_5_UA,
+ TAPAN_PID_MIC_10_UA,
+ TAPAN_PID_MIC_20_UA,
+};
+
+struct tapan_reg_mask_val {
+ u16 reg;
+ u8 mask;
+ u8 val;
+};
+
+enum tapan_mbhc_analog_pwr_cfg {
+ TAPAN_ANALOG_PWR_COLLAPSED = 0,
+ TAPAN_ANALOG_PWR_ON,
+ TAPAN_NUM_ANALOG_PWR_CONFIGS,
+};
+
+/* Number of input and output Slimbus port */
+enum {
+ TAPAN_RX1 = 0,
+ TAPAN_RX2,
+ TAPAN_RX3,
+ TAPAN_RX4,
+ TAPAN_RX5,
+ TAPAN_RX_MAX,
+};
+
+enum {
+ TAPAN_TX1 = 0,
+ TAPAN_TX2,
+ TAPAN_TX3,
+ TAPAN_TX4,
+ TAPAN_TX5,
+ TAPAN_TX_MAX,
+};
+
+struct anc_header {
+ u32 reserved[3];
+ u32 num_anc_slots;
+};
+
+extern int tapan_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
+ bool dapm);
+extern int tapan_hs_detect(struct snd_soc_codec *codec,
+ struct wcd9xxx_mbhc_config *mbhc_cfg);
+
+#endif
diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig
index ee4a3f3..20b9d2d 100644
--- a/sound/soc/msm/Kconfig
+++ b/sound/soc/msm/Kconfig
@@ -107,7 +107,7 @@
config SND_SOC_MSM_QDSP6V2_INTF
bool "SoC Q6 audio driver for MSM8974"
- depends on MSM_QDSP6_APRV2
+ depends on MSM_QDSP6_APR
help
To add support for SoC audio on MSM8974.
This will enable all the platform specific