| commit | 34246055036bcbf9f4db0c84a19fe4010add7e4b | [log] [tgz] |
|---|---|---|
| author | Chandan Uddaraju <chandanu@codeaurora.org> | Thu Sep 12 10:17:41 2013 -0700 |
| committer | Kuogee Hsieh <khsieh@codeaurora.org> | Fri Jan 31 13:39:08 2014 -0800 |
| tree | 6464a62e34fbfe250c4dba35d52a3ecb18440bc8 | |
| parent | 1c3d54e97551b2c87c68d18165a4e23da86a4b9c [diff] |
msm: mdss: dsi-1 as master clock controller at split display case During split display case, both dsi controllers share the same dsi pll(dsi0) dsi-0 clock need to be enabled before dsi-1 and disabled in the reverse order. This mechanism helps using a unified clock control logic. Change-Id: I9fe0095b0427c9c2b7fd84c3179bc8364049cce4 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>